1 /* 2 * (C) Copyright 2012 SAMSUNG Electronics 3 * Jaehoon Chung <jh80.chung@samsung.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <dm.h> 10 #include <malloc.h> 11 #include <sdhci.h> 12 #include <fdtdec.h> 13 #include <libfdt.h> 14 #include <asm/gpio.h> 15 #include <asm/arch/mmc.h> 16 #include <asm/arch/clk.h> 17 #include <errno.h> 18 #include <asm/arch/pinmux.h> 19 20 #ifdef CONFIG_DM_MMC 21 struct s5p_sdhci_plat { 22 struct mmc_config cfg; 23 struct mmc mmc; 24 }; 25 26 DECLARE_GLOBAL_DATA_PTR; 27 #endif 28 29 static char *S5P_NAME = "SAMSUNG SDHCI"; 30 static void s5p_sdhci_set_control_reg(struct sdhci_host *host) 31 { 32 unsigned long val, ctrl; 33 /* 34 * SELCLKPADDS[17:16] 35 * 00 = 2mA 36 * 01 = 4mA 37 * 10 = 7mA 38 * 11 = 9mA 39 */ 40 sdhci_writel(host, SDHCI_CTRL4_DRIVE_MASK(0x3), SDHCI_CONTROL4); 41 42 val = sdhci_readl(host, SDHCI_CONTROL2); 43 val &= SDHCI_CTRL2_SELBASECLK_MASK(3); 44 45 val |= SDHCI_CTRL2_ENSTAASYNCCLR | 46 SDHCI_CTRL2_ENCMDCNFMSK | 47 SDHCI_CTRL2_ENFBCLKRX | 48 SDHCI_CTRL2_ENCLKOUTHOLD; 49 50 sdhci_writel(host, val, SDHCI_CONTROL2); 51 52 /* 53 * FCSEL3[31] FCSEL2[23] FCSEL1[15] FCSEL0[7] 54 * FCSel[1:0] : Rx Feedback Clock Delay Control 55 * Inverter delay means10ns delay if SDCLK 50MHz setting 56 * 01 = Delay1 (basic delay) 57 * 11 = Delay2 (basic delay + 2ns) 58 * 00 = Delay3 (inverter delay) 59 * 10 = Delay4 (inverter delay + 2ns) 60 */ 61 val = SDHCI_CTRL3_FCSEL0 | SDHCI_CTRL3_FCSEL1; 62 sdhci_writel(host, val, SDHCI_CONTROL3); 63 64 /* 65 * SELBASECLK[5:4] 66 * 00/01 = HCLK 67 * 10 = EPLL 68 * 11 = XTI or XEXTCLK 69 */ 70 ctrl = sdhci_readl(host, SDHCI_CONTROL2); 71 ctrl &= ~SDHCI_CTRL2_SELBASECLK_MASK(0x3); 72 ctrl |= SDHCI_CTRL2_SELBASECLK_MASK(0x2); 73 sdhci_writel(host, ctrl, SDHCI_CONTROL2); 74 } 75 76 static void s5p_set_clock(struct sdhci_host *host, u32 div) 77 { 78 /* ToDo : Use the Clock Framework */ 79 set_mmc_clk(host->index, div); 80 } 81 82 static int s5p_sdhci_core_init(struct sdhci_host *host) 83 { 84 host->name = S5P_NAME; 85 86 host->quirks = SDHCI_QUIRK_NO_HISPD_BIT | SDHCI_QUIRK_BROKEN_VOLTAGE | 87 SDHCI_QUIRK_32BIT_DMA_ADDR | 88 SDHCI_QUIRK_WAIT_SEND_CMD | SDHCI_QUIRK_USE_WIDE8; 89 host->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; 90 91 host->set_control_reg = &s5p_sdhci_set_control_reg; 92 host->set_clock = &s5p_set_clock; 93 94 if (host->bus_width == 8) 95 host->host_caps |= MMC_MODE_8BIT; 96 97 #ifndef CONFIG_BLK 98 return add_sdhci(host, 52000000, 400000); 99 #else 100 return 0; 101 #endif 102 } 103 104 int s5p_sdhci_init(u32 regbase, int index, int bus_width) 105 { 106 struct sdhci_host *host = calloc(1, sizeof(struct sdhci_host)); 107 if (!host) { 108 printf("sdhci__host allocation fail!\n"); 109 return -ENOMEM; 110 } 111 host->ioaddr = (void *)regbase; 112 host->index = index; 113 host->bus_width = bus_width; 114 115 return s5p_sdhci_core_init(host); 116 } 117 118 #if CONFIG_IS_ENABLED(OF_CONTROL) 119 struct sdhci_host sdhci_host[SDHCI_MAX_HOSTS]; 120 121 static int do_sdhci_init(struct sdhci_host *host) 122 { 123 int dev_id, flag, ret; 124 125 flag = host->bus_width == 8 ? PINMUX_FLAG_8BIT_MODE : PINMUX_FLAG_NONE; 126 dev_id = host->index + PERIPH_ID_SDMMC0; 127 128 ret = exynos_pinmux_config(dev_id, flag); 129 if (ret) { 130 printf("external SD not configured\n"); 131 return ret; 132 } 133 134 if (dm_gpio_is_valid(&host->pwr_gpio)) { 135 dm_gpio_set_value(&host->pwr_gpio, 1); 136 ret = exynos_pinmux_config(dev_id, flag); 137 if (ret) { 138 debug("MMC not configured\n"); 139 return ret; 140 } 141 } 142 143 if (dm_gpio_is_valid(&host->cd_gpio)) { 144 ret = dm_gpio_get_value(&host->cd_gpio); 145 if (ret) { 146 debug("no SD card detected (%d)\n", ret); 147 return -ENODEV; 148 } 149 } 150 151 return s5p_sdhci_core_init(host); 152 } 153 154 static int sdhci_get_config(const void *blob, int node, struct sdhci_host *host) 155 { 156 int bus_width, dev_id; 157 unsigned int base; 158 159 /* Get device id */ 160 dev_id = pinmux_decode_periph_id(blob, node); 161 if (dev_id < PERIPH_ID_SDMMC0 || dev_id > PERIPH_ID_SDMMC3) { 162 debug("MMC: Can't get device id\n"); 163 return -EINVAL; 164 } 165 host->index = dev_id - PERIPH_ID_SDMMC0; 166 167 /* Get bus width */ 168 bus_width = fdtdec_get_int(blob, node, "samsung,bus-width", 0); 169 if (bus_width <= 0) { 170 debug("MMC: Can't get bus-width\n"); 171 return -EINVAL; 172 } 173 host->bus_width = bus_width; 174 175 /* Get the base address from the device node */ 176 base = fdtdec_get_addr(blob, node, "reg"); 177 if (!base) { 178 debug("MMC: Can't get base address\n"); 179 return -EINVAL; 180 } 181 host->ioaddr = (void *)base; 182 183 gpio_request_by_name_nodev(blob, node, "pwr-gpios", 0, &host->pwr_gpio, 184 GPIOD_IS_OUT); 185 gpio_request_by_name_nodev(blob, node, "cd-gpios", 0, &host->cd_gpio, 186 GPIOD_IS_IN); 187 188 return 0; 189 } 190 191 static int process_nodes(const void *blob, int node_list[], int count) 192 { 193 struct sdhci_host *host; 194 int i, node, ret; 195 int failed = 0; 196 197 debug("%s: count = %d\n", __func__, count); 198 199 /* build sdhci_host[] for each controller */ 200 for (i = 0; i < count; i++) { 201 node = node_list[i]; 202 if (node <= 0) 203 continue; 204 205 host = &sdhci_host[i]; 206 207 ret = sdhci_get_config(blob, node, host); 208 if (ret) { 209 printf("%s: failed to decode dev %d (%d)\n", __func__, i, ret); 210 failed++; 211 continue; 212 } 213 214 ret = do_sdhci_init(host); 215 if (ret && ret != -ENODEV) { 216 printf("%s: failed to initialize dev %d (%d)\n", __func__, i, ret); 217 failed++; 218 } 219 } 220 221 /* we only consider it an error when all nodes fail */ 222 return (failed == count ? -1 : 0); 223 } 224 225 int exynos_mmc_init(const void *blob) 226 { 227 int count; 228 int node_list[SDHCI_MAX_HOSTS]; 229 230 count = fdtdec_find_aliases_for_id(blob, "mmc", 231 COMPAT_SAMSUNG_EXYNOS_MMC, node_list, 232 SDHCI_MAX_HOSTS); 233 234 return process_nodes(blob, node_list, count); 235 } 236 #endif 237 238 #ifdef CONFIG_DM_MMC 239 static int s5p_sdhci_probe(struct udevice *dev) 240 { 241 struct s5p_sdhci_plat *plat = dev_get_platdata(dev); 242 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); 243 struct sdhci_host *host = dev_get_priv(dev); 244 int ret; 245 246 ret = sdhci_get_config(gd->fdt_blob, dev->of_offset, host); 247 if (ret) 248 return ret; 249 250 ret = do_sdhci_init(host); 251 if (ret) 252 return ret; 253 254 ret = sdhci_setup_cfg(&plat->cfg, host, 52000000, 400000); 255 if (ret) 256 return ret; 257 258 host->mmc = &plat->mmc; 259 host->mmc->priv = host; 260 host->mmc->dev = dev; 261 upriv->mmc = host->mmc; 262 263 return sdhci_probe(dev); 264 } 265 266 static int s5p_sdhci_bind(struct udevice *dev) 267 { 268 struct s5p_sdhci_plat *plat = dev_get_platdata(dev); 269 int ret; 270 271 ret = sdhci_bind(dev, &plat->mmc, &plat->cfg); 272 if (ret) 273 return ret; 274 275 return 0; 276 } 277 278 static const struct udevice_id s5p_sdhci_ids[] = { 279 { .compatible = "samsung,exynos4412-sdhci"}, 280 { } 281 }; 282 283 U_BOOT_DRIVER(s5p_sdhci_drv) = { 284 .name = "s5p_sdhci", 285 .id = UCLASS_MMC, 286 .of_match = s5p_sdhci_ids, 287 .bind = s5p_sdhci_bind, 288 .ops = &sdhci_ops, 289 .probe = s5p_sdhci_probe, 290 .priv_auto_alloc_size = sizeof(struct sdhci_host), 291 .platdata_auto_alloc_size = sizeof(struct s5p_sdhci_plat), 292 }; 293 #endif /* CONFIG_DM_MMC */ 294