1 /* 2 * Copyright (c) 2013 Google, Inc 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <clk.h> 9 #include <dm.h> 10 #include <dt-structs.h> 11 #include <dwmmc.h> 12 #include <errno.h> 13 #include <mapmem.h> 14 #include <pwrseq.h> 15 #include <syscon.h> 16 #include <asm/gpio.h> 17 #include <asm/arch/clock.h> 18 #include <asm/arch/periph.h> 19 #include <linux/err.h> 20 21 DECLARE_GLOBAL_DATA_PTR; 22 23 #define USRID_INTER_PHASE 0x20230001 24 #define SDMMC_TIMING_CON0 0x130 25 #define SDMMC_TIMING_CON1 0x134 26 #define ROCKCHIP_MMC_DELAY_SEL BIT(10) 27 #define ROCKCHIP_MMC_DEGREE_MASK 0x3 28 #define ROCKCHIP_MMC_DELAYNUM_OFFSET 2 29 #define ROCKCHIP_MMC_DELAYNUM_MASK (0xff << ROCKCHIP_MMC_DELAYNUM_OFFSET) 30 #define PSECS_PER_SEC 1000000000000LL 31 #define ROCKCHIP_MMC_DELAY_ELEMENT_PSEC 60 32 #define HIWORD_UPDATE(val, mask, shift) \ 33 ((val) << (shift) | (mask) << ((shift) + 16)) 34 35 struct rockchip_mmc_plat { 36 #if CONFIG_IS_ENABLED(OF_PLATDATA) 37 struct dtd_rockchip_rk3288_dw_mshc dtplat; 38 #endif 39 struct mmc_config cfg; 40 struct mmc mmc; 41 }; 42 43 struct rockchip_dwmmc_priv { 44 struct clk clk; 45 struct clk sample_clk; 46 struct dwmci_host host; 47 int fifo_depth; 48 bool fifo_mode; 49 int usrid; 50 u32 minmax[2]; 51 }; 52 53 #ifdef CONFIG_USING_KERNEL_DTB 54 int board_mmc_dm_reinit(struct udevice *dev) 55 { 56 struct rockchip_dwmmc_priv *priv = dev_get_priv(dev); 57 58 if (!priv) 59 return 0; 60 61 if (!memcmp(dev->name, "dwmmc", strlen("dwmmc"))) 62 return clk_get_by_index(dev, 0, &priv->clk); 63 else 64 return 0; 65 } 66 #endif 67 68 #ifdef CONFIG_SPL_BUILD 69 __weak void mmc_gpio_init_direct(void) {} 70 #endif 71 72 /* 73 * Each fine delay is between 44ps-77ps. Assume each fine delay is 60ps to 74 * simplify calculations. So 45degs could be anywhere between 33deg and 57.8deg. 75 */ 76 static int rockchip_mmc_get_phase(struct dwmci_host *host, bool sample) 77 { 78 struct udevice *dev = host->priv; 79 struct rockchip_dwmmc_priv *priv = dev_get_priv(dev); 80 unsigned long rate = clk_get_rate(&priv->clk); 81 u32 raw_value; 82 u16 degrees; 83 u32 delay_num = 0; 84 85 /* Constant signal, no measurable phase shift */ 86 if (!rate) 87 return 0; 88 89 if (sample) 90 raw_value = dwmci_readl(host, SDMMC_TIMING_CON1) >> 1; 91 else 92 raw_value = dwmci_readl(host, SDMMC_TIMING_CON0) >> 1; 93 94 degrees = (raw_value & ROCKCHIP_MMC_DEGREE_MASK) * 90; 95 if (raw_value & ROCKCHIP_MMC_DELAY_SEL) { 96 /* degrees/delaynum * 1000000 */ 97 unsigned long factor = (ROCKCHIP_MMC_DELAY_ELEMENT_PSEC / 10) * 36 * (rate / 10000); 98 99 delay_num = (raw_value & ROCKCHIP_MMC_DELAYNUM_MASK); 100 delay_num >>= ROCKCHIP_MMC_DELAYNUM_OFFSET; 101 degrees += DIV_ROUND_CLOSEST(delay_num * factor, 1000000); 102 } 103 return degrees % 360; 104 } 105 106 static int rockchip_mmc_set_phase(struct dwmci_host *host, bool sample, int degrees) 107 { 108 struct udevice *dev = host->priv; 109 struct rockchip_dwmmc_priv *priv = dev_get_priv(dev); 110 unsigned long rate = clk_get_rate(&priv->clk); 111 u8 nineties, remainder; 112 u8 delay_num; 113 u32 raw_value; 114 u32 delay; 115 116 /* 117 * The below calculation is based on the output clock from 118 * MMC host to the card, which expects the phase clock inherits 119 * the clock rate from its parent, namely the output clock 120 * provider of MMC host. However, things may go wrong if 121 * (1) It is orphan. 122 * (2) It is assigned to the wrong parent. 123 * 124 * This check help debug the case (1), which seems to be the 125 * most likely problem we often face and which makes it difficult 126 * for people to debug unstable mmc tuning results. 127 */ 128 if (!rate) { 129 printf("%s: invalid clk rate\n", __func__); 130 return -EINVAL; 131 } 132 133 nineties = degrees / 90; 134 remainder = (degrees % 90); 135 136 /* 137 * Due to the inexact nature of the "fine" delay, we might 138 * actually go non-monotonic. We don't go _too_ monotonic 139 * though, so we should be OK. Here are options of how we may 140 * work: 141 * 142 * Ideally we end up with: 143 * 1.0, 2.0, ..., 69.0, 70.0, ..., 89.0, 90.0 144 * 145 * On one extreme (if delay is actually 44ps): 146 * .73, 1.5, ..., 50.6, 51.3, ..., 65.3, 90.0 147 * The other (if delay is actually 77ps): 148 * 1.3, 2.6, ..., 88.6. 89.8, ..., 114.0, 90 149 * 150 * It's possible we might make a delay that is up to 25 151 * degrees off from what we think we're making. That's OK 152 * though because we should be REALLY far from any bad range. 153 */ 154 155 /* 156 * Convert to delay; do a little extra work to make sure we 157 * don't overflow 32-bit / 64-bit numbers. 158 */ 159 delay = 10000000; /* PSECS_PER_SEC / 10000 / 10 */ 160 delay *= remainder; 161 delay = DIV_ROUND_CLOSEST(delay, 162 (rate / 1000) * 36 * 163 (ROCKCHIP_MMC_DELAY_ELEMENT_PSEC / 10)); 164 165 delay_num = (u8) min_t(u32, delay, 255); 166 167 raw_value = delay_num ? ROCKCHIP_MMC_DELAY_SEL : 0; 168 raw_value |= delay_num << ROCKCHIP_MMC_DELAYNUM_OFFSET; 169 raw_value |= nineties; 170 171 if (sample) 172 dwmci_writel(host, SDMMC_TIMING_CON1, HIWORD_UPDATE(raw_value, 0x07ff, 1)); 173 else 174 dwmci_writel(host, SDMMC_TIMING_CON1, HIWORD_UPDATE(raw_value, 0x07ff, 1)); 175 176 debug("set %s_phase(%d) delay_nums=%u actual_degrees=%d\n", 177 sample ? "sample" : "drv", degrees, delay_num, 178 rockchip_mmc_get_phase(host, sample) 179 ); 180 181 return 0; 182 } 183 184 static uint rockchip_dwmmc_get_mmc_clk(struct dwmci_host *host, uint freq) 185 { 186 struct udevice *dev = host->priv; 187 struct rockchip_dwmmc_priv *priv = dev_get_priv(dev); 188 int ret; 189 190 /* 191 * If DDR52 8bit mode(only emmc work in 8bit mode), 192 * divider must be set 1 193 */ 194 if (mmc_card_ddr52(host->mmc) && host->mmc->bus_width == 8) 195 freq *= 2; 196 197 ret = clk_set_rate(&priv->clk, freq); 198 if (ret < 0) { 199 debug("%s: err=%d\n", __func__, ret); 200 return 0; 201 } 202 203 return freq; 204 } 205 206 static int rockchip_dwmmc_ofdata_to_platdata(struct udevice *dev) 207 { 208 #if !CONFIG_IS_ENABLED(OF_PLATDATA) 209 struct rockchip_dwmmc_priv *priv = dev_get_priv(dev); 210 struct dwmci_host *host = &priv->host; 211 212 host->name = dev->name; 213 host->ioaddr = dev_read_addr_ptr(dev); 214 host->buswidth = dev_read_u32_default(dev, "bus-width", 4); 215 host->get_mmc_clk = rockchip_dwmmc_get_mmc_clk; 216 host->priv = dev; 217 218 /* use non-removeable as sdcard and emmc as judgement */ 219 if (dev_read_bool(dev, "non-removable")) 220 host->dev_index = 0; 221 else 222 host->dev_index = 1; 223 224 priv->fifo_depth = dev_read_u32_default(dev, "fifo-depth", 0); 225 226 if (priv->fifo_depth < 0) 227 return -EINVAL; 228 priv->fifo_mode = dev_read_bool(dev, "fifo-mode"); 229 230 /* 231 * 'clock-freq-min-max' is deprecated 232 * (see https://github.com/torvalds/linux/commit/b023030f10573de738bbe8df63d43acab64c9f7b) 233 */ 234 if (dev_read_u32_array(dev, "clock-freq-min-max", priv->minmax, 2)) { 235 int val = dev_read_u32_default(dev, "max-frequency", -EINVAL); 236 237 if (val < 0) 238 return val; 239 240 priv->minmax[0] = 400000; /* 400 kHz */ 241 priv->minmax[1] = val; 242 } else { 243 debug("%s: 'clock-freq-min-max' property was deprecated.\n", 244 __func__); 245 } 246 #endif 247 return 0; 248 } 249 250 #ifndef CONFIG_MMC_SIMPLE 251 #define NUM_PHASES 32 252 #define TUNING_ITERATION_TO_PHASE(i, num_phases) (DIV_ROUND_UP((i) * 360, num_phases)) 253 254 static int rockchip_dwmmc_execute_tuning(struct dwmci_host *host, u32 opcode) 255 { 256 struct mmc *mmc = host->mmc; 257 struct udevice *dev = host->priv; 258 struct rockchip_dwmmc_priv *priv = dev_get_priv(dev); 259 int ret = 0; 260 int i, num_phases = NUM_PHASES; 261 bool v, prev_v = 0, first_v; 262 struct range_t { 263 short start; 264 short end; /* inclusive */ 265 }; 266 struct range_t ranges[NUM_PHASES / 2 + 1]; 267 unsigned int range_count = 0; 268 int longest_range_len = -1; 269 int longest_range = -1; 270 int middle_phase, real_middle_phase; 271 ulong ts; 272 273 if (IS_ERR(&priv->sample_clk)) 274 return -EIO; 275 ts = get_timer(0); 276 277 /* Try each phase and extract good ranges */ 278 for (i = 0; i < num_phases; ) { 279 /* Cannot guarantee any phases larger than 270 would work well */ 280 if (TUNING_ITERATION_TO_PHASE(i, num_phases) > 270) 281 break; 282 if (priv->usrid == USRID_INTER_PHASE) 283 rockchip_mmc_set_phase(host, true, TUNING_ITERATION_TO_PHASE(i, num_phases)); 284 else 285 clk_set_phase(&priv->sample_clk, TUNING_ITERATION_TO_PHASE(i, num_phases)); 286 287 v = !mmc_send_tuning(mmc, opcode); 288 debug("3 Tuning phase is %d v = %x\n", TUNING_ITERATION_TO_PHASE(i, num_phases), v); 289 if (i == 0) 290 first_v = v; 291 292 if ((!prev_v) && v) { 293 range_count++; 294 ranges[range_count - 1].start = i; 295 } 296 297 if (v) 298 ranges[range_count - 1].end = i; 299 i++; 300 prev_v = v; 301 } 302 303 if (range_count == 0) { 304 dev_warn(host->dev, "All phases bad!"); 305 return -EIO; 306 } 307 308 /* wrap around case, merge the end points */ 309 if ((range_count > 1) && first_v && v) { 310 ranges[0].start = ranges[range_count - 1].start; 311 range_count--; 312 } 313 314 /* Find the longest range */ 315 for (i = 0; i < range_count; i++) { 316 int len = (ranges[i].end - ranges[i].start + 1); 317 318 if (len < 0) 319 len += num_phases; 320 321 if (longest_range_len < len) { 322 longest_range_len = len; 323 longest_range = i; 324 } 325 326 debug("Good phase range %d-%d (%d len)\n", 327 TUNING_ITERATION_TO_PHASE(ranges[i].start, num_phases), 328 TUNING_ITERATION_TO_PHASE(ranges[i].end, num_phases), 329 len); 330 } 331 332 printf("Best phase range %d-%d (%d len)\n", 333 TUNING_ITERATION_TO_PHASE(ranges[longest_range].start, num_phases), 334 TUNING_ITERATION_TO_PHASE(ranges[longest_range].end, num_phases), 335 longest_range_len); 336 337 middle_phase = ranges[longest_range].start + longest_range_len / 2; 338 middle_phase %= num_phases; 339 real_middle_phase = TUNING_ITERATION_TO_PHASE(middle_phase, num_phases); 340 341 /* 342 * Since we cut out 270 ~ 360, the original algorithm 343 * still rolling ranges before and after 270 together 344 * in some corner cases, we should adjust it to avoid 345 * using any middle phase located between 270 and 360. 346 * By calculatiion, it happends due to the bad phases 347 * lay between 90 ~ 180. So others are all fine to chose. 348 * Pick 270 is a better choice in those cases. In case of 349 * bad phases exceed 180, the middle phase of rollback 350 * would be bigger than 315, so we chose 360. 351 */ 352 if (real_middle_phase > 270) { 353 if (real_middle_phase < 315) 354 real_middle_phase = 270; 355 else 356 real_middle_phase = 0; 357 } 358 359 printf("Successfully tuned phase to %d, used %ldms\n", real_middle_phase, get_timer(0) - ts); 360 361 if (priv->usrid == USRID_INTER_PHASE) 362 rockchip_mmc_set_phase(host, true, real_middle_phase); 363 else 364 clk_set_phase(&priv->sample_clk, real_middle_phase); 365 366 return ret; 367 } 368 #else 369 static int rockchip_dwmmc_execute_tuning(struct dwmci_host *host, u32 opcode) { return 0; } 370 #endif 371 372 static int rockchip_dwmmc_probe(struct udevice *dev) 373 { 374 struct rockchip_mmc_plat *plat = dev_get_platdata(dev); 375 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); 376 struct rockchip_dwmmc_priv *priv = dev_get_priv(dev); 377 struct dwmci_host *host = &priv->host; 378 struct udevice *pwr_dev __maybe_unused; 379 int ret; 380 381 #ifdef CONFIG_SPL_BUILD 382 mmc_gpio_init_direct(); 383 #endif 384 #if CONFIG_IS_ENABLED(OF_PLATDATA) 385 struct dtd_rockchip_rk3288_dw_mshc *dtplat = &plat->dtplat; 386 387 host->name = dev->name; 388 host->ioaddr = map_sysmem(dtplat->reg[0], dtplat->reg[1]); 389 host->buswidth = dtplat->bus_width; 390 host->get_mmc_clk = rockchip_dwmmc_get_mmc_clk; 391 host->execute_tuning = rockchip_dwmmc_execute_tuning; 392 host->priv = dev; 393 host->dev_index = 0; 394 priv->fifo_depth = dtplat->fifo_depth; 395 priv->fifo_mode = 0; 396 priv->minmax[0] = 400000; /* 400 kHz */ 397 priv->minmax[1] = dtplat->max_frequency; 398 399 ret = clk_get_by_index_platdata(dev, 0, dtplat->clocks, &priv->clk); 400 if (ret < 0) 401 return ret; 402 #else 403 ret = clk_get_by_index(dev, 0, &priv->clk); 404 if (ret < 0) 405 return ret; 406 407 priv->usrid = dwmci_readl(host, DWMCI_USRID); 408 if (priv->usrid == USRID_INTER_PHASE) 409 goto internal_phase; 410 411 ret = clk_get_by_name(dev, "ciu-sample", &priv->sample_clk); 412 if (ret < 0) 413 debug("MMC: sample clock not found, not support hs200!\n"); 414 internal_phase: 415 host->execute_tuning = rockchip_dwmmc_execute_tuning; 416 #endif 417 host->fifoth_val = MSIZE(DWMCI_MSIZE) | 418 RX_WMARK(priv->fifo_depth / 2 - 1) | 419 TX_WMARK(priv->fifo_depth / 2); 420 421 host->fifo_mode = priv->fifo_mode; 422 423 #ifdef CONFIG_ROCKCHIP_RK3128 424 host->stride_pio = true; 425 #else 426 host->stride_pio = false; 427 #endif 428 429 #ifdef CONFIG_PWRSEQ 430 /* Enable power if needed */ 431 ret = uclass_get_device_by_phandle(UCLASS_PWRSEQ, dev, "mmc-pwrseq", 432 &pwr_dev); 433 if (!ret) { 434 ret = pwrseq_set_power(pwr_dev, true); 435 if (ret) 436 return ret; 437 } 438 #endif 439 dwmci_setup_cfg(&plat->cfg, host, priv->minmax[1], priv->minmax[0]); 440 if (dev_read_bool(dev, "mmc-hs200-1_8v")) 441 plat->cfg.host_caps |= MMC_MODE_HS200; 442 plat->mmc.default_phase = 443 dev_read_u32_default(dev, "default-sample-phase", 0); 444 #ifdef CONFIG_ROCKCHIP_RV1106 445 if (!(ret < 0) && (&priv->sample_clk)) { 446 ret = clk_set_phase(&priv->sample_clk, plat->mmc.default_phase); 447 if (ret < 0) 448 debug("MMC: can not set default phase!\n"); 449 } 450 #endif 451 452 plat->mmc.init_retry = 0; 453 host->mmc = &plat->mmc; 454 host->mmc->priv = &priv->host; 455 host->mmc->dev = dev; 456 upriv->mmc = host->mmc; 457 458 return dwmci_probe(dev); 459 } 460 461 static int rockchip_dwmmc_bind(struct udevice *dev) 462 { 463 struct rockchip_mmc_plat *plat = dev_get_platdata(dev); 464 465 return dwmci_bind(dev, &plat->mmc, &plat->cfg); 466 } 467 468 static const struct udevice_id rockchip_dwmmc_ids[] = { 469 { .compatible = "rockchip,rk3288-dw-mshc" }, 470 { .compatible = "rockchip,rk2928-dw-mshc" }, 471 { } 472 }; 473 474 U_BOOT_DRIVER(rockchip_dwmmc_drv) = { 475 .name = "rockchip_rk3288_dw_mshc", 476 .id = UCLASS_MMC, 477 .of_match = rockchip_dwmmc_ids, 478 .ofdata_to_platdata = rockchip_dwmmc_ofdata_to_platdata, 479 .ops = &dm_dwmci_ops, 480 .bind = rockchip_dwmmc_bind, 481 .probe = rockchip_dwmmc_probe, 482 .priv_auto_alloc_size = sizeof(struct rockchip_dwmmc_priv), 483 .platdata_auto_alloc_size = sizeof(struct rockchip_mmc_plat), 484 }; 485 486 #ifdef CONFIG_PWRSEQ 487 static int rockchip_dwmmc_pwrseq_set_power(struct udevice *dev, bool enable) 488 { 489 struct gpio_desc reset; 490 int ret; 491 492 ret = gpio_request_by_name(dev, "reset-gpios", 0, &reset, GPIOD_IS_OUT); 493 if (ret) 494 return ret; 495 dm_gpio_set_value(&reset, 1); 496 udelay(1); 497 dm_gpio_set_value(&reset, 0); 498 udelay(200); 499 500 return 0; 501 } 502 503 static const struct pwrseq_ops rockchip_dwmmc_pwrseq_ops = { 504 .set_power = rockchip_dwmmc_pwrseq_set_power, 505 }; 506 507 static const struct udevice_id rockchip_dwmmc_pwrseq_ids[] = { 508 { .compatible = "mmc-pwrseq-emmc" }, 509 { } 510 }; 511 512 U_BOOT_DRIVER(rockchip_dwmmc_pwrseq_drv) = { 513 .name = "mmc_pwrseq_emmc", 514 .id = UCLASS_PWRSEQ, 515 .of_match = rockchip_dwmmc_pwrseq_ids, 516 .ops = &rockchip_dwmmc_pwrseq_ops, 517 }; 518 #endif 519