1 /* 2 * Copyright (c) 2013 Google, Inc 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <clk.h> 9 #include <dm.h> 10 #include <dt-structs.h> 11 #include <dwmmc.h> 12 #include <errno.h> 13 #include <mapmem.h> 14 #include <pwrseq.h> 15 #include <syscon.h> 16 #include <asm/gpio.h> 17 #include <asm/arch/clock.h> 18 #include <asm/arch/periph.h> 19 #include <linux/err.h> 20 21 DECLARE_GLOBAL_DATA_PTR; 22 23 struct rockchip_mmc_plat { 24 #if CONFIG_IS_ENABLED(OF_PLATDATA) 25 struct dtd_rockchip_rk3288_dw_mshc dtplat; 26 #endif 27 struct mmc_config cfg; 28 struct mmc mmc; 29 }; 30 31 struct rockchip_dwmmc_priv { 32 struct clk clk; 33 struct clk sample_clk; 34 struct dwmci_host host; 35 int fifo_depth; 36 bool fifo_mode; 37 u32 minmax[2]; 38 }; 39 40 static uint rockchip_dwmmc_get_mmc_clk(struct dwmci_host *host, uint freq) 41 { 42 struct udevice *dev = host->priv; 43 struct rockchip_dwmmc_priv *priv = dev_get_priv(dev); 44 int ret; 45 46 /* 47 * If DDR52 8bit mode(only emmc work in 8bit mode), 48 * divider must be set 1 49 */ 50 if (mmc_card_ddr52(host->mmc) && host->mmc->bus_width == 8) 51 freq *= 2; 52 53 ret = clk_set_rate(&priv->clk, freq); 54 if (ret < 0) { 55 debug("%s: err=%d\n", __func__, ret); 56 return ret; 57 } 58 59 return freq; 60 } 61 62 static int rockchip_dwmmc_ofdata_to_platdata(struct udevice *dev) 63 { 64 #if !CONFIG_IS_ENABLED(OF_PLATDATA) 65 struct rockchip_dwmmc_priv *priv = dev_get_priv(dev); 66 struct dwmci_host *host = &priv->host; 67 68 host->name = dev->name; 69 host->ioaddr = dev_read_addr_ptr(dev); 70 host->buswidth = dev_read_u32_default(dev, "bus-width", 4); 71 host->get_mmc_clk = rockchip_dwmmc_get_mmc_clk; 72 host->priv = dev; 73 74 /* use non-removeable as sdcard and emmc as judgement */ 75 if (dev_read_bool(dev, "non-removable")) 76 host->dev_index = 0; 77 else 78 host->dev_index = 1; 79 80 priv->fifo_depth = dev_read_u32_default(dev, "fifo-depth", 0); 81 82 if (priv->fifo_depth < 0) 83 return -EINVAL; 84 priv->fifo_mode = dev_read_bool(dev, "fifo-mode"); 85 86 /* 87 * 'clock-freq-min-max' is deprecated 88 * (see https://github.com/torvalds/linux/commit/b023030f10573de738bbe8df63d43acab64c9f7b) 89 */ 90 if (dev_read_u32_array(dev, "clock-freq-min-max", priv->minmax, 2)) { 91 int val = dev_read_u32_default(dev, "max-frequency", -EINVAL); 92 93 if (val < 0) 94 return val; 95 96 priv->minmax[0] = 400000; /* 400 kHz */ 97 priv->minmax[1] = val; 98 } else { 99 debug("%s: 'clock-freq-min-max' property was deprecated.\n", 100 __func__); 101 } 102 #endif 103 return 0; 104 } 105 106 static int rockchip_dwmmc_execute_tuning(struct dwmci_host *host, u32 opcode) 107 { 108 int i = 0; 109 int ret = -1; 110 struct mmc *mmc = host->mmc; 111 struct udevice *dev = host->priv; 112 struct rockchip_dwmmc_priv *priv = dev_get_priv(dev); 113 114 if (IS_ERR(&priv->sample_clk)) 115 return -EIO; 116 117 if (mmc->default_phase > 0 && mmc->default_phase < 360) { 118 ret = clk_set_phase(&priv->sample_clk, mmc->default_phase); 119 if (ret) 120 printf("set clk phase fail\n"); 121 else 122 ret = mmc_send_tuning(mmc, opcode); 123 mmc->default_phase = 0; 124 } 125 /* 126 * If use default_phase to tune successfully, return. 127 * Otherwise, use the othe phase to tune. 128 */ 129 if (!ret) 130 return ret; 131 132 for (i = 0; i < 5; i++) { 133 /* mmc->init_retry must be 0, 1, 2, 3 */ 134 if (mmc->init_retry == 4) 135 mmc->init_retry = 0; 136 137 ret = clk_set_phase(&priv->sample_clk, 90 * mmc->init_retry); 138 if (ret) { 139 printf("set clk phase fail\n"); 140 break; 141 } 142 ret = mmc_send_tuning(mmc, opcode); 143 debug("Tuning phase is %d, ret is %d\n", mmc->init_retry * 90, ret); 144 mmc->init_retry++; 145 if (!ret) 146 break; 147 } 148 149 return ret; 150 } 151 152 static int rockchip_dwmmc_probe(struct udevice *dev) 153 { 154 struct rockchip_mmc_plat *plat = dev_get_platdata(dev); 155 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); 156 struct rockchip_dwmmc_priv *priv = dev_get_priv(dev); 157 struct dwmci_host *host = &priv->host; 158 struct udevice *pwr_dev __maybe_unused; 159 int ret; 160 161 #if CONFIG_IS_ENABLED(OF_PLATDATA) 162 struct dtd_rockchip_rk3288_dw_mshc *dtplat = &plat->dtplat; 163 164 host->name = dev->name; 165 host->ioaddr = map_sysmem(dtplat->reg[0], dtplat->reg[1]); 166 host->buswidth = dtplat->bus_width; 167 host->get_mmc_clk = rockchip_dwmmc_get_mmc_clk; 168 host->execute_tuning = rockchip_dwmmc_execute_tuning; 169 host->priv = dev; 170 host->dev_index = 0; 171 priv->fifo_depth = dtplat->fifo_depth; 172 priv->fifo_mode = 0; 173 priv->minmax[0] = 400000; /* 400 kHz */ 174 priv->minmax[1] = dtplat->max_frequency; 175 176 ret = clk_get_by_index_platdata(dev, 0, dtplat->clocks, &priv->clk); 177 if (ret < 0) 178 return ret; 179 #else 180 ret = clk_get_by_index(dev, 0, &priv->clk); 181 if (ret < 0) 182 return ret; 183 184 ret = clk_get_by_name(dev, "ciu-sample", &priv->sample_clk); 185 if (ret < 0) 186 debug("MMC: sample clock not found, not support hs200!\n"); 187 host->execute_tuning = rockchip_dwmmc_execute_tuning; 188 #endif 189 host->fifoth_val = MSIZE(DWMCI_MSIZE) | 190 RX_WMARK(priv->fifo_depth / 2 - 1) | 191 TX_WMARK(priv->fifo_depth / 2); 192 193 host->fifo_mode = priv->fifo_mode; 194 195 #ifdef CONFIG_ROCKCHIP_RK3128 196 host->stride_pio = true; 197 #else 198 host->stride_pio = false; 199 #endif 200 201 #ifdef CONFIG_PWRSEQ 202 /* Enable power if needed */ 203 ret = uclass_get_device_by_phandle(UCLASS_PWRSEQ, dev, "mmc-pwrseq", 204 &pwr_dev); 205 if (!ret) { 206 ret = pwrseq_set_power(pwr_dev, true); 207 if (ret) 208 return ret; 209 } 210 #endif 211 dwmci_setup_cfg(&plat->cfg, host, priv->minmax[1], priv->minmax[0]); 212 if (dev_read_bool(dev, "mmc-hs200-1_8v")) 213 plat->cfg.host_caps |= MMC_MODE_HS200; 214 plat->mmc.default_phase = 215 dev_read_u32_default(dev, "default-sample-phase", 0); 216 plat->mmc.init_retry = 0; 217 host->mmc = &plat->mmc; 218 host->mmc->priv = &priv->host; 219 host->mmc->dev = dev; 220 upriv->mmc = host->mmc; 221 222 return dwmci_probe(dev); 223 } 224 225 static int rockchip_dwmmc_bind(struct udevice *dev) 226 { 227 struct rockchip_mmc_plat *plat = dev_get_platdata(dev); 228 229 return dwmci_bind(dev, &plat->mmc, &plat->cfg); 230 } 231 232 static const struct udevice_id rockchip_dwmmc_ids[] = { 233 { .compatible = "rockchip,rk3288-dw-mshc" }, 234 { .compatible = "rockchip,rk2928-dw-mshc" }, 235 { } 236 }; 237 238 U_BOOT_DRIVER(rockchip_dwmmc_drv) = { 239 .name = "rockchip_rk3288_dw_mshc", 240 .id = UCLASS_MMC, 241 .of_match = rockchip_dwmmc_ids, 242 .ofdata_to_platdata = rockchip_dwmmc_ofdata_to_platdata, 243 .ops = &dm_dwmci_ops, 244 .bind = rockchip_dwmmc_bind, 245 .probe = rockchip_dwmmc_probe, 246 .priv_auto_alloc_size = sizeof(struct rockchip_dwmmc_priv), 247 .platdata_auto_alloc_size = sizeof(struct rockchip_mmc_plat), 248 }; 249 250 #ifdef CONFIG_PWRSEQ 251 static int rockchip_dwmmc_pwrseq_set_power(struct udevice *dev, bool enable) 252 { 253 struct gpio_desc reset; 254 int ret; 255 256 ret = gpio_request_by_name(dev, "reset-gpios", 0, &reset, GPIOD_IS_OUT); 257 if (ret) 258 return ret; 259 dm_gpio_set_value(&reset, 1); 260 udelay(1); 261 dm_gpio_set_value(&reset, 0); 262 udelay(200); 263 264 return 0; 265 } 266 267 static const struct pwrseq_ops rockchip_dwmmc_pwrseq_ops = { 268 .set_power = rockchip_dwmmc_pwrseq_set_power, 269 }; 270 271 static const struct udevice_id rockchip_dwmmc_pwrseq_ids[] = { 272 { .compatible = "mmc-pwrseq-emmc" }, 273 { } 274 }; 275 276 U_BOOT_DRIVER(rockchip_dwmmc_pwrseq_drv) = { 277 .name = "mmc_pwrseq_emmc", 278 .id = UCLASS_PWRSEQ, 279 .of_match = rockchip_dwmmc_pwrseq_ids, 280 .ops = &rockchip_dwmmc_pwrseq_ops, 281 }; 282 #endif 283