1 /* 2 * Copyright (c) 2013 Google, Inc 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <clk.h> 9 #include <dm.h> 10 #include <dt-structs.h> 11 #include <dwmmc.h> 12 #include <errno.h> 13 #include <mapmem.h> 14 #include <pwrseq.h> 15 #include <syscon.h> 16 #include <asm/gpio.h> 17 #include <asm/arch/clock.h> 18 #include <asm/arch/periph.h> 19 #include <linux/err.h> 20 21 DECLARE_GLOBAL_DATA_PTR; 22 23 struct rockchip_mmc_plat { 24 #if CONFIG_IS_ENABLED(OF_PLATDATA) 25 struct dtd_rockchip_rk3288_dw_mshc dtplat; 26 #endif 27 struct mmc_config cfg; 28 struct mmc mmc; 29 }; 30 31 struct rockchip_dwmmc_priv { 32 struct clk clk; 33 struct clk sample_clk; 34 struct dwmci_host host; 35 int fifo_depth; 36 bool fifo_mode; 37 u32 minmax[2]; 38 }; 39 40 #ifdef CONFIG_USING_KERNEL_DTB 41 int board_mmc_dm_reinit(struct udevice *dev) 42 { 43 struct rockchip_dwmmc_priv *priv = dev_get_priv(dev); 44 45 if (!priv) 46 return 0; 47 48 if (!memcmp(dev->name, "dwmmc", strlen("dwmmc"))) 49 return clk_get_by_index(dev, 0, &priv->clk); 50 else 51 return 0; 52 } 53 #endif 54 55 #ifdef CONFIG_SPL_BUILD 56 __weak void mmc_gpio_init_direct(void) {} 57 #endif 58 59 static uint rockchip_dwmmc_get_mmc_clk(struct dwmci_host *host, uint freq) 60 { 61 struct udevice *dev = host->priv; 62 struct rockchip_dwmmc_priv *priv = dev_get_priv(dev); 63 int ret; 64 65 /* 66 * If DDR52 8bit mode(only emmc work in 8bit mode), 67 * divider must be set 1 68 */ 69 if (mmc_card_ddr52(host->mmc) && host->mmc->bus_width == 8) 70 freq *= 2; 71 72 ret = clk_set_rate(&priv->clk, freq); 73 if (ret < 0) { 74 debug("%s: err=%d\n", __func__, ret); 75 return 0; 76 } 77 78 return freq; 79 } 80 81 static int rockchip_dwmmc_ofdata_to_platdata(struct udevice *dev) 82 { 83 #if !CONFIG_IS_ENABLED(OF_PLATDATA) 84 struct rockchip_dwmmc_priv *priv = dev_get_priv(dev); 85 struct dwmci_host *host = &priv->host; 86 87 host->name = dev->name; 88 host->ioaddr = dev_read_addr_ptr(dev); 89 host->buswidth = dev_read_u32_default(dev, "bus-width", 4); 90 host->get_mmc_clk = rockchip_dwmmc_get_mmc_clk; 91 host->priv = dev; 92 93 /* use non-removeable as sdcard and emmc as judgement */ 94 if (dev_read_bool(dev, "non-removable")) 95 host->dev_index = 0; 96 else 97 host->dev_index = 1; 98 99 priv->fifo_depth = dev_read_u32_default(dev, "fifo-depth", 0); 100 101 if (priv->fifo_depth < 0) 102 return -EINVAL; 103 priv->fifo_mode = dev_read_bool(dev, "fifo-mode"); 104 105 /* 106 * 'clock-freq-min-max' is deprecated 107 * (see https://github.com/torvalds/linux/commit/b023030f10573de738bbe8df63d43acab64c9f7b) 108 */ 109 if (dev_read_u32_array(dev, "clock-freq-min-max", priv->minmax, 2)) { 110 int val = dev_read_u32_default(dev, "max-frequency", -EINVAL); 111 112 if (val < 0) 113 return val; 114 115 priv->minmax[0] = 400000; /* 400 kHz */ 116 priv->minmax[1] = val; 117 } else { 118 debug("%s: 'clock-freq-min-max' property was deprecated.\n", 119 __func__); 120 } 121 #endif 122 return 0; 123 } 124 125 #ifndef CONFIG_MMC_SIMPLE 126 #define NUM_PHASES 32 127 #define TUNING_ITERATION_TO_PHASE(i, num_phases) (DIV_ROUND_UP((i) * 360, num_phases)) 128 129 static int rockchip_dwmmc_execute_tuning(struct dwmci_host *host, u32 opcode) 130 { 131 struct mmc *mmc = host->mmc; 132 struct udevice *dev = host->priv; 133 struct rockchip_dwmmc_priv *priv = dev_get_priv(dev); 134 int ret = 0; 135 int i, num_phases = NUM_PHASES; 136 bool v, prev_v = 0, first_v; 137 struct range_t { 138 short start; 139 short end; /* inclusive */ 140 }; 141 struct range_t ranges[NUM_PHASES / 2 + 1]; 142 unsigned int range_count = 0; 143 int longest_range_len = -1; 144 int longest_range = -1; 145 int middle_phase, real_middle_phase; 146 ulong ts; 147 148 if (IS_ERR(&priv->sample_clk)) 149 return -EIO; 150 ts = get_timer(0); 151 152 /* Try each phase and extract good ranges */ 153 for (i = 0; i < num_phases; ) { 154 /* Cannot guarantee any phases larger than 270 would work well */ 155 if (TUNING_ITERATION_TO_PHASE(i, num_phases) > 270) 156 break; 157 clk_set_phase(&priv->sample_clk, TUNING_ITERATION_TO_PHASE(i, num_phases)); 158 159 v = !mmc_send_tuning(mmc, opcode); 160 debug("3 Tuning phase is %d v = %x\n", TUNING_ITERATION_TO_PHASE(i, num_phases), v); 161 if (i == 0) 162 first_v = v; 163 164 if ((!prev_v) && v) { 165 range_count++; 166 ranges[range_count - 1].start = i; 167 } 168 169 if (v) 170 ranges[range_count - 1].end = i; 171 i++; 172 prev_v = v; 173 } 174 175 if (range_count == 0) { 176 dev_warn(host->dev, "All phases bad!"); 177 return -EIO; 178 } 179 180 /* wrap around case, merge the end points */ 181 if ((range_count > 1) && first_v && v) { 182 ranges[0].start = ranges[range_count - 1].start; 183 range_count--; 184 } 185 186 /* Find the longest range */ 187 for (i = 0; i < range_count; i++) { 188 int len = (ranges[i].end - ranges[i].start + 1); 189 190 if (len < 0) 191 len += num_phases; 192 193 if (longest_range_len < len) { 194 longest_range_len = len; 195 longest_range = i; 196 } 197 198 debug("Good phase range %d-%d (%d len)\n", 199 TUNING_ITERATION_TO_PHASE(ranges[i].start, num_phases), 200 TUNING_ITERATION_TO_PHASE(ranges[i].end, num_phases), 201 len); 202 } 203 204 printf("Best phase range %d-%d (%d len)\n", 205 TUNING_ITERATION_TO_PHASE(ranges[longest_range].start, num_phases), 206 TUNING_ITERATION_TO_PHASE(ranges[longest_range].end, num_phases), 207 longest_range_len); 208 209 middle_phase = ranges[longest_range].start + longest_range_len / 2; 210 middle_phase %= num_phases; 211 real_middle_phase = TUNING_ITERATION_TO_PHASE(middle_phase, num_phases); 212 213 /* 214 * Since we cut out 270 ~ 360, the original algorithm 215 * still rolling ranges before and after 270 together 216 * in some corner cases, we should adjust it to avoid 217 * using any middle phase located between 270 and 360. 218 * By calculatiion, it happends due to the bad phases 219 * lay between 90 ~ 180. So others are all fine to chose. 220 * Pick 270 is a better choice in those cases. In case of 221 * bad phases exceed 180, the middle phase of rollback 222 * would be bigger than 315, so we chose 360. 223 */ 224 if (real_middle_phase > 270) { 225 if (real_middle_phase < 315) 226 real_middle_phase = 270; 227 else 228 real_middle_phase = 0; 229 } 230 231 printf("Successfully tuned phase to %d, used %ldms\n", real_middle_phase, get_timer(0) - ts); 232 233 clk_set_phase(&priv->sample_clk, real_middle_phase); 234 235 return ret; 236 } 237 #else 238 static int rockchip_dwmmc_execute_tuning(struct dwmci_host *host, u32 opcode) { return 0; } 239 #endif 240 241 static int rockchip_dwmmc_probe(struct udevice *dev) 242 { 243 struct rockchip_mmc_plat *plat = dev_get_platdata(dev); 244 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); 245 struct rockchip_dwmmc_priv *priv = dev_get_priv(dev); 246 struct dwmci_host *host = &priv->host; 247 struct udevice *pwr_dev __maybe_unused; 248 int ret; 249 250 #ifdef CONFIG_SPL_BUILD 251 mmc_gpio_init_direct(); 252 #endif 253 #if CONFIG_IS_ENABLED(OF_PLATDATA) 254 struct dtd_rockchip_rk3288_dw_mshc *dtplat = &plat->dtplat; 255 256 host->name = dev->name; 257 host->ioaddr = map_sysmem(dtplat->reg[0], dtplat->reg[1]); 258 host->buswidth = dtplat->bus_width; 259 host->get_mmc_clk = rockchip_dwmmc_get_mmc_clk; 260 host->execute_tuning = rockchip_dwmmc_execute_tuning; 261 host->priv = dev; 262 host->dev_index = 0; 263 priv->fifo_depth = dtplat->fifo_depth; 264 priv->fifo_mode = 0; 265 priv->minmax[0] = 400000; /* 400 kHz */ 266 priv->minmax[1] = dtplat->max_frequency; 267 268 ret = clk_get_by_index_platdata(dev, 0, dtplat->clocks, &priv->clk); 269 if (ret < 0) 270 return ret; 271 #else 272 ret = clk_get_by_index(dev, 0, &priv->clk); 273 if (ret < 0) 274 return ret; 275 276 ret = clk_get_by_name(dev, "ciu-sample", &priv->sample_clk); 277 if (ret < 0) 278 debug("MMC: sample clock not found, not support hs200!\n"); 279 host->execute_tuning = rockchip_dwmmc_execute_tuning; 280 #endif 281 host->fifoth_val = MSIZE(DWMCI_MSIZE) | 282 RX_WMARK(priv->fifo_depth / 2 - 1) | 283 TX_WMARK(priv->fifo_depth / 2); 284 285 host->fifo_mode = priv->fifo_mode; 286 287 #ifdef CONFIG_ROCKCHIP_RK3128 288 host->stride_pio = true; 289 #else 290 host->stride_pio = false; 291 #endif 292 293 #ifdef CONFIG_PWRSEQ 294 /* Enable power if needed */ 295 ret = uclass_get_device_by_phandle(UCLASS_PWRSEQ, dev, "mmc-pwrseq", 296 &pwr_dev); 297 if (!ret) { 298 ret = pwrseq_set_power(pwr_dev, true); 299 if (ret) 300 return ret; 301 } 302 #endif 303 dwmci_setup_cfg(&plat->cfg, host, priv->minmax[1], priv->minmax[0]); 304 if (dev_read_bool(dev, "mmc-hs200-1_8v")) 305 plat->cfg.host_caps |= MMC_MODE_HS200; 306 plat->mmc.default_phase = 307 dev_read_u32_default(dev, "default-sample-phase", 0); 308 #ifdef CONFIG_ROCKCHIP_RV1106 309 if (!(ret < 0) && (&priv->sample_clk)) { 310 ret = clk_set_phase(&priv->sample_clk, plat->mmc.default_phase); 311 if (ret < 0) 312 debug("MMC: can not set default phase!\n"); 313 } 314 #endif 315 316 plat->mmc.init_retry = 0; 317 host->mmc = &plat->mmc; 318 host->mmc->priv = &priv->host; 319 host->mmc->dev = dev; 320 upriv->mmc = host->mmc; 321 322 return dwmci_probe(dev); 323 } 324 325 static int rockchip_dwmmc_bind(struct udevice *dev) 326 { 327 struct rockchip_mmc_plat *plat = dev_get_platdata(dev); 328 329 return dwmci_bind(dev, &plat->mmc, &plat->cfg); 330 } 331 332 static const struct udevice_id rockchip_dwmmc_ids[] = { 333 { .compatible = "rockchip,rk3288-dw-mshc" }, 334 { .compatible = "rockchip,rk2928-dw-mshc" }, 335 { } 336 }; 337 338 U_BOOT_DRIVER(rockchip_dwmmc_drv) = { 339 .name = "rockchip_rk3288_dw_mshc", 340 .id = UCLASS_MMC, 341 .of_match = rockchip_dwmmc_ids, 342 .ofdata_to_platdata = rockchip_dwmmc_ofdata_to_platdata, 343 .ops = &dm_dwmci_ops, 344 .bind = rockchip_dwmmc_bind, 345 .probe = rockchip_dwmmc_probe, 346 .priv_auto_alloc_size = sizeof(struct rockchip_dwmmc_priv), 347 .platdata_auto_alloc_size = sizeof(struct rockchip_mmc_plat), 348 }; 349 350 #ifdef CONFIG_PWRSEQ 351 static int rockchip_dwmmc_pwrseq_set_power(struct udevice *dev, bool enable) 352 { 353 struct gpio_desc reset; 354 int ret; 355 356 ret = gpio_request_by_name(dev, "reset-gpios", 0, &reset, GPIOD_IS_OUT); 357 if (ret) 358 return ret; 359 dm_gpio_set_value(&reset, 1); 360 udelay(1); 361 dm_gpio_set_value(&reset, 0); 362 udelay(200); 363 364 return 0; 365 } 366 367 static const struct pwrseq_ops rockchip_dwmmc_pwrseq_ops = { 368 .set_power = rockchip_dwmmc_pwrseq_set_power, 369 }; 370 371 static const struct udevice_id rockchip_dwmmc_pwrseq_ids[] = { 372 { .compatible = "mmc-pwrseq-emmc" }, 373 { } 374 }; 375 376 U_BOOT_DRIVER(rockchip_dwmmc_pwrseq_drv) = { 377 .name = "mmc_pwrseq_emmc", 378 .id = UCLASS_PWRSEQ, 379 .of_match = rockchip_dwmmc_pwrseq_ids, 380 .ops = &rockchip_dwmmc_pwrseq_ops, 381 }; 382 #endif 383