1 /* 2 * (C) Copyright 2008 3 * Texas Instruments, <www.ti.com> 4 * Sukumar Ghorai <s-ghorai@ti.com> 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation's version 2 of 12 * the License. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22 * MA 02111-1307 USA 23 */ 24 25 #include <config.h> 26 #include <common.h> 27 #include <mmc.h> 28 #include <part.h> 29 #include <i2c.h> 30 #include <twl4030.h> 31 #include <twl6030.h> 32 #include <twl6035.h> 33 #include <asm/io.h> 34 #include <asm/arch/mmc_host_def.h> 35 #include <asm/arch/sys_proto.h> 36 37 /* common definitions for all OMAPs */ 38 #define SYSCTL_SRC (1 << 25) 39 #define SYSCTL_SRD (1 << 26) 40 41 struct omap_hsmmc_data { 42 struct hsmmc *base_addr; 43 }; 44 45 /* If we fail after 1 second wait, something is really bad */ 46 #define MAX_RETRY_MS 1000 47 48 static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size); 49 static int mmc_write_data(struct hsmmc *mmc_base, const char *buf, 50 unsigned int siz); 51 static struct mmc hsmmc_dev[3]; 52 static struct omap_hsmmc_data hsmmc_dev_data[3]; 53 54 #if defined(CONFIG_OMAP44XX) && defined(CONFIG_TWL6030_POWER) 55 static void omap4_vmmc_pbias_config(struct mmc *mmc) 56 { 57 u32 value = 0; 58 struct omap_sys_ctrl_regs *const ctrl = 59 (struct omap_sys_ctrl_regs *) SYSCTRL_GENERAL_CORE_BASE; 60 61 62 value = readl(&ctrl->control_pbiaslite); 63 value &= ~(MMC1_PBIASLITE_PWRDNZ | MMC1_PWRDNZ); 64 writel(value, &ctrl->control_pbiaslite); 65 /* set VMMC to 3V */ 66 twl6030_power_mmc_init(); 67 value = readl(&ctrl->control_pbiaslite); 68 value |= MMC1_PBIASLITE_VMODE | MMC1_PBIASLITE_PWRDNZ | MMC1_PWRDNZ; 69 writel(value, &ctrl->control_pbiaslite); 70 } 71 #endif 72 73 #if defined(CONFIG_OMAP54XX) && defined(CONFIG_TWL6035_POWER) 74 static void omap5_pbias_config(struct mmc *mmc) 75 { 76 u32 value = 0; 77 struct omap_sys_ctrl_regs *const ctrl = 78 (struct omap_sys_ctrl_regs *) SYSCTRL_GENERAL_CORE_BASE; 79 80 value = readl(&ctrl->control_pbias); 81 value &= ~(SDCARD_PWRDNZ | SDCARD_BIAS_PWRDNZ); 82 value |= SDCARD_BIAS_HIZ_MODE; 83 writel(value, &ctrl->control_pbias); 84 85 twl6035_mmc1_poweron_ldo(); 86 87 value = readl(&ctrl->control_pbias); 88 value &= ~SDCARD_BIAS_HIZ_MODE; 89 value |= SDCARD_PBIASLITE_VMODE | SDCARD_PWRDNZ | SDCARD_BIAS_PWRDNZ; 90 writel(value, &ctrl->control_pbias); 91 92 value = readl(&ctrl->control_pbias); 93 if (value & (1 << 23)) { 94 value &= ~(SDCARD_PWRDNZ | SDCARD_BIAS_PWRDNZ); 95 value |= SDCARD_BIAS_HIZ_MODE; 96 writel(value, &ctrl->control_pbias); 97 } 98 } 99 #endif 100 101 unsigned char mmc_board_init(struct mmc *mmc) 102 { 103 #if defined(CONFIG_OMAP34XX) 104 t2_t *t2_base = (t2_t *)T2_BASE; 105 struct prcm *prcm_base = (struct prcm *)PRCM_BASE; 106 u32 pbias_lite; 107 108 pbias_lite = readl(&t2_base->pbias_lite); 109 pbias_lite &= ~(PBIASLITEPWRDNZ1 | PBIASLITEPWRDNZ0); 110 writel(pbias_lite, &t2_base->pbias_lite); 111 #endif 112 #if defined(CONFIG_TWL4030_POWER) 113 twl4030_power_mmc_init(); 114 mdelay(100); /* ramp-up delay from Linux code */ 115 #endif 116 #if defined(CONFIG_OMAP34XX) 117 writel(pbias_lite | PBIASLITEPWRDNZ1 | 118 PBIASSPEEDCTRL0 | PBIASLITEPWRDNZ0, 119 &t2_base->pbias_lite); 120 121 writel(readl(&t2_base->devconf0) | MMCSDIO1ADPCLKISEL, 122 &t2_base->devconf0); 123 124 writel(readl(&t2_base->devconf1) | MMCSDIO2ADPCLKISEL, 125 &t2_base->devconf1); 126 127 /* Change from default of 52MHz to 26MHz if necessary */ 128 if (!(mmc->host_caps & MMC_MODE_HS_52MHz)) 129 writel(readl(&t2_base->ctl_prog_io1) & ~CTLPROGIO1SPEEDCTRL, 130 &t2_base->ctl_prog_io1); 131 132 writel(readl(&prcm_base->fclken1_core) | 133 EN_MMC1 | EN_MMC2 | EN_MMC3, 134 &prcm_base->fclken1_core); 135 136 writel(readl(&prcm_base->iclken1_core) | 137 EN_MMC1 | EN_MMC2 | EN_MMC3, 138 &prcm_base->iclken1_core); 139 #endif 140 141 #if defined(CONFIG_OMAP44XX) && defined(CONFIG_TWL6030_POWER) 142 /* PBIAS config needed for MMC1 only */ 143 if (mmc->block_dev.dev == 0) 144 omap4_vmmc_pbias_config(mmc); 145 #endif 146 #if defined(CONFIG_OMAP54XX) && defined(CONFIG_TWL6035_POWER) 147 if (mmc->block_dev.dev == 0) 148 omap5_pbias_config(mmc); 149 #endif 150 151 return 0; 152 } 153 154 void mmc_init_stream(struct hsmmc *mmc_base) 155 { 156 ulong start; 157 158 writel(readl(&mmc_base->con) | INIT_INITSTREAM, &mmc_base->con); 159 160 writel(MMC_CMD0, &mmc_base->cmd); 161 start = get_timer(0); 162 while (!(readl(&mmc_base->stat) & CC_MASK)) { 163 if (get_timer(0) - start > MAX_RETRY_MS) { 164 printf("%s: timedout waiting for cc!\n", __func__); 165 return; 166 } 167 } 168 writel(CC_MASK, &mmc_base->stat) 169 ; 170 writel(MMC_CMD0, &mmc_base->cmd) 171 ; 172 start = get_timer(0); 173 while (!(readl(&mmc_base->stat) & CC_MASK)) { 174 if (get_timer(0) - start > MAX_RETRY_MS) { 175 printf("%s: timedout waiting for cc2!\n", __func__); 176 return; 177 } 178 } 179 writel(readl(&mmc_base->con) & ~INIT_INITSTREAM, &mmc_base->con); 180 } 181 182 183 static int mmc_init_setup(struct mmc *mmc) 184 { 185 struct hsmmc *mmc_base; 186 unsigned int reg_val; 187 unsigned int dsor; 188 ulong start; 189 190 mmc_base = ((struct omap_hsmmc_data *)mmc->priv)->base_addr; 191 mmc_board_init(mmc); 192 193 writel(readl(&mmc_base->sysconfig) | MMC_SOFTRESET, 194 &mmc_base->sysconfig); 195 start = get_timer(0); 196 while ((readl(&mmc_base->sysstatus) & RESETDONE) == 0) { 197 if (get_timer(0) - start > MAX_RETRY_MS) { 198 printf("%s: timedout waiting for cc2!\n", __func__); 199 return TIMEOUT; 200 } 201 } 202 writel(readl(&mmc_base->sysctl) | SOFTRESETALL, &mmc_base->sysctl); 203 start = get_timer(0); 204 while ((readl(&mmc_base->sysctl) & SOFTRESETALL) != 0x0) { 205 if (get_timer(0) - start > MAX_RETRY_MS) { 206 printf("%s: timedout waiting for softresetall!\n", 207 __func__); 208 return TIMEOUT; 209 } 210 } 211 writel(DTW_1_BITMODE | SDBP_PWROFF | SDVS_3V0, &mmc_base->hctl); 212 writel(readl(&mmc_base->capa) | VS30_3V0SUP | VS18_1V8SUP, 213 &mmc_base->capa); 214 215 reg_val = readl(&mmc_base->con) & RESERVED_MASK; 216 217 writel(CTPL_MMC_SD | reg_val | WPP_ACTIVEHIGH | CDP_ACTIVEHIGH | 218 MIT_CTO | DW8_1_4BITMODE | MODE_FUNC | STR_BLOCK | 219 HR_NOHOSTRESP | INIT_NOINIT | NOOPENDRAIN, &mmc_base->con); 220 221 dsor = 240; 222 mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK), 223 (ICE_STOP | DTO_15THDTO | CEN_DISABLE)); 224 mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK, 225 (dsor << CLKD_OFFSET) | ICE_OSCILLATE); 226 start = get_timer(0); 227 while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) { 228 if (get_timer(0) - start > MAX_RETRY_MS) { 229 printf("%s: timedout waiting for ics!\n", __func__); 230 return TIMEOUT; 231 } 232 } 233 writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl); 234 235 writel(readl(&mmc_base->hctl) | SDBP_PWRON, &mmc_base->hctl); 236 237 writel(IE_BADA | IE_CERR | IE_DEB | IE_DCRC | IE_DTO | IE_CIE | 238 IE_CEB | IE_CCRC | IE_CTO | IE_BRR | IE_BWR | IE_TC | IE_CC, 239 &mmc_base->ie); 240 241 mmc_init_stream(mmc_base); 242 243 return 0; 244 } 245 246 /* 247 * MMC controller internal finite state machine reset 248 * 249 * Used to reset command or data internal state machines, using respectively 250 * SRC or SRD bit of SYSCTL register 251 */ 252 static void mmc_reset_controller_fsm(struct hsmmc *mmc_base, u32 bit) 253 { 254 ulong start; 255 256 mmc_reg_out(&mmc_base->sysctl, bit, bit); 257 258 start = get_timer(0); 259 while ((readl(&mmc_base->sysctl) & bit) != 0) { 260 if (get_timer(0) - start > MAX_RETRY_MS) { 261 printf("%s: timedout waiting for sysctl %x to clear\n", 262 __func__, bit); 263 return; 264 } 265 } 266 } 267 268 static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, 269 struct mmc_data *data) 270 { 271 struct hsmmc *mmc_base; 272 unsigned int flags, mmc_stat; 273 ulong start; 274 275 mmc_base = ((struct omap_hsmmc_data *)mmc->priv)->base_addr; 276 start = get_timer(0); 277 while ((readl(&mmc_base->pstate) & (DATI_MASK | CMDI_MASK)) != 0) { 278 if (get_timer(0) - start > MAX_RETRY_MS) { 279 printf("%s: timedout waiting on cmd inhibit to clear\n", 280 __func__); 281 return TIMEOUT; 282 } 283 } 284 writel(0xFFFFFFFF, &mmc_base->stat); 285 start = get_timer(0); 286 while (readl(&mmc_base->stat)) { 287 if (get_timer(0) - start > MAX_RETRY_MS) { 288 printf("%s: timedout waiting for STAT (%x) to clear\n", 289 __func__, readl(&mmc_base->stat)); 290 return TIMEOUT; 291 } 292 } 293 /* 294 * CMDREG 295 * CMDIDX[13:8] : Command index 296 * DATAPRNT[5] : Data Present Select 297 * ENCMDIDX[4] : Command Index Check Enable 298 * ENCMDCRC[3] : Command CRC Check Enable 299 * RSPTYP[1:0] 300 * 00 = No Response 301 * 01 = Length 136 302 * 10 = Length 48 303 * 11 = Length 48 Check busy after response 304 */ 305 /* Delay added before checking the status of frq change 306 * retry not supported by mmc.c(core file) 307 */ 308 if (cmd->cmdidx == SD_CMD_APP_SEND_SCR) 309 udelay(50000); /* wait 50 ms */ 310 311 if (!(cmd->resp_type & MMC_RSP_PRESENT)) 312 flags = 0; 313 else if (cmd->resp_type & MMC_RSP_136) 314 flags = RSP_TYPE_LGHT136 | CICE_NOCHECK; 315 else if (cmd->resp_type & MMC_RSP_BUSY) 316 flags = RSP_TYPE_LGHT48B; 317 else 318 flags = RSP_TYPE_LGHT48; 319 320 /* enable default flags */ 321 flags = flags | (CMD_TYPE_NORMAL | CICE_NOCHECK | CCCE_NOCHECK | 322 MSBS_SGLEBLK | ACEN_DISABLE | BCE_DISABLE | DE_DISABLE); 323 324 if (cmd->resp_type & MMC_RSP_CRC) 325 flags |= CCCE_CHECK; 326 if (cmd->resp_type & MMC_RSP_OPCODE) 327 flags |= CICE_CHECK; 328 329 if (data) { 330 if ((cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK) || 331 (cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK)) { 332 flags |= (MSBS_MULTIBLK | BCE_ENABLE); 333 data->blocksize = 512; 334 writel(data->blocksize | (data->blocks << 16), 335 &mmc_base->blk); 336 } else 337 writel(data->blocksize | NBLK_STPCNT, &mmc_base->blk); 338 339 if (data->flags & MMC_DATA_READ) 340 flags |= (DP_DATA | DDIR_READ); 341 else 342 flags |= (DP_DATA | DDIR_WRITE); 343 } 344 345 writel(cmd->cmdarg, &mmc_base->arg); 346 writel((cmd->cmdidx << 24) | flags, &mmc_base->cmd); 347 348 start = get_timer(0); 349 do { 350 mmc_stat = readl(&mmc_base->stat); 351 if (get_timer(0) - start > MAX_RETRY_MS) { 352 printf("%s : timeout: No status update\n", __func__); 353 return TIMEOUT; 354 } 355 } while (!mmc_stat); 356 357 if ((mmc_stat & IE_CTO) != 0) { 358 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC); 359 return TIMEOUT; 360 } else if ((mmc_stat & ERRI_MASK) != 0) 361 return -1; 362 363 if (mmc_stat & CC_MASK) { 364 writel(CC_MASK, &mmc_base->stat); 365 if (cmd->resp_type & MMC_RSP_PRESENT) { 366 if (cmd->resp_type & MMC_RSP_136) { 367 /* response type 2 */ 368 cmd->response[3] = readl(&mmc_base->rsp10); 369 cmd->response[2] = readl(&mmc_base->rsp32); 370 cmd->response[1] = readl(&mmc_base->rsp54); 371 cmd->response[0] = readl(&mmc_base->rsp76); 372 } else 373 /* response types 1, 1b, 3, 4, 5, 6 */ 374 cmd->response[0] = readl(&mmc_base->rsp10); 375 } 376 } 377 378 if (data && (data->flags & MMC_DATA_READ)) { 379 mmc_read_data(mmc_base, data->dest, 380 data->blocksize * data->blocks); 381 } else if (data && (data->flags & MMC_DATA_WRITE)) { 382 mmc_write_data(mmc_base, data->src, 383 data->blocksize * data->blocks); 384 } 385 return 0; 386 } 387 388 static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size) 389 { 390 unsigned int *output_buf = (unsigned int *)buf; 391 unsigned int mmc_stat; 392 unsigned int count; 393 394 /* 395 * Start Polled Read 396 */ 397 count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size; 398 count /= 4; 399 400 while (size) { 401 ulong start = get_timer(0); 402 do { 403 mmc_stat = readl(&mmc_base->stat); 404 if (get_timer(0) - start > MAX_RETRY_MS) { 405 printf("%s: timedout waiting for status!\n", 406 __func__); 407 return TIMEOUT; 408 } 409 } while (mmc_stat == 0); 410 411 if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0) 412 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD); 413 414 if ((mmc_stat & ERRI_MASK) != 0) 415 return 1; 416 417 if (mmc_stat & BRR_MASK) { 418 unsigned int k; 419 420 writel(readl(&mmc_base->stat) | BRR_MASK, 421 &mmc_base->stat); 422 for (k = 0; k < count; k++) { 423 *output_buf = readl(&mmc_base->data); 424 output_buf++; 425 } 426 size -= (count*4); 427 } 428 429 if (mmc_stat & BWR_MASK) 430 writel(readl(&mmc_base->stat) | BWR_MASK, 431 &mmc_base->stat); 432 433 if (mmc_stat & TC_MASK) { 434 writel(readl(&mmc_base->stat) | TC_MASK, 435 &mmc_base->stat); 436 break; 437 } 438 } 439 return 0; 440 } 441 442 static int mmc_write_data(struct hsmmc *mmc_base, const char *buf, 443 unsigned int size) 444 { 445 unsigned int *input_buf = (unsigned int *)buf; 446 unsigned int mmc_stat; 447 unsigned int count; 448 449 /* 450 * Start Polled Read 451 */ 452 count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size; 453 count /= 4; 454 455 while (size) { 456 ulong start = get_timer(0); 457 do { 458 mmc_stat = readl(&mmc_base->stat); 459 if (get_timer(0) - start > MAX_RETRY_MS) { 460 printf("%s: timedout waiting for status!\n", 461 __func__); 462 return TIMEOUT; 463 } 464 } while (mmc_stat == 0); 465 466 if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0) 467 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD); 468 469 if ((mmc_stat & ERRI_MASK) != 0) 470 return 1; 471 472 if (mmc_stat & BWR_MASK) { 473 unsigned int k; 474 475 writel(readl(&mmc_base->stat) | BWR_MASK, 476 &mmc_base->stat); 477 for (k = 0; k < count; k++) { 478 writel(*input_buf, &mmc_base->data); 479 input_buf++; 480 } 481 size -= (count*4); 482 } 483 484 if (mmc_stat & BRR_MASK) 485 writel(readl(&mmc_base->stat) | BRR_MASK, 486 &mmc_base->stat); 487 488 if (mmc_stat & TC_MASK) { 489 writel(readl(&mmc_base->stat) | TC_MASK, 490 &mmc_base->stat); 491 break; 492 } 493 } 494 return 0; 495 } 496 497 static void mmc_set_ios(struct mmc *mmc) 498 { 499 struct hsmmc *mmc_base; 500 unsigned int dsor = 0; 501 ulong start; 502 503 mmc_base = ((struct omap_hsmmc_data *)mmc->priv)->base_addr; 504 /* configue bus width */ 505 switch (mmc->bus_width) { 506 case 8: 507 writel(readl(&mmc_base->con) | DTW_8_BITMODE, 508 &mmc_base->con); 509 break; 510 511 case 4: 512 writel(readl(&mmc_base->con) & ~DTW_8_BITMODE, 513 &mmc_base->con); 514 writel(readl(&mmc_base->hctl) | DTW_4_BITMODE, 515 &mmc_base->hctl); 516 break; 517 518 case 1: 519 default: 520 writel(readl(&mmc_base->con) & ~DTW_8_BITMODE, 521 &mmc_base->con); 522 writel(readl(&mmc_base->hctl) & ~DTW_4_BITMODE, 523 &mmc_base->hctl); 524 break; 525 } 526 527 /* configure clock with 96Mhz system clock. 528 */ 529 if (mmc->clock != 0) { 530 dsor = (MMC_CLOCK_REFERENCE * 1000000 / mmc->clock); 531 if ((MMC_CLOCK_REFERENCE * 1000000) / dsor > mmc->clock) 532 dsor++; 533 } 534 535 mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK), 536 (ICE_STOP | DTO_15THDTO | CEN_DISABLE)); 537 538 mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK, 539 (dsor << CLKD_OFFSET) | ICE_OSCILLATE); 540 541 start = get_timer(0); 542 while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) { 543 if (get_timer(0) - start > MAX_RETRY_MS) { 544 printf("%s: timedout waiting for ics!\n", __func__); 545 return; 546 } 547 } 548 writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl); 549 } 550 551 int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max) 552 { 553 struct mmc *mmc = &hsmmc_dev[dev_index]; 554 struct omap_hsmmc_data *priv_data = &hsmmc_dev_data[dev_index]; 555 556 sprintf(mmc->name, "OMAP SD/MMC"); 557 mmc->send_cmd = mmc_send_cmd; 558 mmc->set_ios = mmc_set_ios; 559 mmc->init = mmc_init_setup; 560 mmc->getcd = NULL; 561 mmc->priv = priv_data; 562 563 switch (dev_index) { 564 case 0: 565 priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE; 566 break; 567 #ifdef OMAP_HSMMC2_BASE 568 case 1: 569 priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC2_BASE; 570 break; 571 #endif 572 #ifdef OMAP_HSMMC3_BASE 573 case 2: 574 priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC3_BASE; 575 break; 576 #endif 577 default: 578 priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE; 579 return 1; 580 } 581 mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; 582 mmc->host_caps = (MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS | 583 MMC_MODE_HC) & ~host_caps_mask; 584 585 mmc->f_min = 400000; 586 587 if (f_max != 0) 588 mmc->f_max = f_max; 589 else { 590 if (mmc->host_caps & MMC_MODE_HS) { 591 if (mmc->host_caps & MMC_MODE_HS_52MHz) 592 mmc->f_max = 52000000; 593 else 594 mmc->f_max = 26000000; 595 } else 596 mmc->f_max = 20000000; 597 } 598 599 mmc->b_max = 0; 600 601 #if defined(CONFIG_OMAP34XX) 602 /* 603 * Silicon revs 2.1 and older do not support multiblock transfers. 604 */ 605 if ((get_cpu_family() == CPU_OMAP34XX) && (get_cpu_rev() <= CPU_3XX_ES21)) 606 mmc->b_max = 1; 607 #endif 608 609 mmc_register(mmc); 610 611 return 0; 612 } 613