1 /* 2 * (C) Copyright 2008 3 * Texas Instruments, <www.ti.com> 4 * Sukumar Ghorai <s-ghorai@ti.com> 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation's version 2 of 12 * the License. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22 * MA 02111-1307 USA 23 */ 24 25 #include <config.h> 26 #include <common.h> 27 #include <mmc.h> 28 #include <part.h> 29 #include <i2c.h> 30 #include <twl4030.h> 31 #include <twl6030.h> 32 #include <asm/io.h> 33 #include <asm/arch/mmc_host_def.h> 34 #include <asm/arch/sys_proto.h> 35 36 /* If we fail after 1 second wait, something is really bad */ 37 #define MAX_RETRY_MS 1000 38 39 static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size); 40 static int mmc_write_data(struct hsmmc *mmc_base, const char *buf, 41 unsigned int siz); 42 static struct mmc hsmmc_dev[2]; 43 44 #if defined(CONFIG_OMAP44XX) && defined(CONFIG_TWL6030_POWER) 45 static void omap4_vmmc_pbias_config(struct mmc *mmc) 46 { 47 u32 value = 0; 48 struct omap4_sys_ctrl_regs *const ctrl = 49 (struct omap4_sys_ctrl_regs *)SYSCTRL_GENERAL_CORE_BASE; 50 51 52 value = readl(&ctrl->control_pbiaslite); 53 value &= ~(MMC1_PBIASLITE_PWRDNZ | MMC1_PWRDNZ); 54 writel(value, &ctrl->control_pbiaslite); 55 /* set VMMC to 3V */ 56 twl6030_power_mmc_init(); 57 value = readl(&ctrl->control_pbiaslite); 58 value |= MMC1_PBIASLITE_VMODE | MMC1_PBIASLITE_PWRDNZ | MMC1_PWRDNZ; 59 writel(value, &ctrl->control_pbiaslite); 60 } 61 #endif 62 63 unsigned char mmc_board_init(struct mmc *mmc) 64 { 65 #if defined(CONFIG_OMAP34XX) 66 t2_t *t2_base = (t2_t *)T2_BASE; 67 struct prcm *prcm_base = (struct prcm *)PRCM_BASE; 68 u32 pbias_lite; 69 70 pbias_lite = readl(&t2_base->pbias_lite); 71 pbias_lite &= ~(PBIASLITEPWRDNZ1 | PBIASLITEPWRDNZ0); 72 writel(pbias_lite, &t2_base->pbias_lite); 73 #endif 74 #if defined(CONFIG_TWL4030_POWER) 75 twl4030_power_mmc_init(); 76 mdelay(100); /* ramp-up delay from Linux code */ 77 #endif 78 #if defined(CONFIG_OMAP34XX) 79 writel(pbias_lite | PBIASLITEPWRDNZ1 | 80 PBIASSPEEDCTRL0 | PBIASLITEPWRDNZ0, 81 &t2_base->pbias_lite); 82 83 writel(readl(&t2_base->devconf0) | MMCSDIO1ADPCLKISEL, 84 &t2_base->devconf0); 85 86 writel(readl(&t2_base->devconf1) | MMCSDIO2ADPCLKISEL, 87 &t2_base->devconf1); 88 89 writel(readl(&prcm_base->fclken1_core) | 90 EN_MMC1 | EN_MMC2 | EN_MMC3, 91 &prcm_base->fclken1_core); 92 93 writel(readl(&prcm_base->iclken1_core) | 94 EN_MMC1 | EN_MMC2 | EN_MMC3, 95 &prcm_base->iclken1_core); 96 #endif 97 98 #if defined(CONFIG_OMAP44XX) && defined(CONFIG_TWL6030_POWER) 99 /* PBIAS config needed for MMC1 only */ 100 if (mmc->block_dev.dev == 0) 101 omap4_vmmc_pbias_config(mmc); 102 #endif 103 104 return 0; 105 } 106 107 void mmc_init_stream(struct hsmmc *mmc_base) 108 { 109 ulong start; 110 111 writel(readl(&mmc_base->con) | INIT_INITSTREAM, &mmc_base->con); 112 113 writel(MMC_CMD0, &mmc_base->cmd); 114 start = get_timer(0); 115 while (!(readl(&mmc_base->stat) & CC_MASK)) { 116 if (get_timer(0) - start > MAX_RETRY_MS) { 117 printf("%s: timedout waiting for cc!\n", __func__); 118 return; 119 } 120 } 121 writel(CC_MASK, &mmc_base->stat) 122 ; 123 writel(MMC_CMD0, &mmc_base->cmd) 124 ; 125 start = get_timer(0); 126 while (!(readl(&mmc_base->stat) & CC_MASK)) { 127 if (get_timer(0) - start > MAX_RETRY_MS) { 128 printf("%s: timedout waiting for cc2!\n", __func__); 129 return; 130 } 131 } 132 writel(readl(&mmc_base->con) & ~INIT_INITSTREAM, &mmc_base->con); 133 } 134 135 136 static int mmc_init_setup(struct mmc *mmc) 137 { 138 struct hsmmc *mmc_base = (struct hsmmc *)mmc->priv; 139 unsigned int reg_val; 140 unsigned int dsor; 141 ulong start; 142 143 mmc_board_init(mmc); 144 145 writel(readl(&mmc_base->sysconfig) | MMC_SOFTRESET, 146 &mmc_base->sysconfig); 147 start = get_timer(0); 148 while ((readl(&mmc_base->sysstatus) & RESETDONE) == 0) { 149 if (get_timer(0) - start > MAX_RETRY_MS) { 150 printf("%s: timedout waiting for cc2!\n", __func__); 151 return TIMEOUT; 152 } 153 } 154 writel(readl(&mmc_base->sysctl) | SOFTRESETALL, &mmc_base->sysctl); 155 start = get_timer(0); 156 while ((readl(&mmc_base->sysctl) & SOFTRESETALL) != 0x0) { 157 if (get_timer(0) - start > MAX_RETRY_MS) { 158 printf("%s: timedout waiting for softresetall!\n", 159 __func__); 160 return TIMEOUT; 161 } 162 } 163 writel(DTW_1_BITMODE | SDBP_PWROFF | SDVS_3V0, &mmc_base->hctl); 164 writel(readl(&mmc_base->capa) | VS30_3V0SUP | VS18_1V8SUP, 165 &mmc_base->capa); 166 167 reg_val = readl(&mmc_base->con) & RESERVED_MASK; 168 169 writel(CTPL_MMC_SD | reg_val | WPP_ACTIVEHIGH | CDP_ACTIVEHIGH | 170 MIT_CTO | DW8_1_4BITMODE | MODE_FUNC | STR_BLOCK | 171 HR_NOHOSTRESP | INIT_NOINIT | NOOPENDRAIN, &mmc_base->con); 172 173 dsor = 240; 174 mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK), 175 (ICE_STOP | DTO_15THDTO | CEN_DISABLE)); 176 mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK, 177 (dsor << CLKD_OFFSET) | ICE_OSCILLATE); 178 start = get_timer(0); 179 while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) { 180 if (get_timer(0) - start > MAX_RETRY_MS) { 181 printf("%s: timedout waiting for ics!\n", __func__); 182 return TIMEOUT; 183 } 184 } 185 writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl); 186 187 writel(readl(&mmc_base->hctl) | SDBP_PWRON, &mmc_base->hctl); 188 189 writel(IE_BADA | IE_CERR | IE_DEB | IE_DCRC | IE_DTO | IE_CIE | 190 IE_CEB | IE_CCRC | IE_CTO | IE_BRR | IE_BWR | IE_TC | IE_CC, 191 &mmc_base->ie); 192 193 mmc_init_stream(mmc_base); 194 195 return 0; 196 } 197 198 199 static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, 200 struct mmc_data *data) 201 { 202 struct hsmmc *mmc_base = (struct hsmmc *)mmc->priv; 203 unsigned int flags, mmc_stat; 204 ulong start; 205 206 start = get_timer(0); 207 while ((readl(&mmc_base->pstate) & (DATI_MASK | CMDI_MASK)) != 0) { 208 if (get_timer(0) - start > MAX_RETRY_MS) { 209 printf("%s: timedout waiting on cmd inhibit to clear\n", 210 __func__); 211 return TIMEOUT; 212 } 213 } 214 writel(0xFFFFFFFF, &mmc_base->stat); 215 start = get_timer(0); 216 while (readl(&mmc_base->stat)) { 217 if (get_timer(0) - start > MAX_RETRY_MS) { 218 printf("%s: timedout waiting for stat!\n", __func__); 219 return TIMEOUT; 220 } 221 } 222 /* 223 * CMDREG 224 * CMDIDX[13:8] : Command index 225 * DATAPRNT[5] : Data Present Select 226 * ENCMDIDX[4] : Command Index Check Enable 227 * ENCMDCRC[3] : Command CRC Check Enable 228 * RSPTYP[1:0] 229 * 00 = No Response 230 * 01 = Length 136 231 * 10 = Length 48 232 * 11 = Length 48 Check busy after response 233 */ 234 /* Delay added before checking the status of frq change 235 * retry not supported by mmc.c(core file) 236 */ 237 if (cmd->cmdidx == SD_CMD_APP_SEND_SCR) 238 udelay(50000); /* wait 50 ms */ 239 240 if (!(cmd->resp_type & MMC_RSP_PRESENT)) 241 flags = 0; 242 else if (cmd->resp_type & MMC_RSP_136) 243 flags = RSP_TYPE_LGHT136 | CICE_NOCHECK; 244 else if (cmd->resp_type & MMC_RSP_BUSY) 245 flags = RSP_TYPE_LGHT48B; 246 else 247 flags = RSP_TYPE_LGHT48; 248 249 /* enable default flags */ 250 flags = flags | (CMD_TYPE_NORMAL | CICE_NOCHECK | CCCE_NOCHECK | 251 MSBS_SGLEBLK | ACEN_DISABLE | BCE_DISABLE | DE_DISABLE); 252 253 if (cmd->resp_type & MMC_RSP_CRC) 254 flags |= CCCE_CHECK; 255 if (cmd->resp_type & MMC_RSP_OPCODE) 256 flags |= CICE_CHECK; 257 258 if (data) { 259 if ((cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK) || 260 (cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK)) { 261 flags |= (MSBS_MULTIBLK | BCE_ENABLE); 262 data->blocksize = 512; 263 writel(data->blocksize | (data->blocks << 16), 264 &mmc_base->blk); 265 } else 266 writel(data->blocksize | NBLK_STPCNT, &mmc_base->blk); 267 268 if (data->flags & MMC_DATA_READ) 269 flags |= (DP_DATA | DDIR_READ); 270 else 271 flags |= (DP_DATA | DDIR_WRITE); 272 } 273 274 writel(cmd->cmdarg, &mmc_base->arg); 275 writel((cmd->cmdidx << 24) | flags, &mmc_base->cmd); 276 277 start = get_timer(0); 278 do { 279 mmc_stat = readl(&mmc_base->stat); 280 if (get_timer(0) - start > MAX_RETRY_MS) { 281 printf("%s : timeout: No status update\n", __func__); 282 return TIMEOUT; 283 } 284 } while (!mmc_stat); 285 286 if ((mmc_stat & IE_CTO) != 0) 287 return TIMEOUT; 288 else if ((mmc_stat & ERRI_MASK) != 0) 289 return -1; 290 291 if (mmc_stat & CC_MASK) { 292 writel(CC_MASK, &mmc_base->stat); 293 if (cmd->resp_type & MMC_RSP_PRESENT) { 294 if (cmd->resp_type & MMC_RSP_136) { 295 /* response type 2 */ 296 cmd->response[3] = readl(&mmc_base->rsp10); 297 cmd->response[2] = readl(&mmc_base->rsp32); 298 cmd->response[1] = readl(&mmc_base->rsp54); 299 cmd->response[0] = readl(&mmc_base->rsp76); 300 } else 301 /* response types 1, 1b, 3, 4, 5, 6 */ 302 cmd->response[0] = readl(&mmc_base->rsp10); 303 } 304 } 305 306 if (data && (data->flags & MMC_DATA_READ)) { 307 mmc_read_data(mmc_base, data->dest, 308 data->blocksize * data->blocks); 309 } else if (data && (data->flags & MMC_DATA_WRITE)) { 310 mmc_write_data(mmc_base, data->src, 311 data->blocksize * data->blocks); 312 } 313 return 0; 314 } 315 316 static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size) 317 { 318 unsigned int *output_buf = (unsigned int *)buf; 319 unsigned int mmc_stat; 320 unsigned int count; 321 322 /* 323 * Start Polled Read 324 */ 325 count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size; 326 count /= 4; 327 328 while (size) { 329 ulong start = get_timer(0); 330 do { 331 mmc_stat = readl(&mmc_base->stat); 332 if (get_timer(0) - start > MAX_RETRY_MS) { 333 printf("%s: timedout waiting for status!\n", 334 __func__); 335 return TIMEOUT; 336 } 337 } while (mmc_stat == 0); 338 339 if ((mmc_stat & ERRI_MASK) != 0) 340 return 1; 341 342 if (mmc_stat & BRR_MASK) { 343 unsigned int k; 344 345 writel(readl(&mmc_base->stat) | BRR_MASK, 346 &mmc_base->stat); 347 for (k = 0; k < count; k++) { 348 *output_buf = readl(&mmc_base->data); 349 output_buf++; 350 } 351 size -= (count*4); 352 } 353 354 if (mmc_stat & BWR_MASK) 355 writel(readl(&mmc_base->stat) | BWR_MASK, 356 &mmc_base->stat); 357 358 if (mmc_stat & TC_MASK) { 359 writel(readl(&mmc_base->stat) | TC_MASK, 360 &mmc_base->stat); 361 break; 362 } 363 } 364 return 0; 365 } 366 367 static int mmc_write_data(struct hsmmc *mmc_base, const char *buf, 368 unsigned int size) 369 { 370 unsigned int *input_buf = (unsigned int *)buf; 371 unsigned int mmc_stat; 372 unsigned int count; 373 374 /* 375 * Start Polled Read 376 */ 377 count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size; 378 count /= 4; 379 380 while (size) { 381 ulong start = get_timer(0); 382 do { 383 mmc_stat = readl(&mmc_base->stat); 384 if (get_timer(0) - start > MAX_RETRY_MS) { 385 printf("%s: timedout waiting for status!\n", 386 __func__); 387 return TIMEOUT; 388 } 389 } while (mmc_stat == 0); 390 391 if ((mmc_stat & ERRI_MASK) != 0) 392 return 1; 393 394 if (mmc_stat & BWR_MASK) { 395 unsigned int k; 396 397 writel(readl(&mmc_base->stat) | BWR_MASK, 398 &mmc_base->stat); 399 for (k = 0; k < count; k++) { 400 writel(*input_buf, &mmc_base->data); 401 input_buf++; 402 } 403 size -= (count*4); 404 } 405 406 if (mmc_stat & BRR_MASK) 407 writel(readl(&mmc_base->stat) | BRR_MASK, 408 &mmc_base->stat); 409 410 if (mmc_stat & TC_MASK) { 411 writel(readl(&mmc_base->stat) | TC_MASK, 412 &mmc_base->stat); 413 break; 414 } 415 } 416 return 0; 417 } 418 419 static void mmc_set_ios(struct mmc *mmc) 420 { 421 struct hsmmc *mmc_base = (struct hsmmc *)mmc->priv; 422 unsigned int dsor = 0; 423 ulong start; 424 425 /* configue bus width */ 426 switch (mmc->bus_width) { 427 case 8: 428 writel(readl(&mmc_base->con) | DTW_8_BITMODE, 429 &mmc_base->con); 430 break; 431 432 case 4: 433 writel(readl(&mmc_base->con) & ~DTW_8_BITMODE, 434 &mmc_base->con); 435 writel(readl(&mmc_base->hctl) | DTW_4_BITMODE, 436 &mmc_base->hctl); 437 break; 438 439 case 1: 440 default: 441 writel(readl(&mmc_base->con) & ~DTW_8_BITMODE, 442 &mmc_base->con); 443 writel(readl(&mmc_base->hctl) & ~DTW_4_BITMODE, 444 &mmc_base->hctl); 445 break; 446 } 447 448 /* configure clock with 96Mhz system clock. 449 */ 450 if (mmc->clock != 0) { 451 dsor = (MMC_CLOCK_REFERENCE * 1000000 / mmc->clock); 452 if ((MMC_CLOCK_REFERENCE * 1000000) / dsor > mmc->clock) 453 dsor++; 454 } 455 456 mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK), 457 (ICE_STOP | DTO_15THDTO | CEN_DISABLE)); 458 459 mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK, 460 (dsor << CLKD_OFFSET) | ICE_OSCILLATE); 461 462 start = get_timer(0); 463 while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) { 464 if (get_timer(0) - start > MAX_RETRY_MS) { 465 printf("%s: timedout waiting for ics!\n", __func__); 466 return; 467 } 468 } 469 writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl); 470 } 471 472 int omap_mmc_init(int dev_index) 473 { 474 struct mmc *mmc; 475 476 mmc = &hsmmc_dev[dev_index]; 477 478 sprintf(mmc->name, "OMAP SD/MMC"); 479 mmc->send_cmd = mmc_send_cmd; 480 mmc->set_ios = mmc_set_ios; 481 mmc->init = mmc_init_setup; 482 mmc->getcd = NULL; 483 484 switch (dev_index) { 485 case 0: 486 mmc->priv = (struct hsmmc *)OMAP_HSMMC1_BASE; 487 break; 488 #ifdef OMAP_HSMMC2_BASE 489 case 1: 490 mmc->priv = (struct hsmmc *)OMAP_HSMMC2_BASE; 491 break; 492 #endif 493 #ifdef OMAP_HSMMC3_BASE 494 case 2: 495 mmc->priv = (struct hsmmc *)OMAP_HSMMC3_BASE; 496 break; 497 #endif 498 default: 499 mmc->priv = (struct hsmmc *)OMAP_HSMMC1_BASE; 500 return 1; 501 } 502 mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; 503 mmc->host_caps = MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS | 504 MMC_MODE_HC; 505 506 mmc->f_min = 400000; 507 mmc->f_max = 52000000; 508 509 mmc->b_max = 0; 510 511 #if defined(CONFIG_OMAP34XX) 512 /* 513 * Silicon revs 2.1 and older do not support multiblock transfers. 514 */ 515 if ((get_cpu_family() == CPU_OMAP34XX) && (get_cpu_rev() <= CPU_3XX_ES21)) 516 mmc->b_max = 1; 517 #endif 518 519 mmc_register(mmc); 520 521 return 0; 522 } 523