1 /* 2 * (C) Copyright 2008 3 * Texas Instruments, <www.ti.com> 4 * Sukumar Ghorai <s-ghorai@ti.com> 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation's version 2 of 12 * the License. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22 * MA 02111-1307 USA 23 */ 24 25 #include <config.h> 26 #include <common.h> 27 #include <mmc.h> 28 #include <part.h> 29 #include <i2c.h> 30 #include <twl4030.h> 31 #include <twl6030.h> 32 #include <asm/io.h> 33 #include <asm/arch/mmc_host_def.h> 34 #include <asm/arch/sys_proto.h> 35 36 /* common definitions for all OMAPs */ 37 #define SYSCTL_SRC (1 << 25) 38 #define SYSCTL_SRD (1 << 26) 39 40 /* If we fail after 1 second wait, something is really bad */ 41 #define MAX_RETRY_MS 1000 42 43 static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size); 44 static int mmc_write_data(struct hsmmc *mmc_base, const char *buf, 45 unsigned int siz); 46 static struct mmc hsmmc_dev[2]; 47 48 #if defined(CONFIG_OMAP44XX) && defined(CONFIG_TWL6030_POWER) 49 static void omap4_vmmc_pbias_config(struct mmc *mmc) 50 { 51 u32 value = 0; 52 struct omap4_sys_ctrl_regs *const ctrl = 53 (struct omap4_sys_ctrl_regs *)SYSCTRL_GENERAL_CORE_BASE; 54 55 56 value = readl(&ctrl->control_pbiaslite); 57 value &= ~(MMC1_PBIASLITE_PWRDNZ | MMC1_PWRDNZ); 58 writel(value, &ctrl->control_pbiaslite); 59 /* set VMMC to 3V */ 60 twl6030_power_mmc_init(); 61 value = readl(&ctrl->control_pbiaslite); 62 value |= MMC1_PBIASLITE_VMODE | MMC1_PBIASLITE_PWRDNZ | MMC1_PWRDNZ; 63 writel(value, &ctrl->control_pbiaslite); 64 } 65 #endif 66 67 unsigned char mmc_board_init(struct mmc *mmc) 68 { 69 #if defined(CONFIG_OMAP34XX) 70 t2_t *t2_base = (t2_t *)T2_BASE; 71 struct prcm *prcm_base = (struct prcm *)PRCM_BASE; 72 u32 pbias_lite; 73 74 pbias_lite = readl(&t2_base->pbias_lite); 75 pbias_lite &= ~(PBIASLITEPWRDNZ1 | PBIASLITEPWRDNZ0); 76 writel(pbias_lite, &t2_base->pbias_lite); 77 #endif 78 #if defined(CONFIG_TWL4030_POWER) 79 twl4030_power_mmc_init(); 80 mdelay(100); /* ramp-up delay from Linux code */ 81 #endif 82 #if defined(CONFIG_OMAP34XX) 83 writel(pbias_lite | PBIASLITEPWRDNZ1 | 84 PBIASSPEEDCTRL0 | PBIASLITEPWRDNZ0, 85 &t2_base->pbias_lite); 86 87 writel(readl(&t2_base->devconf0) | MMCSDIO1ADPCLKISEL, 88 &t2_base->devconf0); 89 90 writel(readl(&t2_base->devconf1) | MMCSDIO2ADPCLKISEL, 91 &t2_base->devconf1); 92 93 writel(readl(&prcm_base->fclken1_core) | 94 EN_MMC1 | EN_MMC2 | EN_MMC3, 95 &prcm_base->fclken1_core); 96 97 writel(readl(&prcm_base->iclken1_core) | 98 EN_MMC1 | EN_MMC2 | EN_MMC3, 99 &prcm_base->iclken1_core); 100 #endif 101 102 #if defined(CONFIG_OMAP44XX) && defined(CONFIG_TWL6030_POWER) 103 /* PBIAS config needed for MMC1 only */ 104 if (mmc->block_dev.dev == 0) 105 omap4_vmmc_pbias_config(mmc); 106 #endif 107 108 return 0; 109 } 110 111 void mmc_init_stream(struct hsmmc *mmc_base) 112 { 113 ulong start; 114 115 writel(readl(&mmc_base->con) | INIT_INITSTREAM, &mmc_base->con); 116 117 writel(MMC_CMD0, &mmc_base->cmd); 118 start = get_timer(0); 119 while (!(readl(&mmc_base->stat) & CC_MASK)) { 120 if (get_timer(0) - start > MAX_RETRY_MS) { 121 printf("%s: timedout waiting for cc!\n", __func__); 122 return; 123 } 124 } 125 writel(CC_MASK, &mmc_base->stat) 126 ; 127 writel(MMC_CMD0, &mmc_base->cmd) 128 ; 129 start = get_timer(0); 130 while (!(readl(&mmc_base->stat) & CC_MASK)) { 131 if (get_timer(0) - start > MAX_RETRY_MS) { 132 printf("%s: timedout waiting for cc2!\n", __func__); 133 return; 134 } 135 } 136 writel(readl(&mmc_base->con) & ~INIT_INITSTREAM, &mmc_base->con); 137 } 138 139 140 static int mmc_init_setup(struct mmc *mmc) 141 { 142 struct hsmmc *mmc_base = (struct hsmmc *)mmc->priv; 143 unsigned int reg_val; 144 unsigned int dsor; 145 ulong start; 146 147 mmc_board_init(mmc); 148 149 writel(readl(&mmc_base->sysconfig) | MMC_SOFTRESET, 150 &mmc_base->sysconfig); 151 start = get_timer(0); 152 while ((readl(&mmc_base->sysstatus) & RESETDONE) == 0) { 153 if (get_timer(0) - start > MAX_RETRY_MS) { 154 printf("%s: timedout waiting for cc2!\n", __func__); 155 return TIMEOUT; 156 } 157 } 158 writel(readl(&mmc_base->sysctl) | SOFTRESETALL, &mmc_base->sysctl); 159 start = get_timer(0); 160 while ((readl(&mmc_base->sysctl) & SOFTRESETALL) != 0x0) { 161 if (get_timer(0) - start > MAX_RETRY_MS) { 162 printf("%s: timedout waiting for softresetall!\n", 163 __func__); 164 return TIMEOUT; 165 } 166 } 167 writel(DTW_1_BITMODE | SDBP_PWROFF | SDVS_3V0, &mmc_base->hctl); 168 writel(readl(&mmc_base->capa) | VS30_3V0SUP | VS18_1V8SUP, 169 &mmc_base->capa); 170 171 reg_val = readl(&mmc_base->con) & RESERVED_MASK; 172 173 writel(CTPL_MMC_SD | reg_val | WPP_ACTIVEHIGH | CDP_ACTIVEHIGH | 174 MIT_CTO | DW8_1_4BITMODE | MODE_FUNC | STR_BLOCK | 175 HR_NOHOSTRESP | INIT_NOINIT | NOOPENDRAIN, &mmc_base->con); 176 177 dsor = 240; 178 mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK), 179 (ICE_STOP | DTO_15THDTO | CEN_DISABLE)); 180 mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK, 181 (dsor << CLKD_OFFSET) | ICE_OSCILLATE); 182 start = get_timer(0); 183 while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) { 184 if (get_timer(0) - start > MAX_RETRY_MS) { 185 printf("%s: timedout waiting for ics!\n", __func__); 186 return TIMEOUT; 187 } 188 } 189 writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl); 190 191 writel(readl(&mmc_base->hctl) | SDBP_PWRON, &mmc_base->hctl); 192 193 writel(IE_BADA | IE_CERR | IE_DEB | IE_DCRC | IE_DTO | IE_CIE | 194 IE_CEB | IE_CCRC | IE_CTO | IE_BRR | IE_BWR | IE_TC | IE_CC, 195 &mmc_base->ie); 196 197 mmc_init_stream(mmc_base); 198 199 return 0; 200 } 201 202 /* 203 * MMC controller internal finite state machine reset 204 * 205 * Used to reset command or data internal state machines, using respectively 206 * SRC or SRD bit of SYSCTL register 207 */ 208 static void mmc_reset_controller_fsm(struct hsmmc *mmc_base, u32 bit) 209 { 210 ulong start; 211 212 mmc_reg_out(&mmc_base->sysctl, bit, bit); 213 214 start = get_timer(0); 215 while ((readl(&mmc_base->sysctl) & bit) != 0) { 216 if (get_timer(0) - start > MAX_RETRY_MS) { 217 printf("%s: timedout waiting for sysctl %x to clear\n", 218 __func__, bit); 219 return; 220 } 221 } 222 } 223 224 static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, 225 struct mmc_data *data) 226 { 227 struct hsmmc *mmc_base = (struct hsmmc *)mmc->priv; 228 unsigned int flags, mmc_stat; 229 ulong start; 230 231 start = get_timer(0); 232 while ((readl(&mmc_base->pstate) & (DATI_MASK | CMDI_MASK)) != 0) { 233 if (get_timer(0) - start > MAX_RETRY_MS) { 234 printf("%s: timedout waiting on cmd inhibit to clear\n", 235 __func__); 236 return TIMEOUT; 237 } 238 } 239 writel(0xFFFFFFFF, &mmc_base->stat); 240 start = get_timer(0); 241 while (readl(&mmc_base->stat)) { 242 if (get_timer(0) - start > MAX_RETRY_MS) { 243 printf("%s: timedout waiting for STAT (%x) to clear\n", 244 __func__, readl(&mmc_base->stat)); 245 return TIMEOUT; 246 } 247 } 248 /* 249 * CMDREG 250 * CMDIDX[13:8] : Command index 251 * DATAPRNT[5] : Data Present Select 252 * ENCMDIDX[4] : Command Index Check Enable 253 * ENCMDCRC[3] : Command CRC Check Enable 254 * RSPTYP[1:0] 255 * 00 = No Response 256 * 01 = Length 136 257 * 10 = Length 48 258 * 11 = Length 48 Check busy after response 259 */ 260 /* Delay added before checking the status of frq change 261 * retry not supported by mmc.c(core file) 262 */ 263 if (cmd->cmdidx == SD_CMD_APP_SEND_SCR) 264 udelay(50000); /* wait 50 ms */ 265 266 if (!(cmd->resp_type & MMC_RSP_PRESENT)) 267 flags = 0; 268 else if (cmd->resp_type & MMC_RSP_136) 269 flags = RSP_TYPE_LGHT136 | CICE_NOCHECK; 270 else if (cmd->resp_type & MMC_RSP_BUSY) 271 flags = RSP_TYPE_LGHT48B; 272 else 273 flags = RSP_TYPE_LGHT48; 274 275 /* enable default flags */ 276 flags = flags | (CMD_TYPE_NORMAL | CICE_NOCHECK | CCCE_NOCHECK | 277 MSBS_SGLEBLK | ACEN_DISABLE | BCE_DISABLE | DE_DISABLE); 278 279 if (cmd->resp_type & MMC_RSP_CRC) 280 flags |= CCCE_CHECK; 281 if (cmd->resp_type & MMC_RSP_OPCODE) 282 flags |= CICE_CHECK; 283 284 if (data) { 285 if ((cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK) || 286 (cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK)) { 287 flags |= (MSBS_MULTIBLK | BCE_ENABLE); 288 data->blocksize = 512; 289 writel(data->blocksize | (data->blocks << 16), 290 &mmc_base->blk); 291 } else 292 writel(data->blocksize | NBLK_STPCNT, &mmc_base->blk); 293 294 if (data->flags & MMC_DATA_READ) 295 flags |= (DP_DATA | DDIR_READ); 296 else 297 flags |= (DP_DATA | DDIR_WRITE); 298 } 299 300 writel(cmd->cmdarg, &mmc_base->arg); 301 writel((cmd->cmdidx << 24) | flags, &mmc_base->cmd); 302 303 start = get_timer(0); 304 do { 305 mmc_stat = readl(&mmc_base->stat); 306 if (get_timer(0) - start > MAX_RETRY_MS) { 307 printf("%s : timeout: No status update\n", __func__); 308 return TIMEOUT; 309 } 310 } while (!mmc_stat); 311 312 if ((mmc_stat & IE_CTO) != 0) { 313 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC); 314 return TIMEOUT; 315 } else if ((mmc_stat & ERRI_MASK) != 0) 316 return -1; 317 318 if (mmc_stat & CC_MASK) { 319 writel(CC_MASK, &mmc_base->stat); 320 if (cmd->resp_type & MMC_RSP_PRESENT) { 321 if (cmd->resp_type & MMC_RSP_136) { 322 /* response type 2 */ 323 cmd->response[3] = readl(&mmc_base->rsp10); 324 cmd->response[2] = readl(&mmc_base->rsp32); 325 cmd->response[1] = readl(&mmc_base->rsp54); 326 cmd->response[0] = readl(&mmc_base->rsp76); 327 } else 328 /* response types 1, 1b, 3, 4, 5, 6 */ 329 cmd->response[0] = readl(&mmc_base->rsp10); 330 } 331 } 332 333 if (data && (data->flags & MMC_DATA_READ)) { 334 mmc_read_data(mmc_base, data->dest, 335 data->blocksize * data->blocks); 336 } else if (data && (data->flags & MMC_DATA_WRITE)) { 337 mmc_write_data(mmc_base, data->src, 338 data->blocksize * data->blocks); 339 } 340 return 0; 341 } 342 343 static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size) 344 { 345 unsigned int *output_buf = (unsigned int *)buf; 346 unsigned int mmc_stat; 347 unsigned int count; 348 349 /* 350 * Start Polled Read 351 */ 352 count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size; 353 count /= 4; 354 355 while (size) { 356 ulong start = get_timer(0); 357 do { 358 mmc_stat = readl(&mmc_base->stat); 359 if (get_timer(0) - start > MAX_RETRY_MS) { 360 printf("%s: timedout waiting for status!\n", 361 __func__); 362 return TIMEOUT; 363 } 364 } while (mmc_stat == 0); 365 366 if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0) 367 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD); 368 369 if ((mmc_stat & ERRI_MASK) != 0) 370 return 1; 371 372 if (mmc_stat & BRR_MASK) { 373 unsigned int k; 374 375 writel(readl(&mmc_base->stat) | BRR_MASK, 376 &mmc_base->stat); 377 for (k = 0; k < count; k++) { 378 *output_buf = readl(&mmc_base->data); 379 output_buf++; 380 } 381 size -= (count*4); 382 } 383 384 if (mmc_stat & BWR_MASK) 385 writel(readl(&mmc_base->stat) | BWR_MASK, 386 &mmc_base->stat); 387 388 if (mmc_stat & TC_MASK) { 389 writel(readl(&mmc_base->stat) | TC_MASK, 390 &mmc_base->stat); 391 break; 392 } 393 } 394 return 0; 395 } 396 397 static int mmc_write_data(struct hsmmc *mmc_base, const char *buf, 398 unsigned int size) 399 { 400 unsigned int *input_buf = (unsigned int *)buf; 401 unsigned int mmc_stat; 402 unsigned int count; 403 404 /* 405 * Start Polled Read 406 */ 407 count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size; 408 count /= 4; 409 410 while (size) { 411 ulong start = get_timer(0); 412 do { 413 mmc_stat = readl(&mmc_base->stat); 414 if (get_timer(0) - start > MAX_RETRY_MS) { 415 printf("%s: timedout waiting for status!\n", 416 __func__); 417 return TIMEOUT; 418 } 419 } while (mmc_stat == 0); 420 421 if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0) 422 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD); 423 424 if ((mmc_stat & ERRI_MASK) != 0) 425 return 1; 426 427 if (mmc_stat & BWR_MASK) { 428 unsigned int k; 429 430 writel(readl(&mmc_base->stat) | BWR_MASK, 431 &mmc_base->stat); 432 for (k = 0; k < count; k++) { 433 writel(*input_buf, &mmc_base->data); 434 input_buf++; 435 } 436 size -= (count*4); 437 } 438 439 if (mmc_stat & BRR_MASK) 440 writel(readl(&mmc_base->stat) | BRR_MASK, 441 &mmc_base->stat); 442 443 if (mmc_stat & TC_MASK) { 444 writel(readl(&mmc_base->stat) | TC_MASK, 445 &mmc_base->stat); 446 break; 447 } 448 } 449 return 0; 450 } 451 452 static void mmc_set_ios(struct mmc *mmc) 453 { 454 struct hsmmc *mmc_base = (struct hsmmc *)mmc->priv; 455 unsigned int dsor = 0; 456 ulong start; 457 458 /* configue bus width */ 459 switch (mmc->bus_width) { 460 case 8: 461 writel(readl(&mmc_base->con) | DTW_8_BITMODE, 462 &mmc_base->con); 463 break; 464 465 case 4: 466 writel(readl(&mmc_base->con) & ~DTW_8_BITMODE, 467 &mmc_base->con); 468 writel(readl(&mmc_base->hctl) | DTW_4_BITMODE, 469 &mmc_base->hctl); 470 break; 471 472 case 1: 473 default: 474 writel(readl(&mmc_base->con) & ~DTW_8_BITMODE, 475 &mmc_base->con); 476 writel(readl(&mmc_base->hctl) & ~DTW_4_BITMODE, 477 &mmc_base->hctl); 478 break; 479 } 480 481 /* configure clock with 96Mhz system clock. 482 */ 483 if (mmc->clock != 0) { 484 dsor = (MMC_CLOCK_REFERENCE * 1000000 / mmc->clock); 485 if ((MMC_CLOCK_REFERENCE * 1000000) / dsor > mmc->clock) 486 dsor++; 487 } 488 489 mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK), 490 (ICE_STOP | DTO_15THDTO | CEN_DISABLE)); 491 492 mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK, 493 (dsor << CLKD_OFFSET) | ICE_OSCILLATE); 494 495 start = get_timer(0); 496 while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) { 497 if (get_timer(0) - start > MAX_RETRY_MS) { 498 printf("%s: timedout waiting for ics!\n", __func__); 499 return; 500 } 501 } 502 writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl); 503 } 504 505 int omap_mmc_init(int dev_index) 506 { 507 struct mmc *mmc; 508 509 mmc = &hsmmc_dev[dev_index]; 510 511 sprintf(mmc->name, "OMAP SD/MMC"); 512 mmc->send_cmd = mmc_send_cmd; 513 mmc->set_ios = mmc_set_ios; 514 mmc->init = mmc_init_setup; 515 mmc->getcd = NULL; 516 517 switch (dev_index) { 518 case 0: 519 mmc->priv = (struct hsmmc *)OMAP_HSMMC1_BASE; 520 break; 521 #ifdef OMAP_HSMMC2_BASE 522 case 1: 523 mmc->priv = (struct hsmmc *)OMAP_HSMMC2_BASE; 524 break; 525 #endif 526 #ifdef OMAP_HSMMC3_BASE 527 case 2: 528 mmc->priv = (struct hsmmc *)OMAP_HSMMC3_BASE; 529 break; 530 #endif 531 default: 532 mmc->priv = (struct hsmmc *)OMAP_HSMMC1_BASE; 533 return 1; 534 } 535 mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; 536 mmc->host_caps = MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS | 537 MMC_MODE_HC; 538 539 mmc->f_min = 400000; 540 mmc->f_max = 52000000; 541 542 mmc->b_max = 0; 543 544 #if defined(CONFIG_OMAP34XX) 545 /* 546 * Silicon revs 2.1 and older do not support multiblock transfers. 547 */ 548 if ((get_cpu_family() == CPU_OMAP34XX) && (get_cpu_rev() <= CPU_3XX_ES21)) 549 mmc->b_max = 1; 550 #endif 551 552 mmc_register(mmc); 553 554 return 0; 555 } 556