1 /* 2 * Copyright 2008, Freescale Semiconductor, Inc 3 * Andy Fleming 4 * 5 * Based vaguely on the Linux code 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #include <config.h> 11 #include <common.h> 12 #include <command.h> 13 #include <dm.h> 14 #include <dm/device-internal.h> 15 #include <errno.h> 16 #include <mmc.h> 17 #include <part.h> 18 #include <malloc.h> 19 #include <memalign.h> 20 #include <linux/list.h> 21 #include <div64.h> 22 #include "mmc_private.h" 23 24 __weak int board_mmc_getwp(struct mmc *mmc) 25 { 26 return -1; 27 } 28 29 int mmc_getwp(struct mmc *mmc) 30 { 31 int wp; 32 33 wp = board_mmc_getwp(mmc); 34 35 if (wp < 0) { 36 if (mmc->cfg->ops->getwp) 37 wp = mmc->cfg->ops->getwp(mmc); 38 else 39 wp = 0; 40 } 41 42 return wp; 43 } 44 45 __weak int board_mmc_getcd(struct mmc *mmc) 46 { 47 return -1; 48 } 49 50 int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) 51 { 52 int ret; 53 54 #ifdef CONFIG_MMC_TRACE 55 int i; 56 u8 *ptr; 57 58 printf("CMD_SEND:%d\n", cmd->cmdidx); 59 printf("\t\tARG\t\t\t 0x%08X\n", cmd->cmdarg); 60 ret = mmc->cfg->ops->send_cmd(mmc, cmd, data); 61 if (ret) { 62 printf("\t\tRET\t\t\t %d\n", ret); 63 } else { 64 switch (cmd->resp_type) { 65 case MMC_RSP_NONE: 66 printf("\t\tMMC_RSP_NONE\n"); 67 break; 68 case MMC_RSP_R1: 69 printf("\t\tMMC_RSP_R1,5,6,7 \t 0x%08X \n", 70 cmd->response[0]); 71 break; 72 case MMC_RSP_R1b: 73 printf("\t\tMMC_RSP_R1b\t\t 0x%08X \n", 74 cmd->response[0]); 75 break; 76 case MMC_RSP_R2: 77 printf("\t\tMMC_RSP_R2\t\t 0x%08X \n", 78 cmd->response[0]); 79 printf("\t\t \t\t 0x%08X \n", 80 cmd->response[1]); 81 printf("\t\t \t\t 0x%08X \n", 82 cmd->response[2]); 83 printf("\t\t \t\t 0x%08X \n", 84 cmd->response[3]); 85 printf("\n"); 86 printf("\t\t\t\t\tDUMPING DATA\n"); 87 for (i = 0; i < 4; i++) { 88 int j; 89 printf("\t\t\t\t\t%03d - ", i*4); 90 ptr = (u8 *)&cmd->response[i]; 91 ptr += 3; 92 for (j = 0; j < 4; j++) 93 printf("%02X ", *ptr--); 94 printf("\n"); 95 } 96 break; 97 case MMC_RSP_R3: 98 printf("\t\tMMC_RSP_R3,4\t\t 0x%08X \n", 99 cmd->response[0]); 100 break; 101 default: 102 printf("\t\tERROR MMC rsp not supported\n"); 103 break; 104 } 105 } 106 #else 107 ret = mmc->cfg->ops->send_cmd(mmc, cmd, data); 108 #endif 109 return ret; 110 } 111 112 int mmc_send_status(struct mmc *mmc, int timeout) 113 { 114 struct mmc_cmd cmd; 115 int err, retries = 5; 116 #ifdef CONFIG_MMC_TRACE 117 int status; 118 #endif 119 120 cmd.cmdidx = MMC_CMD_SEND_STATUS; 121 cmd.resp_type = MMC_RSP_R1; 122 if (!mmc_host_is_spi(mmc)) 123 cmd.cmdarg = mmc->rca << 16; 124 125 while (1) { 126 err = mmc_send_cmd(mmc, &cmd, NULL); 127 if (!err) { 128 if ((cmd.response[0] & MMC_STATUS_RDY_FOR_DATA) && 129 (cmd.response[0] & MMC_STATUS_CURR_STATE) != 130 MMC_STATE_PRG) 131 break; 132 else if (cmd.response[0] & MMC_STATUS_MASK) { 133 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) 134 printf("Status Error: 0x%08X\n", 135 cmd.response[0]); 136 #endif 137 return COMM_ERR; 138 } 139 } else if (--retries < 0) 140 return err; 141 142 if (timeout-- <= 0) 143 break; 144 145 udelay(1000); 146 } 147 148 #ifdef CONFIG_MMC_TRACE 149 status = (cmd.response[0] & MMC_STATUS_CURR_STATE) >> 9; 150 printf("CURR STATE:%d\n", status); 151 #endif 152 if (timeout <= 0) { 153 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) 154 printf("Timeout waiting card ready\n"); 155 #endif 156 return TIMEOUT; 157 } 158 159 return 0; 160 } 161 162 int mmc_set_blocklen(struct mmc *mmc, int len) 163 { 164 struct mmc_cmd cmd; 165 166 if (mmc->ddr_mode) 167 return 0; 168 169 cmd.cmdidx = MMC_CMD_SET_BLOCKLEN; 170 cmd.resp_type = MMC_RSP_R1; 171 cmd.cmdarg = len; 172 173 return mmc_send_cmd(mmc, &cmd, NULL); 174 } 175 176 static int mmc_read_blocks(struct mmc *mmc, void *dst, lbaint_t start, 177 lbaint_t blkcnt) 178 { 179 struct mmc_cmd cmd; 180 struct mmc_data data; 181 182 if (blkcnt > 1) 183 cmd.cmdidx = MMC_CMD_READ_MULTIPLE_BLOCK; 184 else 185 cmd.cmdidx = MMC_CMD_READ_SINGLE_BLOCK; 186 187 if (mmc->high_capacity) 188 cmd.cmdarg = start; 189 else 190 cmd.cmdarg = start * mmc->read_bl_len; 191 192 cmd.resp_type = MMC_RSP_R1; 193 194 data.dest = dst; 195 data.blocks = blkcnt; 196 data.blocksize = mmc->read_bl_len; 197 data.flags = MMC_DATA_READ; 198 199 if (mmc_send_cmd(mmc, &cmd, &data)) 200 return 0; 201 202 if (blkcnt > 1) { 203 cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION; 204 cmd.cmdarg = 0; 205 cmd.resp_type = MMC_RSP_R1b; 206 if (mmc_send_cmd(mmc, &cmd, NULL)) { 207 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) 208 printf("mmc fail to send stop cmd\n"); 209 #endif 210 return 0; 211 } 212 } 213 214 return blkcnt; 215 } 216 217 #ifdef CONFIG_BLK 218 ulong mmc_bread(struct udevice *dev, lbaint_t start, lbaint_t blkcnt, void *dst) 219 #else 220 ulong mmc_bread(struct blk_desc *block_dev, lbaint_t start, lbaint_t blkcnt, 221 void *dst) 222 #endif 223 { 224 #ifdef CONFIG_BLK 225 struct blk_desc *block_dev = dev_get_uclass_platdata(dev); 226 #endif 227 int dev_num = block_dev->devnum; 228 int err; 229 lbaint_t cur, blocks_todo = blkcnt; 230 231 if (blkcnt == 0) 232 return 0; 233 234 struct mmc *mmc = find_mmc_device(dev_num); 235 if (!mmc) 236 return 0; 237 238 err = blk_dselect_hwpart(block_dev, block_dev->hwpart); 239 if (err < 0) 240 return 0; 241 242 if ((start + blkcnt) > block_dev->lba) { 243 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) 244 printf("MMC: block number 0x" LBAF " exceeds max(0x" LBAF ")\n", 245 start + blkcnt, block_dev->lba); 246 #endif 247 return 0; 248 } 249 250 if (mmc_set_blocklen(mmc, mmc->read_bl_len)) { 251 debug("%s: Failed to set blocklen\n", __func__); 252 return 0; 253 } 254 255 do { 256 cur = (blocks_todo > mmc->cfg->b_max) ? 257 mmc->cfg->b_max : blocks_todo; 258 if (mmc_read_blocks(mmc, dst, start, cur) != cur) { 259 debug("%s: Failed to read blocks\n", __func__); 260 return 0; 261 } 262 blocks_todo -= cur; 263 start += cur; 264 dst += cur * mmc->read_bl_len; 265 } while (blocks_todo > 0); 266 267 return blkcnt; 268 } 269 270 static int mmc_go_idle(struct mmc *mmc) 271 { 272 struct mmc_cmd cmd; 273 int err; 274 275 udelay(1000); 276 277 cmd.cmdidx = MMC_CMD_GO_IDLE_STATE; 278 cmd.cmdarg = 0; 279 cmd.resp_type = MMC_RSP_NONE; 280 281 err = mmc_send_cmd(mmc, &cmd, NULL); 282 283 if (err) 284 return err; 285 286 udelay(2000); 287 288 return 0; 289 } 290 291 static int sd_send_op_cond(struct mmc *mmc) 292 { 293 int timeout = 1000; 294 int err; 295 struct mmc_cmd cmd; 296 297 while (1) { 298 cmd.cmdidx = MMC_CMD_APP_CMD; 299 cmd.resp_type = MMC_RSP_R1; 300 cmd.cmdarg = 0; 301 302 err = mmc_send_cmd(mmc, &cmd, NULL); 303 304 if (err) 305 return err; 306 307 cmd.cmdidx = SD_CMD_APP_SEND_OP_COND; 308 cmd.resp_type = MMC_RSP_R3; 309 310 /* 311 * Most cards do not answer if some reserved bits 312 * in the ocr are set. However, Some controller 313 * can set bit 7 (reserved for low voltages), but 314 * how to manage low voltages SD card is not yet 315 * specified. 316 */ 317 cmd.cmdarg = mmc_host_is_spi(mmc) ? 0 : 318 (mmc->cfg->voltages & 0xff8000); 319 320 if (mmc->version == SD_VERSION_2) 321 cmd.cmdarg |= OCR_HCS; 322 323 err = mmc_send_cmd(mmc, &cmd, NULL); 324 325 if (err) 326 return err; 327 328 if (cmd.response[0] & OCR_BUSY) 329 break; 330 331 if (timeout-- <= 0) 332 return UNUSABLE_ERR; 333 334 udelay(1000); 335 } 336 337 if (mmc->version != SD_VERSION_2) 338 mmc->version = SD_VERSION_1_0; 339 340 if (mmc_host_is_spi(mmc)) { /* read OCR for spi */ 341 cmd.cmdidx = MMC_CMD_SPI_READ_OCR; 342 cmd.resp_type = MMC_RSP_R3; 343 cmd.cmdarg = 0; 344 345 err = mmc_send_cmd(mmc, &cmd, NULL); 346 347 if (err) 348 return err; 349 } 350 351 mmc->ocr = cmd.response[0]; 352 353 mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS); 354 mmc->rca = 0; 355 356 return 0; 357 } 358 359 static int mmc_send_op_cond_iter(struct mmc *mmc, int use_arg) 360 { 361 struct mmc_cmd cmd; 362 int err; 363 364 cmd.cmdidx = MMC_CMD_SEND_OP_COND; 365 cmd.resp_type = MMC_RSP_R3; 366 cmd.cmdarg = 0; 367 if (use_arg && !mmc_host_is_spi(mmc)) 368 cmd.cmdarg = OCR_HCS | 369 (mmc->cfg->voltages & 370 (mmc->ocr & OCR_VOLTAGE_MASK)) | 371 (mmc->ocr & OCR_ACCESS_MODE); 372 373 err = mmc_send_cmd(mmc, &cmd, NULL); 374 if (err) 375 return err; 376 mmc->ocr = cmd.response[0]; 377 return 0; 378 } 379 380 static int mmc_send_op_cond(struct mmc *mmc) 381 { 382 int err, i; 383 384 /* Some cards seem to need this */ 385 mmc_go_idle(mmc); 386 387 /* Asking to the card its capabilities */ 388 for (i = 0; i < 2; i++) { 389 err = mmc_send_op_cond_iter(mmc, i != 0); 390 if (err) 391 return err; 392 393 /* exit if not busy (flag seems to be inverted) */ 394 if (mmc->ocr & OCR_BUSY) 395 break; 396 } 397 mmc->op_cond_pending = 1; 398 return 0; 399 } 400 401 static int mmc_complete_op_cond(struct mmc *mmc) 402 { 403 struct mmc_cmd cmd; 404 int timeout = 1000; 405 uint start; 406 int err; 407 408 mmc->op_cond_pending = 0; 409 if (!(mmc->ocr & OCR_BUSY)) { 410 start = get_timer(0); 411 while (1) { 412 err = mmc_send_op_cond_iter(mmc, 1); 413 if (err) 414 return err; 415 if (mmc->ocr & OCR_BUSY) 416 break; 417 if (get_timer(start) > timeout) 418 return UNUSABLE_ERR; 419 udelay(100); 420 } 421 } 422 423 if (mmc_host_is_spi(mmc)) { /* read OCR for spi */ 424 cmd.cmdidx = MMC_CMD_SPI_READ_OCR; 425 cmd.resp_type = MMC_RSP_R3; 426 cmd.cmdarg = 0; 427 428 err = mmc_send_cmd(mmc, &cmd, NULL); 429 430 if (err) 431 return err; 432 433 mmc->ocr = cmd.response[0]; 434 } 435 436 mmc->version = MMC_VERSION_UNKNOWN; 437 438 mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS); 439 mmc->rca = 1; 440 441 return 0; 442 } 443 444 445 static int mmc_send_ext_csd(struct mmc *mmc, u8 *ext_csd) 446 { 447 struct mmc_cmd cmd; 448 struct mmc_data data; 449 int err; 450 451 /* Get the Card Status Register */ 452 cmd.cmdidx = MMC_CMD_SEND_EXT_CSD; 453 cmd.resp_type = MMC_RSP_R1; 454 cmd.cmdarg = 0; 455 456 data.dest = (char *)ext_csd; 457 data.blocks = 1; 458 data.blocksize = MMC_MAX_BLOCK_LEN; 459 data.flags = MMC_DATA_READ; 460 461 err = mmc_send_cmd(mmc, &cmd, &data); 462 463 return err; 464 } 465 466 467 static int mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value) 468 { 469 struct mmc_cmd cmd; 470 int timeout = 1000; 471 int ret; 472 473 cmd.cmdidx = MMC_CMD_SWITCH; 474 cmd.resp_type = MMC_RSP_R1b; 475 cmd.cmdarg = (MMC_SWITCH_MODE_WRITE_BYTE << 24) | 476 (index << 16) | 477 (value << 8); 478 479 ret = mmc_send_cmd(mmc, &cmd, NULL); 480 481 /* Waiting for the ready status */ 482 if (!ret) 483 ret = mmc_send_status(mmc, timeout); 484 485 return ret; 486 487 } 488 489 static int mmc_change_freq(struct mmc *mmc) 490 { 491 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN); 492 char cardtype; 493 int err; 494 495 mmc->card_caps = 0; 496 497 if (mmc_host_is_spi(mmc)) 498 return 0; 499 500 /* Only version 4 supports high-speed */ 501 if (mmc->version < MMC_VERSION_4) 502 return 0; 503 504 mmc->card_caps |= MMC_MODE_4BIT | MMC_MODE_8BIT; 505 506 err = mmc_send_ext_csd(mmc, ext_csd); 507 508 if (err) 509 return err; 510 511 cardtype = ext_csd[EXT_CSD_CARD_TYPE] & 0xf; 512 513 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_HS_TIMING, 1); 514 515 if (err) 516 return err; 517 518 /* Now check to see that it worked */ 519 err = mmc_send_ext_csd(mmc, ext_csd); 520 521 if (err) 522 return err; 523 524 /* No high-speed support */ 525 if (!ext_csd[EXT_CSD_HS_TIMING]) 526 return 0; 527 528 /* High Speed is set, there are two types: 52MHz and 26MHz */ 529 if (cardtype & EXT_CSD_CARD_TYPE_52) { 530 if (cardtype & EXT_CSD_CARD_TYPE_DDR_1_8V) 531 mmc->card_caps |= MMC_MODE_DDR_52MHz; 532 mmc->card_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS; 533 } else { 534 mmc->card_caps |= MMC_MODE_HS; 535 } 536 537 return 0; 538 } 539 540 static int mmc_set_capacity(struct mmc *mmc, int part_num) 541 { 542 switch (part_num) { 543 case 0: 544 mmc->capacity = mmc->capacity_user; 545 break; 546 case 1: 547 case 2: 548 mmc->capacity = mmc->capacity_boot; 549 break; 550 case 3: 551 mmc->capacity = mmc->capacity_rpmb; 552 break; 553 case 4: 554 case 5: 555 case 6: 556 case 7: 557 mmc->capacity = mmc->capacity_gp[part_num - 4]; 558 break; 559 default: 560 return -1; 561 } 562 563 mmc_get_blk_desc(mmc)->lba = lldiv(mmc->capacity, mmc->read_bl_len); 564 565 return 0; 566 } 567 568 int mmc_switch_part(struct mmc *mmc, unsigned int part_num) 569 { 570 int ret; 571 572 ret = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_PART_CONF, 573 (mmc->part_config & ~PART_ACCESS_MASK) 574 | (part_num & PART_ACCESS_MASK)); 575 576 /* 577 * Set the capacity if the switch succeeded or was intended 578 * to return to representing the raw device. 579 */ 580 if ((ret == 0) || ((ret == -ENODEV) && (part_num == 0))) { 581 ret = mmc_set_capacity(mmc, part_num); 582 mmc_get_blk_desc(mmc)->hwpart = part_num; 583 } 584 585 return ret; 586 } 587 588 #ifndef CONFIG_BLK 589 static int mmc_select_hwpartp(struct blk_desc *desc, int hwpart) 590 { 591 struct mmc *mmc = find_mmc_device(desc->devnum); 592 int ret; 593 594 if (!mmc) 595 return -ENODEV; 596 597 if (mmc->block_dev.hwpart == hwpart) 598 return 0; 599 600 if (mmc->part_config == MMCPART_NOAVAILABLE) 601 return -EMEDIUMTYPE; 602 603 ret = mmc_switch_part(mmc, hwpart); 604 if (ret) 605 return ret; 606 607 return 0; 608 } 609 #endif 610 611 int mmc_hwpart_config(struct mmc *mmc, 612 const struct mmc_hwpart_conf *conf, 613 enum mmc_hwpart_conf_mode mode) 614 { 615 u8 part_attrs = 0; 616 u32 enh_size_mult; 617 u32 enh_start_addr; 618 u32 gp_size_mult[4]; 619 u32 max_enh_size_mult; 620 u32 tot_enh_size_mult = 0; 621 u8 wr_rel_set; 622 int i, pidx, err; 623 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN); 624 625 if (mode < MMC_HWPART_CONF_CHECK || mode > MMC_HWPART_CONF_COMPLETE) 626 return -EINVAL; 627 628 if (IS_SD(mmc) || (mmc->version < MMC_VERSION_4_41)) { 629 printf("eMMC >= 4.4 required for enhanced user data area\n"); 630 return -EMEDIUMTYPE; 631 } 632 633 if (!(mmc->part_support & PART_SUPPORT)) { 634 printf("Card does not support partitioning\n"); 635 return -EMEDIUMTYPE; 636 } 637 638 if (!mmc->hc_wp_grp_size) { 639 printf("Card does not define HC WP group size\n"); 640 return -EMEDIUMTYPE; 641 } 642 643 /* check partition alignment and total enhanced size */ 644 if (conf->user.enh_size) { 645 if (conf->user.enh_size % mmc->hc_wp_grp_size || 646 conf->user.enh_start % mmc->hc_wp_grp_size) { 647 printf("User data enhanced area not HC WP group " 648 "size aligned\n"); 649 return -EINVAL; 650 } 651 part_attrs |= EXT_CSD_ENH_USR; 652 enh_size_mult = conf->user.enh_size / mmc->hc_wp_grp_size; 653 if (mmc->high_capacity) { 654 enh_start_addr = conf->user.enh_start; 655 } else { 656 enh_start_addr = (conf->user.enh_start << 9); 657 } 658 } else { 659 enh_size_mult = 0; 660 enh_start_addr = 0; 661 } 662 tot_enh_size_mult += enh_size_mult; 663 664 for (pidx = 0; pidx < 4; pidx++) { 665 if (conf->gp_part[pidx].size % mmc->hc_wp_grp_size) { 666 printf("GP%i partition not HC WP group size " 667 "aligned\n", pidx+1); 668 return -EINVAL; 669 } 670 gp_size_mult[pidx] = conf->gp_part[pidx].size / mmc->hc_wp_grp_size; 671 if (conf->gp_part[pidx].size && conf->gp_part[pidx].enhanced) { 672 part_attrs |= EXT_CSD_ENH_GP(pidx); 673 tot_enh_size_mult += gp_size_mult[pidx]; 674 } 675 } 676 677 if (part_attrs && ! (mmc->part_support & ENHNCD_SUPPORT)) { 678 printf("Card does not support enhanced attribute\n"); 679 return -EMEDIUMTYPE; 680 } 681 682 err = mmc_send_ext_csd(mmc, ext_csd); 683 if (err) 684 return err; 685 686 max_enh_size_mult = 687 (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+2] << 16) + 688 (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+1] << 8) + 689 ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT]; 690 if (tot_enh_size_mult > max_enh_size_mult) { 691 printf("Total enhanced size exceeds maximum (%u > %u)\n", 692 tot_enh_size_mult, max_enh_size_mult); 693 return -EMEDIUMTYPE; 694 } 695 696 /* The default value of EXT_CSD_WR_REL_SET is device 697 * dependent, the values can only be changed if the 698 * EXT_CSD_HS_CTRL_REL bit is set. The values can be 699 * changed only once and before partitioning is completed. */ 700 wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET]; 701 if (conf->user.wr_rel_change) { 702 if (conf->user.wr_rel_set) 703 wr_rel_set |= EXT_CSD_WR_DATA_REL_USR; 704 else 705 wr_rel_set &= ~EXT_CSD_WR_DATA_REL_USR; 706 } 707 for (pidx = 0; pidx < 4; pidx++) { 708 if (conf->gp_part[pidx].wr_rel_change) { 709 if (conf->gp_part[pidx].wr_rel_set) 710 wr_rel_set |= EXT_CSD_WR_DATA_REL_GP(pidx); 711 else 712 wr_rel_set &= ~EXT_CSD_WR_DATA_REL_GP(pidx); 713 } 714 } 715 716 if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET] && 717 !(ext_csd[EXT_CSD_WR_REL_PARAM] & EXT_CSD_HS_CTRL_REL)) { 718 puts("Card does not support host controlled partition write " 719 "reliability settings\n"); 720 return -EMEDIUMTYPE; 721 } 722 723 if (ext_csd[EXT_CSD_PARTITION_SETTING] & 724 EXT_CSD_PARTITION_SETTING_COMPLETED) { 725 printf("Card already partitioned\n"); 726 return -EPERM; 727 } 728 729 if (mode == MMC_HWPART_CONF_CHECK) 730 return 0; 731 732 /* Partitioning requires high-capacity size definitions */ 733 if (!(ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01)) { 734 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, 735 EXT_CSD_ERASE_GROUP_DEF, 1); 736 737 if (err) 738 return err; 739 740 ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1; 741 742 /* update erase group size to be high-capacity */ 743 mmc->erase_grp_size = 744 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024; 745 746 } 747 748 /* all OK, write the configuration */ 749 for (i = 0; i < 4; i++) { 750 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, 751 EXT_CSD_ENH_START_ADDR+i, 752 (enh_start_addr >> (i*8)) & 0xFF); 753 if (err) 754 return err; 755 } 756 for (i = 0; i < 3; i++) { 757 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, 758 EXT_CSD_ENH_SIZE_MULT+i, 759 (enh_size_mult >> (i*8)) & 0xFF); 760 if (err) 761 return err; 762 } 763 for (pidx = 0; pidx < 4; pidx++) { 764 for (i = 0; i < 3; i++) { 765 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, 766 EXT_CSD_GP_SIZE_MULT+pidx*3+i, 767 (gp_size_mult[pidx] >> (i*8)) & 0xFF); 768 if (err) 769 return err; 770 } 771 } 772 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, 773 EXT_CSD_PARTITIONS_ATTRIBUTE, part_attrs); 774 if (err) 775 return err; 776 777 if (mode == MMC_HWPART_CONF_SET) 778 return 0; 779 780 /* The WR_REL_SET is a write-once register but shall be 781 * written before setting PART_SETTING_COMPLETED. As it is 782 * write-once we can only write it when completing the 783 * partitioning. */ 784 if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET]) { 785 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, 786 EXT_CSD_WR_REL_SET, wr_rel_set); 787 if (err) 788 return err; 789 } 790 791 /* Setting PART_SETTING_COMPLETED confirms the partition 792 * configuration but it only becomes effective after power 793 * cycle, so we do not adjust the partition related settings 794 * in the mmc struct. */ 795 796 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, 797 EXT_CSD_PARTITION_SETTING, 798 EXT_CSD_PARTITION_SETTING_COMPLETED); 799 if (err) 800 return err; 801 802 return 0; 803 } 804 805 int mmc_getcd(struct mmc *mmc) 806 { 807 int cd; 808 809 cd = board_mmc_getcd(mmc); 810 811 if (cd < 0) { 812 if (mmc->cfg->ops->getcd) 813 cd = mmc->cfg->ops->getcd(mmc); 814 else 815 cd = 1; 816 } 817 818 return cd; 819 } 820 821 static int sd_switch(struct mmc *mmc, int mode, int group, u8 value, u8 *resp) 822 { 823 struct mmc_cmd cmd; 824 struct mmc_data data; 825 826 /* Switch the frequency */ 827 cmd.cmdidx = SD_CMD_SWITCH_FUNC; 828 cmd.resp_type = MMC_RSP_R1; 829 cmd.cmdarg = (mode << 31) | 0xffffff; 830 cmd.cmdarg &= ~(0xf << (group * 4)); 831 cmd.cmdarg |= value << (group * 4); 832 833 data.dest = (char *)resp; 834 data.blocksize = 64; 835 data.blocks = 1; 836 data.flags = MMC_DATA_READ; 837 838 return mmc_send_cmd(mmc, &cmd, &data); 839 } 840 841 842 static int sd_change_freq(struct mmc *mmc) 843 { 844 int err; 845 struct mmc_cmd cmd; 846 ALLOC_CACHE_ALIGN_BUFFER(uint, scr, 2); 847 ALLOC_CACHE_ALIGN_BUFFER(uint, switch_status, 16); 848 struct mmc_data data; 849 int timeout; 850 851 mmc->card_caps = 0; 852 853 if (mmc_host_is_spi(mmc)) 854 return 0; 855 856 /* Read the SCR to find out if this card supports higher speeds */ 857 cmd.cmdidx = MMC_CMD_APP_CMD; 858 cmd.resp_type = MMC_RSP_R1; 859 cmd.cmdarg = mmc->rca << 16; 860 861 err = mmc_send_cmd(mmc, &cmd, NULL); 862 863 if (err) 864 return err; 865 866 cmd.cmdidx = SD_CMD_APP_SEND_SCR; 867 cmd.resp_type = MMC_RSP_R1; 868 cmd.cmdarg = 0; 869 870 timeout = 3; 871 872 retry_scr: 873 data.dest = (char *)scr; 874 data.blocksize = 8; 875 data.blocks = 1; 876 data.flags = MMC_DATA_READ; 877 878 err = mmc_send_cmd(mmc, &cmd, &data); 879 880 if (err) { 881 if (timeout--) 882 goto retry_scr; 883 884 return err; 885 } 886 887 mmc->scr[0] = __be32_to_cpu(scr[0]); 888 mmc->scr[1] = __be32_to_cpu(scr[1]); 889 890 switch ((mmc->scr[0] >> 24) & 0xf) { 891 case 0: 892 mmc->version = SD_VERSION_1_0; 893 break; 894 case 1: 895 mmc->version = SD_VERSION_1_10; 896 break; 897 case 2: 898 mmc->version = SD_VERSION_2; 899 if ((mmc->scr[0] >> 15) & 0x1) 900 mmc->version = SD_VERSION_3; 901 break; 902 default: 903 mmc->version = SD_VERSION_1_0; 904 break; 905 } 906 907 if (mmc->scr[0] & SD_DATA_4BIT) 908 mmc->card_caps |= MMC_MODE_4BIT; 909 910 /* Version 1.0 doesn't support switching */ 911 if (mmc->version == SD_VERSION_1_0) 912 return 0; 913 914 timeout = 4; 915 while (timeout--) { 916 err = sd_switch(mmc, SD_SWITCH_CHECK, 0, 1, 917 (u8 *)switch_status); 918 919 if (err) 920 return err; 921 922 /* The high-speed function is busy. Try again */ 923 if (!(__be32_to_cpu(switch_status[7]) & SD_HIGHSPEED_BUSY)) 924 break; 925 } 926 927 /* If high-speed isn't supported, we return */ 928 if (!(__be32_to_cpu(switch_status[3]) & SD_HIGHSPEED_SUPPORTED)) 929 return 0; 930 931 /* 932 * If the host doesn't support SD_HIGHSPEED, do not switch card to 933 * HIGHSPEED mode even if the card support SD_HIGHSPPED. 934 * This can avoid furthur problem when the card runs in different 935 * mode between the host. 936 */ 937 if (!((mmc->cfg->host_caps & MMC_MODE_HS_52MHz) && 938 (mmc->cfg->host_caps & MMC_MODE_HS))) 939 return 0; 940 941 err = sd_switch(mmc, SD_SWITCH_SWITCH, 0, 1, (u8 *)switch_status); 942 943 if (err) 944 return err; 945 946 if ((__be32_to_cpu(switch_status[4]) & 0x0f000000) == 0x01000000) 947 mmc->card_caps |= MMC_MODE_HS; 948 949 return 0; 950 } 951 952 /* frequency bases */ 953 /* divided by 10 to be nice to platforms without floating point */ 954 static const int fbase[] = { 955 10000, 956 100000, 957 1000000, 958 10000000, 959 }; 960 961 /* Multiplier values for TRAN_SPEED. Multiplied by 10 to be nice 962 * to platforms without floating point. 963 */ 964 static const u8 multipliers[] = { 965 0, /* reserved */ 966 10, 967 12, 968 13, 969 15, 970 20, 971 25, 972 30, 973 35, 974 40, 975 45, 976 50, 977 55, 978 60, 979 70, 980 80, 981 }; 982 983 static void mmc_set_ios(struct mmc *mmc) 984 { 985 if (mmc->cfg->ops->set_ios) 986 mmc->cfg->ops->set_ios(mmc); 987 } 988 989 void mmc_set_clock(struct mmc *mmc, uint clock) 990 { 991 if (clock > mmc->cfg->f_max) 992 clock = mmc->cfg->f_max; 993 994 if (clock < mmc->cfg->f_min) 995 clock = mmc->cfg->f_min; 996 997 mmc->clock = clock; 998 999 mmc_set_ios(mmc); 1000 } 1001 1002 static void mmc_set_bus_width(struct mmc *mmc, uint width) 1003 { 1004 mmc->bus_width = width; 1005 1006 mmc_set_ios(mmc); 1007 } 1008 1009 static int mmc_startup(struct mmc *mmc) 1010 { 1011 int err, i; 1012 uint mult, freq; 1013 u64 cmult, csize, capacity; 1014 struct mmc_cmd cmd; 1015 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN); 1016 ALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, MMC_MAX_BLOCK_LEN); 1017 int timeout = 1000; 1018 bool has_parts = false; 1019 bool part_completed; 1020 struct blk_desc *bdesc; 1021 1022 #ifdef CONFIG_MMC_SPI_CRC_ON 1023 if (mmc_host_is_spi(mmc)) { /* enable CRC check for spi */ 1024 cmd.cmdidx = MMC_CMD_SPI_CRC_ON_OFF; 1025 cmd.resp_type = MMC_RSP_R1; 1026 cmd.cmdarg = 1; 1027 err = mmc_send_cmd(mmc, &cmd, NULL); 1028 1029 if (err) 1030 return err; 1031 } 1032 #endif 1033 1034 /* Put the Card in Identify Mode */ 1035 cmd.cmdidx = mmc_host_is_spi(mmc) ? MMC_CMD_SEND_CID : 1036 MMC_CMD_ALL_SEND_CID; /* cmd not supported in spi */ 1037 cmd.resp_type = MMC_RSP_R2; 1038 cmd.cmdarg = 0; 1039 1040 err = mmc_send_cmd(mmc, &cmd, NULL); 1041 1042 if (err) 1043 return err; 1044 1045 memcpy(mmc->cid, cmd.response, 16); 1046 1047 /* 1048 * For MMC cards, set the Relative Address. 1049 * For SD cards, get the Relatvie Address. 1050 * This also puts the cards into Standby State 1051 */ 1052 if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */ 1053 cmd.cmdidx = SD_CMD_SEND_RELATIVE_ADDR; 1054 cmd.cmdarg = mmc->rca << 16; 1055 cmd.resp_type = MMC_RSP_R6; 1056 1057 err = mmc_send_cmd(mmc, &cmd, NULL); 1058 1059 if (err) 1060 return err; 1061 1062 if (IS_SD(mmc)) 1063 mmc->rca = (cmd.response[0] >> 16) & 0xffff; 1064 } 1065 1066 /* Get the Card-Specific Data */ 1067 cmd.cmdidx = MMC_CMD_SEND_CSD; 1068 cmd.resp_type = MMC_RSP_R2; 1069 cmd.cmdarg = mmc->rca << 16; 1070 1071 err = mmc_send_cmd(mmc, &cmd, NULL); 1072 1073 /* Waiting for the ready status */ 1074 mmc_send_status(mmc, timeout); 1075 1076 if (err) 1077 return err; 1078 1079 mmc->csd[0] = cmd.response[0]; 1080 mmc->csd[1] = cmd.response[1]; 1081 mmc->csd[2] = cmd.response[2]; 1082 mmc->csd[3] = cmd.response[3]; 1083 1084 if (mmc->version == MMC_VERSION_UNKNOWN) { 1085 int version = (cmd.response[0] >> 26) & 0xf; 1086 1087 switch (version) { 1088 case 0: 1089 mmc->version = MMC_VERSION_1_2; 1090 break; 1091 case 1: 1092 mmc->version = MMC_VERSION_1_4; 1093 break; 1094 case 2: 1095 mmc->version = MMC_VERSION_2_2; 1096 break; 1097 case 3: 1098 mmc->version = MMC_VERSION_3; 1099 break; 1100 case 4: 1101 mmc->version = MMC_VERSION_4; 1102 break; 1103 default: 1104 mmc->version = MMC_VERSION_1_2; 1105 break; 1106 } 1107 } 1108 1109 /* divide frequency by 10, since the mults are 10x bigger */ 1110 freq = fbase[(cmd.response[0] & 0x7)]; 1111 mult = multipliers[((cmd.response[0] >> 3) & 0xf)]; 1112 1113 mmc->tran_speed = freq * mult; 1114 1115 mmc->dsr_imp = ((cmd.response[1] >> 12) & 0x1); 1116 mmc->read_bl_len = 1 << ((cmd.response[1] >> 16) & 0xf); 1117 1118 if (IS_SD(mmc)) 1119 mmc->write_bl_len = mmc->read_bl_len; 1120 else 1121 mmc->write_bl_len = 1 << ((cmd.response[3] >> 22) & 0xf); 1122 1123 if (mmc->high_capacity) { 1124 csize = (mmc->csd[1] & 0x3f) << 16 1125 | (mmc->csd[2] & 0xffff0000) >> 16; 1126 cmult = 8; 1127 } else { 1128 csize = (mmc->csd[1] & 0x3ff) << 2 1129 | (mmc->csd[2] & 0xc0000000) >> 30; 1130 cmult = (mmc->csd[2] & 0x00038000) >> 15; 1131 } 1132 1133 mmc->capacity_user = (csize + 1) << (cmult + 2); 1134 mmc->capacity_user *= mmc->read_bl_len; 1135 mmc->capacity_boot = 0; 1136 mmc->capacity_rpmb = 0; 1137 for (i = 0; i < 4; i++) 1138 mmc->capacity_gp[i] = 0; 1139 1140 if (mmc->read_bl_len > MMC_MAX_BLOCK_LEN) 1141 mmc->read_bl_len = MMC_MAX_BLOCK_LEN; 1142 1143 if (mmc->write_bl_len > MMC_MAX_BLOCK_LEN) 1144 mmc->write_bl_len = MMC_MAX_BLOCK_LEN; 1145 1146 if ((mmc->dsr_imp) && (0xffffffff != mmc->dsr)) { 1147 cmd.cmdidx = MMC_CMD_SET_DSR; 1148 cmd.cmdarg = (mmc->dsr & 0xffff) << 16; 1149 cmd.resp_type = MMC_RSP_NONE; 1150 if (mmc_send_cmd(mmc, &cmd, NULL)) 1151 printf("MMC: SET_DSR failed\n"); 1152 } 1153 1154 /* Select the card, and put it into Transfer Mode */ 1155 if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */ 1156 cmd.cmdidx = MMC_CMD_SELECT_CARD; 1157 cmd.resp_type = MMC_RSP_R1; 1158 cmd.cmdarg = mmc->rca << 16; 1159 err = mmc_send_cmd(mmc, &cmd, NULL); 1160 1161 if (err) 1162 return err; 1163 } 1164 1165 /* 1166 * For SD, its erase group is always one sector 1167 */ 1168 mmc->erase_grp_size = 1; 1169 mmc->part_config = MMCPART_NOAVAILABLE; 1170 if (!IS_SD(mmc) && (mmc->version >= MMC_VERSION_4)) { 1171 /* check ext_csd version and capacity */ 1172 err = mmc_send_ext_csd(mmc, ext_csd); 1173 if (err) 1174 return err; 1175 if (ext_csd[EXT_CSD_REV] >= 2) { 1176 /* 1177 * According to the JEDEC Standard, the value of 1178 * ext_csd's capacity is valid if the value is more 1179 * than 2GB 1180 */ 1181 capacity = ext_csd[EXT_CSD_SEC_CNT] << 0 1182 | ext_csd[EXT_CSD_SEC_CNT + 1] << 8 1183 | ext_csd[EXT_CSD_SEC_CNT + 2] << 16 1184 | ext_csd[EXT_CSD_SEC_CNT + 3] << 24; 1185 capacity *= MMC_MAX_BLOCK_LEN; 1186 if ((capacity >> 20) > 2 * 1024) 1187 mmc->capacity_user = capacity; 1188 } 1189 1190 switch (ext_csd[EXT_CSD_REV]) { 1191 case 1: 1192 mmc->version = MMC_VERSION_4_1; 1193 break; 1194 case 2: 1195 mmc->version = MMC_VERSION_4_2; 1196 break; 1197 case 3: 1198 mmc->version = MMC_VERSION_4_3; 1199 break; 1200 case 5: 1201 mmc->version = MMC_VERSION_4_41; 1202 break; 1203 case 6: 1204 mmc->version = MMC_VERSION_4_5; 1205 break; 1206 case 7: 1207 mmc->version = MMC_VERSION_5_0; 1208 break; 1209 case 8: 1210 mmc->version = MMC_VERSION_5_1; 1211 break; 1212 } 1213 1214 /* The partition data may be non-zero but it is only 1215 * effective if PARTITION_SETTING_COMPLETED is set in 1216 * EXT_CSD, so ignore any data if this bit is not set, 1217 * except for enabling the high-capacity group size 1218 * definition (see below). */ 1219 part_completed = !!(ext_csd[EXT_CSD_PARTITION_SETTING] & 1220 EXT_CSD_PARTITION_SETTING_COMPLETED); 1221 1222 /* store the partition info of emmc */ 1223 mmc->part_support = ext_csd[EXT_CSD_PARTITIONING_SUPPORT]; 1224 if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) || 1225 ext_csd[EXT_CSD_BOOT_MULT]) 1226 mmc->part_config = ext_csd[EXT_CSD_PART_CONF]; 1227 if (part_completed && 1228 (ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & ENHNCD_SUPPORT)) 1229 mmc->part_attr = ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE]; 1230 1231 mmc->capacity_boot = ext_csd[EXT_CSD_BOOT_MULT] << 17; 1232 1233 mmc->capacity_rpmb = ext_csd[EXT_CSD_RPMB_MULT] << 17; 1234 1235 for (i = 0; i < 4; i++) { 1236 int idx = EXT_CSD_GP_SIZE_MULT + i * 3; 1237 uint mult = (ext_csd[idx + 2] << 16) + 1238 (ext_csd[idx + 1] << 8) + ext_csd[idx]; 1239 if (mult) 1240 has_parts = true; 1241 if (!part_completed) 1242 continue; 1243 mmc->capacity_gp[i] = mult; 1244 mmc->capacity_gp[i] *= 1245 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]; 1246 mmc->capacity_gp[i] *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE]; 1247 mmc->capacity_gp[i] <<= 19; 1248 } 1249 1250 if (part_completed) { 1251 mmc->enh_user_size = 1252 (ext_csd[EXT_CSD_ENH_SIZE_MULT+2] << 16) + 1253 (ext_csd[EXT_CSD_ENH_SIZE_MULT+1] << 8) + 1254 ext_csd[EXT_CSD_ENH_SIZE_MULT]; 1255 mmc->enh_user_size *= ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]; 1256 mmc->enh_user_size *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE]; 1257 mmc->enh_user_size <<= 19; 1258 mmc->enh_user_start = 1259 (ext_csd[EXT_CSD_ENH_START_ADDR+3] << 24) + 1260 (ext_csd[EXT_CSD_ENH_START_ADDR+2] << 16) + 1261 (ext_csd[EXT_CSD_ENH_START_ADDR+1] << 8) + 1262 ext_csd[EXT_CSD_ENH_START_ADDR]; 1263 if (mmc->high_capacity) 1264 mmc->enh_user_start <<= 9; 1265 } 1266 1267 /* 1268 * Host needs to enable ERASE_GRP_DEF bit if device is 1269 * partitioned. This bit will be lost every time after a reset 1270 * or power off. This will affect erase size. 1271 */ 1272 if (part_completed) 1273 has_parts = true; 1274 if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) && 1275 (ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE] & PART_ENH_ATTRIB)) 1276 has_parts = true; 1277 if (has_parts) { 1278 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, 1279 EXT_CSD_ERASE_GROUP_DEF, 1); 1280 1281 if (err) 1282 return err; 1283 else 1284 ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1; 1285 } 1286 1287 if (ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01) { 1288 /* Read out group size from ext_csd */ 1289 mmc->erase_grp_size = 1290 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024; 1291 /* 1292 * if high capacity and partition setting completed 1293 * SEC_COUNT is valid even if it is smaller than 2 GiB 1294 * JEDEC Standard JESD84-B45, 6.2.4 1295 */ 1296 if (mmc->high_capacity && part_completed) { 1297 capacity = (ext_csd[EXT_CSD_SEC_CNT]) | 1298 (ext_csd[EXT_CSD_SEC_CNT + 1] << 8) | 1299 (ext_csd[EXT_CSD_SEC_CNT + 2] << 16) | 1300 (ext_csd[EXT_CSD_SEC_CNT + 3] << 24); 1301 capacity *= MMC_MAX_BLOCK_LEN; 1302 mmc->capacity_user = capacity; 1303 } 1304 } else { 1305 /* Calculate the group size from the csd value. */ 1306 int erase_gsz, erase_gmul; 1307 erase_gsz = (mmc->csd[2] & 0x00007c00) >> 10; 1308 erase_gmul = (mmc->csd[2] & 0x000003e0) >> 5; 1309 mmc->erase_grp_size = (erase_gsz + 1) 1310 * (erase_gmul + 1); 1311 } 1312 1313 mmc->hc_wp_grp_size = 1024 1314 * ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] 1315 * ext_csd[EXT_CSD_HC_WP_GRP_SIZE]; 1316 1317 mmc->wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET]; 1318 } 1319 1320 err = mmc_set_capacity(mmc, mmc_get_blk_desc(mmc)->hwpart); 1321 if (err) 1322 return err; 1323 1324 if (IS_SD(mmc)) 1325 err = sd_change_freq(mmc); 1326 else 1327 err = mmc_change_freq(mmc); 1328 1329 if (err) 1330 return err; 1331 1332 /* Restrict card's capabilities by what the host can do */ 1333 mmc->card_caps &= mmc->cfg->host_caps; 1334 1335 if (IS_SD(mmc)) { 1336 if (mmc->card_caps & MMC_MODE_4BIT) { 1337 cmd.cmdidx = MMC_CMD_APP_CMD; 1338 cmd.resp_type = MMC_RSP_R1; 1339 cmd.cmdarg = mmc->rca << 16; 1340 1341 err = mmc_send_cmd(mmc, &cmd, NULL); 1342 if (err) 1343 return err; 1344 1345 cmd.cmdidx = SD_CMD_APP_SET_BUS_WIDTH; 1346 cmd.resp_type = MMC_RSP_R1; 1347 cmd.cmdarg = 2; 1348 err = mmc_send_cmd(mmc, &cmd, NULL); 1349 if (err) 1350 return err; 1351 1352 mmc_set_bus_width(mmc, 4); 1353 } 1354 1355 if (mmc->card_caps & MMC_MODE_HS) 1356 mmc->tran_speed = 50000000; 1357 else 1358 mmc->tran_speed = 25000000; 1359 } else if (mmc->version >= MMC_VERSION_4) { 1360 /* Only version 4 of MMC supports wider bus widths */ 1361 int idx; 1362 1363 /* An array of possible bus widths in order of preference */ 1364 static unsigned ext_csd_bits[] = { 1365 EXT_CSD_DDR_BUS_WIDTH_8, 1366 EXT_CSD_DDR_BUS_WIDTH_4, 1367 EXT_CSD_BUS_WIDTH_8, 1368 EXT_CSD_BUS_WIDTH_4, 1369 EXT_CSD_BUS_WIDTH_1, 1370 }; 1371 1372 /* An array to map CSD bus widths to host cap bits */ 1373 static unsigned ext_to_hostcaps[] = { 1374 [EXT_CSD_DDR_BUS_WIDTH_4] = 1375 MMC_MODE_DDR_52MHz | MMC_MODE_4BIT, 1376 [EXT_CSD_DDR_BUS_WIDTH_8] = 1377 MMC_MODE_DDR_52MHz | MMC_MODE_8BIT, 1378 [EXT_CSD_BUS_WIDTH_4] = MMC_MODE_4BIT, 1379 [EXT_CSD_BUS_WIDTH_8] = MMC_MODE_8BIT, 1380 }; 1381 1382 /* An array to map chosen bus width to an integer */ 1383 static unsigned widths[] = { 1384 8, 4, 8, 4, 1, 1385 }; 1386 1387 for (idx=0; idx < ARRAY_SIZE(ext_csd_bits); idx++) { 1388 unsigned int extw = ext_csd_bits[idx]; 1389 unsigned int caps = ext_to_hostcaps[extw]; 1390 1391 /* 1392 * If the bus width is still not changed, 1393 * don't try to set the default again. 1394 * Otherwise, recover from switch attempts 1395 * by switching to 1-bit bus width. 1396 */ 1397 if (extw == EXT_CSD_BUS_WIDTH_1 && 1398 mmc->bus_width == 1) { 1399 err = 0; 1400 break; 1401 } 1402 1403 /* 1404 * Check to make sure the card and controller support 1405 * these capabilities 1406 */ 1407 if ((mmc->card_caps & caps) != caps) 1408 continue; 1409 1410 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, 1411 EXT_CSD_BUS_WIDTH, extw); 1412 1413 if (err) 1414 continue; 1415 1416 mmc->ddr_mode = (caps & MMC_MODE_DDR_52MHz) ? 1 : 0; 1417 mmc_set_bus_width(mmc, widths[idx]); 1418 1419 err = mmc_send_ext_csd(mmc, test_csd); 1420 1421 if (err) 1422 continue; 1423 1424 /* Only compare read only fields */ 1425 if (ext_csd[EXT_CSD_PARTITIONING_SUPPORT] 1426 == test_csd[EXT_CSD_PARTITIONING_SUPPORT] && 1427 ext_csd[EXT_CSD_HC_WP_GRP_SIZE] 1428 == test_csd[EXT_CSD_HC_WP_GRP_SIZE] && 1429 ext_csd[EXT_CSD_REV] 1430 == test_csd[EXT_CSD_REV] && 1431 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] 1432 == test_csd[EXT_CSD_HC_ERASE_GRP_SIZE] && 1433 memcmp(&ext_csd[EXT_CSD_SEC_CNT], 1434 &test_csd[EXT_CSD_SEC_CNT], 4) == 0) 1435 break; 1436 else 1437 err = SWITCH_ERR; 1438 } 1439 1440 if (err) 1441 return err; 1442 1443 if (mmc->card_caps & MMC_MODE_HS) { 1444 if (mmc->card_caps & MMC_MODE_HS_52MHz) 1445 mmc->tran_speed = 52000000; 1446 else 1447 mmc->tran_speed = 26000000; 1448 } 1449 } 1450 1451 mmc_set_clock(mmc, mmc->tran_speed); 1452 1453 /* Fix the block length for DDR mode */ 1454 if (mmc->ddr_mode) { 1455 mmc->read_bl_len = MMC_MAX_BLOCK_LEN; 1456 mmc->write_bl_len = MMC_MAX_BLOCK_LEN; 1457 } 1458 1459 /* fill in device description */ 1460 bdesc = mmc_get_blk_desc(mmc); 1461 bdesc->lun = 0; 1462 bdesc->hwpart = 0; 1463 bdesc->type = 0; 1464 bdesc->blksz = mmc->read_bl_len; 1465 bdesc->log2blksz = LOG2(bdesc->blksz); 1466 bdesc->lba = lldiv(mmc->capacity, mmc->read_bl_len); 1467 #if !defined(CONFIG_SPL_BUILD) || \ 1468 (defined(CONFIG_SPL_LIBCOMMON_SUPPORT) && \ 1469 !defined(CONFIG_USE_TINY_PRINTF)) 1470 sprintf(bdesc->vendor, "Man %06x Snr %04x%04x", 1471 mmc->cid[0] >> 24, (mmc->cid[2] & 0xffff), 1472 (mmc->cid[3] >> 16) & 0xffff); 1473 sprintf(bdesc->product, "%c%c%c%c%c%c", mmc->cid[0] & 0xff, 1474 (mmc->cid[1] >> 24), (mmc->cid[1] >> 16) & 0xff, 1475 (mmc->cid[1] >> 8) & 0xff, mmc->cid[1] & 0xff, 1476 (mmc->cid[2] >> 24) & 0xff); 1477 sprintf(bdesc->revision, "%d.%d", (mmc->cid[2] >> 20) & 0xf, 1478 (mmc->cid[2] >> 16) & 0xf); 1479 #else 1480 bdesc->vendor[0] = 0; 1481 bdesc->product[0] = 0; 1482 bdesc->revision[0] = 0; 1483 #endif 1484 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBDISK_SUPPORT) 1485 part_init(bdesc); 1486 #endif 1487 1488 return 0; 1489 } 1490 1491 static int mmc_send_if_cond(struct mmc *mmc) 1492 { 1493 struct mmc_cmd cmd; 1494 int err; 1495 1496 cmd.cmdidx = SD_CMD_SEND_IF_COND; 1497 /* We set the bit if the host supports voltages between 2.7 and 3.6 V */ 1498 cmd.cmdarg = ((mmc->cfg->voltages & 0xff8000) != 0) << 8 | 0xaa; 1499 cmd.resp_type = MMC_RSP_R7; 1500 1501 err = mmc_send_cmd(mmc, &cmd, NULL); 1502 1503 if (err) 1504 return err; 1505 1506 if ((cmd.response[0] & 0xff) != 0xaa) 1507 return UNUSABLE_ERR; 1508 else 1509 mmc->version = SD_VERSION_2; 1510 1511 return 0; 1512 } 1513 1514 #ifndef CONFIG_BLK 1515 struct mmc *mmc_create(const struct mmc_config *cfg, void *priv) 1516 { 1517 struct blk_desc *bdesc; 1518 struct mmc *mmc; 1519 1520 /* quick validation */ 1521 if (cfg == NULL || cfg->ops == NULL || cfg->ops->send_cmd == NULL || 1522 cfg->f_min == 0 || cfg->f_max == 0 || cfg->b_max == 0) 1523 return NULL; 1524 1525 mmc = calloc(1, sizeof(*mmc)); 1526 if (mmc == NULL) 1527 return NULL; 1528 1529 mmc->cfg = cfg; 1530 mmc->priv = priv; 1531 1532 /* the following chunk was mmc_register() */ 1533 1534 /* Setup dsr related values */ 1535 mmc->dsr_imp = 0; 1536 mmc->dsr = 0xffffffff; 1537 /* Setup the universal parts of the block interface just once */ 1538 bdesc = mmc_get_blk_desc(mmc); 1539 bdesc->if_type = IF_TYPE_MMC; 1540 bdesc->removable = 1; 1541 bdesc->devnum = mmc_get_next_devnum(); 1542 bdesc->block_read = mmc_bread; 1543 bdesc->block_write = mmc_bwrite; 1544 bdesc->block_erase = mmc_berase; 1545 1546 /* setup initial part type */ 1547 bdesc->part_type = mmc->cfg->part_type; 1548 mmc_list_add(mmc); 1549 1550 return mmc; 1551 } 1552 1553 void mmc_destroy(struct mmc *mmc) 1554 { 1555 /* only freeing memory for now */ 1556 free(mmc); 1557 } 1558 1559 static int mmc_get_dev(int dev, struct blk_desc **descp) 1560 { 1561 struct mmc *mmc = find_mmc_device(dev); 1562 int ret; 1563 1564 if (!mmc) 1565 return -ENODEV; 1566 ret = mmc_init(mmc); 1567 if (ret) 1568 return ret; 1569 1570 *descp = &mmc->block_dev; 1571 1572 return 0; 1573 } 1574 #endif 1575 1576 /* board-specific MMC power initializations. */ 1577 __weak void board_mmc_power_init(void) 1578 { 1579 } 1580 1581 int mmc_start_init(struct mmc *mmc) 1582 { 1583 int err; 1584 1585 /* we pretend there's no card when init is NULL */ 1586 if (mmc_getcd(mmc) == 0 || mmc->cfg->ops->init == NULL) { 1587 mmc->has_init = 0; 1588 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) 1589 printf("MMC: no card present\n"); 1590 #endif 1591 return NO_CARD_ERR; 1592 } 1593 1594 if (mmc->has_init) 1595 return 0; 1596 1597 #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT 1598 mmc_adapter_card_type_ident(); 1599 #endif 1600 board_mmc_power_init(); 1601 1602 /* made sure it's not NULL earlier */ 1603 err = mmc->cfg->ops->init(mmc); 1604 1605 if (err) 1606 return err; 1607 1608 mmc->ddr_mode = 0; 1609 mmc_set_bus_width(mmc, 1); 1610 mmc_set_clock(mmc, 1); 1611 1612 /* Reset the Card */ 1613 err = mmc_go_idle(mmc); 1614 1615 if (err) 1616 return err; 1617 1618 /* The internal partition reset to user partition(0) at every CMD0*/ 1619 mmc_get_blk_desc(mmc)->hwpart = 0; 1620 1621 /* Test for SD version 2 */ 1622 err = mmc_send_if_cond(mmc); 1623 1624 /* Now try to get the SD card's operating condition */ 1625 err = sd_send_op_cond(mmc); 1626 1627 /* If the command timed out, we check for an MMC card */ 1628 if (err == TIMEOUT) { 1629 err = mmc_send_op_cond(mmc); 1630 1631 if (err) { 1632 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) 1633 printf("Card did not respond to voltage select!\n"); 1634 #endif 1635 return UNUSABLE_ERR; 1636 } 1637 } 1638 1639 if (!err) 1640 mmc->init_in_progress = 1; 1641 1642 return err; 1643 } 1644 1645 static int mmc_complete_init(struct mmc *mmc) 1646 { 1647 int err = 0; 1648 1649 mmc->init_in_progress = 0; 1650 if (mmc->op_cond_pending) 1651 err = mmc_complete_op_cond(mmc); 1652 1653 if (!err) 1654 err = mmc_startup(mmc); 1655 if (err) 1656 mmc->has_init = 0; 1657 else 1658 mmc->has_init = 1; 1659 return err; 1660 } 1661 1662 int mmc_init(struct mmc *mmc) 1663 { 1664 int err = 0; 1665 unsigned start; 1666 #ifdef CONFIG_DM_MMC 1667 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(mmc->dev); 1668 1669 upriv->mmc = mmc; 1670 #endif 1671 if (mmc->has_init) 1672 return 0; 1673 1674 start = get_timer(0); 1675 1676 if (!mmc->init_in_progress) 1677 err = mmc_start_init(mmc); 1678 1679 if (!err) 1680 err = mmc_complete_init(mmc); 1681 debug("%s: %d, time %lu\n", __func__, err, get_timer(start)); 1682 return err; 1683 } 1684 1685 int mmc_set_dsr(struct mmc *mmc, u16 val) 1686 { 1687 mmc->dsr = val; 1688 return 0; 1689 } 1690 1691 /* CPU-specific MMC initializations */ 1692 __weak int cpu_mmc_init(bd_t *bis) 1693 { 1694 return -1; 1695 } 1696 1697 /* board-specific MMC initializations. */ 1698 __weak int board_mmc_init(bd_t *bis) 1699 { 1700 return -1; 1701 } 1702 1703 void mmc_set_preinit(struct mmc *mmc, int preinit) 1704 { 1705 mmc->preinit = preinit; 1706 } 1707 1708 #if defined(CONFIG_DM_MMC) && defined(CONFIG_SPL_BUILD) 1709 static int mmc_probe(bd_t *bis) 1710 { 1711 return 0; 1712 } 1713 #elif defined(CONFIG_DM_MMC) 1714 static int mmc_probe(bd_t *bis) 1715 { 1716 int ret, i; 1717 struct uclass *uc; 1718 struct udevice *dev; 1719 1720 ret = uclass_get(UCLASS_MMC, &uc); 1721 if (ret) 1722 return ret; 1723 1724 /* 1725 * Try to add them in sequence order. Really with driver model we 1726 * should allow holes, but the current MMC list does not allow that. 1727 * So if we request 0, 1, 3 we will get 0, 1, 2. 1728 */ 1729 for (i = 0; ; i++) { 1730 ret = uclass_get_device_by_seq(UCLASS_MMC, i, &dev); 1731 if (ret == -ENODEV) 1732 break; 1733 } 1734 uclass_foreach_dev(dev, uc) { 1735 ret = device_probe(dev); 1736 if (ret) 1737 printf("%s - probe failed: %d\n", dev->name, ret); 1738 } 1739 1740 return 0; 1741 } 1742 #else 1743 static int mmc_probe(bd_t *bis) 1744 { 1745 if (board_mmc_init(bis) < 0) 1746 cpu_mmc_init(bis); 1747 1748 return 0; 1749 } 1750 #endif 1751 1752 int mmc_initialize(bd_t *bis) 1753 { 1754 static int initialized = 0; 1755 int ret; 1756 if (initialized) /* Avoid initializing mmc multiple times */ 1757 return 0; 1758 initialized = 1; 1759 1760 #ifndef CONFIG_BLK 1761 mmc_list_init(); 1762 #endif 1763 ret = mmc_probe(bis); 1764 if (ret) 1765 return ret; 1766 1767 #ifndef CONFIG_SPL_BUILD 1768 print_mmc_devices(','); 1769 #endif 1770 1771 mmc_do_preinit(); 1772 return 0; 1773 } 1774 1775 #ifdef CONFIG_SUPPORT_EMMC_BOOT 1776 /* 1777 * This function changes the size of boot partition and the size of rpmb 1778 * partition present on EMMC devices. 1779 * 1780 * Input Parameters: 1781 * struct *mmc: pointer for the mmc device strcuture 1782 * bootsize: size of boot partition 1783 * rpmbsize: size of rpmb partition 1784 * 1785 * Returns 0 on success. 1786 */ 1787 1788 int mmc_boot_partition_size_change(struct mmc *mmc, unsigned long bootsize, 1789 unsigned long rpmbsize) 1790 { 1791 int err; 1792 struct mmc_cmd cmd; 1793 1794 /* Only use this command for raw EMMC moviNAND. Enter backdoor mode */ 1795 cmd.cmdidx = MMC_CMD_RES_MAN; 1796 cmd.resp_type = MMC_RSP_R1b; 1797 cmd.cmdarg = MMC_CMD62_ARG1; 1798 1799 err = mmc_send_cmd(mmc, &cmd, NULL); 1800 if (err) { 1801 debug("mmc_boot_partition_size_change: Error1 = %d\n", err); 1802 return err; 1803 } 1804 1805 /* Boot partition changing mode */ 1806 cmd.cmdidx = MMC_CMD_RES_MAN; 1807 cmd.resp_type = MMC_RSP_R1b; 1808 cmd.cmdarg = MMC_CMD62_ARG2; 1809 1810 err = mmc_send_cmd(mmc, &cmd, NULL); 1811 if (err) { 1812 debug("mmc_boot_partition_size_change: Error2 = %d\n", err); 1813 return err; 1814 } 1815 /* boot partition size is multiple of 128KB */ 1816 bootsize = (bootsize * 1024) / 128; 1817 1818 /* Arg: boot partition size */ 1819 cmd.cmdidx = MMC_CMD_RES_MAN; 1820 cmd.resp_type = MMC_RSP_R1b; 1821 cmd.cmdarg = bootsize; 1822 1823 err = mmc_send_cmd(mmc, &cmd, NULL); 1824 if (err) { 1825 debug("mmc_boot_partition_size_change: Error3 = %d\n", err); 1826 return err; 1827 } 1828 /* RPMB partition size is multiple of 128KB */ 1829 rpmbsize = (rpmbsize * 1024) / 128; 1830 /* Arg: RPMB partition size */ 1831 cmd.cmdidx = MMC_CMD_RES_MAN; 1832 cmd.resp_type = MMC_RSP_R1b; 1833 cmd.cmdarg = rpmbsize; 1834 1835 err = mmc_send_cmd(mmc, &cmd, NULL); 1836 if (err) { 1837 debug("mmc_boot_partition_size_change: Error4 = %d\n", err); 1838 return err; 1839 } 1840 return 0; 1841 } 1842 1843 /* 1844 * Modify EXT_CSD[177] which is BOOT_BUS_WIDTH 1845 * based on the passed in values for BOOT_BUS_WIDTH, RESET_BOOT_BUS_WIDTH 1846 * and BOOT_MODE. 1847 * 1848 * Returns 0 on success. 1849 */ 1850 int mmc_set_boot_bus_width(struct mmc *mmc, u8 width, u8 reset, u8 mode) 1851 { 1852 int err; 1853 1854 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BOOT_BUS_WIDTH, 1855 EXT_CSD_BOOT_BUS_WIDTH_MODE(mode) | 1856 EXT_CSD_BOOT_BUS_WIDTH_RESET(reset) | 1857 EXT_CSD_BOOT_BUS_WIDTH_WIDTH(width)); 1858 1859 if (err) 1860 return err; 1861 return 0; 1862 } 1863 1864 /* 1865 * Modify EXT_CSD[179] which is PARTITION_CONFIG (formerly BOOT_CONFIG) 1866 * based on the passed in values for BOOT_ACK, BOOT_PARTITION_ENABLE and 1867 * PARTITION_ACCESS. 1868 * 1869 * Returns 0 on success. 1870 */ 1871 int mmc_set_part_conf(struct mmc *mmc, u8 ack, u8 part_num, u8 access) 1872 { 1873 int err; 1874 1875 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_PART_CONF, 1876 EXT_CSD_BOOT_ACK(ack) | 1877 EXT_CSD_BOOT_PART_NUM(part_num) | 1878 EXT_CSD_PARTITION_ACCESS(access)); 1879 1880 if (err) 1881 return err; 1882 return 0; 1883 } 1884 1885 /* 1886 * Modify EXT_CSD[162] which is RST_n_FUNCTION based on the given value 1887 * for enable. Note that this is a write-once field for non-zero values. 1888 * 1889 * Returns 0 on success. 1890 */ 1891 int mmc_set_rst_n_function(struct mmc *mmc, u8 enable) 1892 { 1893 return mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_RST_N_FUNCTION, 1894 enable); 1895 } 1896 #endif 1897 1898 #ifndef CONFIG_BLK 1899 U_BOOT_LEGACY_BLK(mmc) = { 1900 .if_typename = "mmc", 1901 .if_type = IF_TYPE_MMC, 1902 .max_devs = -1, 1903 .get_dev = mmc_get_dev, 1904 .select_hwpart = mmc_select_hwpartp, 1905 }; 1906 #endif 1907