1 /* 2 * Copyright 2008, Freescale Semiconductor, Inc 3 * Andy Fleming 4 * 5 * Based vaguely on the Linux code 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #include <config.h> 11 #include <common.h> 12 #include <command.h> 13 #include <dm.h> 14 #include <dm/device-internal.h> 15 #include <errno.h> 16 #include <mmc.h> 17 #include <part.h> 18 #include <power/regulator.h> 19 #include <malloc.h> 20 #include <memalign.h> 21 #include <linux/list.h> 22 #include <div64.h> 23 #include "mmc_private.h" 24 25 static const unsigned int sd_au_size[] = { 26 0, SZ_16K / 512, SZ_32K / 512, 27 SZ_64K / 512, SZ_128K / 512, SZ_256K / 512, 28 SZ_512K / 512, SZ_1M / 512, SZ_2M / 512, 29 SZ_4M / 512, SZ_8M / 512, (SZ_8M + SZ_4M) / 512, 30 SZ_16M / 512, (SZ_16M + SZ_8M) / 512, SZ_32M / 512, SZ_64M / 512, 31 }; 32 33 static char mmc_ext_csd[512]; 34 35 #if CONFIG_IS_ENABLED(MMC_TINY) 36 static struct mmc mmc_static; 37 struct mmc *find_mmc_device(int dev_num) 38 { 39 return &mmc_static; 40 } 41 42 void mmc_do_preinit(void) 43 { 44 struct mmc *m = &mmc_static; 45 #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT 46 mmc_set_preinit(m, 1); 47 #endif 48 if (m->preinit) 49 mmc_start_init(m); 50 } 51 52 struct blk_desc *mmc_get_blk_desc(struct mmc *mmc) 53 { 54 return &mmc->block_dev; 55 } 56 #endif 57 58 #if !CONFIG_IS_ENABLED(DM_MMC) 59 __weak int board_mmc_getwp(struct mmc *mmc) 60 { 61 return -1; 62 } 63 64 int mmc_getwp(struct mmc *mmc) 65 { 66 int wp; 67 68 wp = board_mmc_getwp(mmc); 69 70 if (wp < 0) { 71 if (mmc->cfg->ops->getwp) 72 wp = mmc->cfg->ops->getwp(mmc); 73 else 74 wp = 0; 75 } 76 77 return wp; 78 } 79 80 __weak int board_mmc_getcd(struct mmc *mmc) 81 { 82 return -1; 83 } 84 #endif 85 86 #ifdef CONFIG_MMC_TRACE 87 void mmmc_trace_before_send(struct mmc *mmc, struct mmc_cmd *cmd) 88 { 89 printf("CMD_SEND:%d\n", cmd->cmdidx); 90 printf("\t\tARG\t\t\t 0x%08X\n", cmd->cmdarg); 91 } 92 93 void mmmc_trace_after_send(struct mmc *mmc, struct mmc_cmd *cmd, int ret) 94 { 95 int i; 96 u8 *ptr; 97 98 if (ret) { 99 printf("\t\tRET\t\t\t %d\n", ret); 100 } else { 101 switch (cmd->resp_type) { 102 case MMC_RSP_NONE: 103 printf("\t\tMMC_RSP_NONE\n"); 104 break; 105 case MMC_RSP_R1: 106 printf("\t\tMMC_RSP_R1,5,6,7 \t 0x%08X \n", 107 cmd->response[0]); 108 break; 109 case MMC_RSP_R1b: 110 printf("\t\tMMC_RSP_R1b\t\t 0x%08X \n", 111 cmd->response[0]); 112 break; 113 case MMC_RSP_R2: 114 printf("\t\tMMC_RSP_R2\t\t 0x%08X \n", 115 cmd->response[0]); 116 printf("\t\t \t\t 0x%08X \n", 117 cmd->response[1]); 118 printf("\t\t \t\t 0x%08X \n", 119 cmd->response[2]); 120 printf("\t\t \t\t 0x%08X \n", 121 cmd->response[3]); 122 printf("\n"); 123 printf("\t\t\t\t\tDUMPING DATA\n"); 124 for (i = 0; i < 4; i++) { 125 int j; 126 printf("\t\t\t\t\t%03d - ", i*4); 127 ptr = (u8 *)&cmd->response[i]; 128 ptr += 3; 129 for (j = 0; j < 4; j++) 130 printf("%02X ", *ptr--); 131 printf("\n"); 132 } 133 break; 134 case MMC_RSP_R3: 135 printf("\t\tMMC_RSP_R3,4\t\t 0x%08X \n", 136 cmd->response[0]); 137 break; 138 default: 139 printf("\t\tERROR MMC rsp not supported\n"); 140 break; 141 } 142 } 143 } 144 145 void mmc_trace_state(struct mmc *mmc, struct mmc_cmd *cmd) 146 { 147 int status; 148 149 status = (cmd->response[0] & MMC_STATUS_CURR_STATE) >> 9; 150 printf("CURR STATE:%d\n", status); 151 } 152 #endif 153 154 #if !CONFIG_IS_ENABLED(DM_MMC) 155 int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) 156 { 157 int ret; 158 159 mmmc_trace_before_send(mmc, cmd); 160 ret = mmc->cfg->ops->send_cmd(mmc, cmd, data); 161 mmmc_trace_after_send(mmc, cmd, ret); 162 163 return ret; 164 } 165 #endif 166 167 int mmc_send_status(struct mmc *mmc, int timeout) 168 { 169 struct mmc_cmd cmd; 170 int err, retries = 5; 171 172 cmd.cmdidx = MMC_CMD_SEND_STATUS; 173 cmd.resp_type = MMC_RSP_R1; 174 if (!mmc_host_is_spi(mmc)) 175 cmd.cmdarg = mmc->rca << 16; 176 177 while (1) { 178 err = mmc_send_cmd(mmc, &cmd, NULL); 179 if (!err) { 180 if ((cmd.response[0] & MMC_STATUS_RDY_FOR_DATA) && 181 (cmd.response[0] & MMC_STATUS_CURR_STATE) != 182 MMC_STATE_PRG) 183 break; 184 else if (cmd.response[0] & MMC_STATUS_MASK) { 185 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) 186 printf("Status Error: 0x%08X\n", 187 cmd.response[0]); 188 #endif 189 return -ECOMM; 190 } 191 } else if (--retries < 0) 192 return err; 193 194 if (timeout-- <= 0) 195 break; 196 197 udelay(1000); 198 } 199 200 mmc_trace_state(mmc, &cmd); 201 if (timeout <= 0) { 202 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) 203 printf("Timeout waiting card ready\n"); 204 #endif 205 return -ETIMEDOUT; 206 } 207 208 return 0; 209 } 210 211 int mmc_set_blocklen(struct mmc *mmc, int len) 212 { 213 struct mmc_cmd cmd; 214 215 if (mmc_card_ddr(mmc)) 216 return 0; 217 218 cmd.cmdidx = MMC_CMD_SET_BLOCKLEN; 219 cmd.resp_type = MMC_RSP_R1; 220 cmd.cmdarg = len; 221 222 return mmc_send_cmd(mmc, &cmd, NULL); 223 } 224 225 static int mmc_read_blocks(struct mmc *mmc, void *dst, lbaint_t start, 226 lbaint_t blkcnt) 227 { 228 struct mmc_cmd cmd; 229 struct mmc_data data; 230 231 if (blkcnt > 1) 232 cmd.cmdidx = MMC_CMD_READ_MULTIPLE_BLOCK; 233 else 234 cmd.cmdidx = MMC_CMD_READ_SINGLE_BLOCK; 235 236 if (mmc->high_capacity) 237 cmd.cmdarg = start; 238 else 239 cmd.cmdarg = start * mmc->read_bl_len; 240 241 cmd.resp_type = MMC_RSP_R1; 242 243 data.dest = dst; 244 data.blocks = blkcnt; 245 data.blocksize = mmc->read_bl_len; 246 data.flags = MMC_DATA_READ; 247 248 if (mmc_send_cmd(mmc, &cmd, &data)) 249 return 0; 250 251 if (blkcnt > 1) { 252 cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION; 253 cmd.cmdarg = 0; 254 cmd.resp_type = MMC_RSP_R1b; 255 if (mmc_send_cmd(mmc, &cmd, NULL)) { 256 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) 257 printf("mmc fail to send stop cmd\n"); 258 #endif 259 return 0; 260 } 261 } 262 263 return blkcnt; 264 } 265 266 #if CONFIG_IS_ENABLED(BLK) 267 ulong mmc_bread(struct udevice *dev, lbaint_t start, lbaint_t blkcnt, void *dst) 268 #else 269 ulong mmc_bread(struct blk_desc *block_dev, lbaint_t start, lbaint_t blkcnt, 270 void *dst) 271 #endif 272 { 273 #if CONFIG_IS_ENABLED(BLK) 274 struct blk_desc *block_dev = dev_get_uclass_platdata(dev); 275 #endif 276 int dev_num = block_dev->devnum; 277 int err; 278 lbaint_t cur, blocks_todo = blkcnt; 279 280 if (blkcnt == 0) 281 return 0; 282 283 struct mmc *mmc = find_mmc_device(dev_num); 284 if (!mmc) 285 return 0; 286 287 if (CONFIG_IS_ENABLED(MMC_TINY)) 288 err = mmc_switch_part(mmc, block_dev->hwpart); 289 else 290 err = blk_dselect_hwpart(block_dev, block_dev->hwpart); 291 292 if (err < 0) 293 return 0; 294 295 if ((start + blkcnt) > block_dev->lba) { 296 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) 297 printf("MMC: block number 0x" LBAF " exceeds max(0x" LBAF ")\n", 298 start + blkcnt, block_dev->lba); 299 #endif 300 return 0; 301 } 302 303 if (mmc_set_blocklen(mmc, mmc->read_bl_len)) { 304 debug("%s: Failed to set blocklen\n", __func__); 305 return 0; 306 } 307 308 do { 309 cur = (blocks_todo > mmc->cfg->b_max) ? 310 mmc->cfg->b_max : blocks_todo; 311 if (mmc_read_blocks(mmc, dst, start, cur) != cur) { 312 debug("%s: Failed to read blocks\n", __func__); 313 int timeout = 0; 314 re_init_retry: 315 timeout++; 316 /* 317 * Try re-init seven times. 318 */ 319 if (timeout > 7) { 320 printf("Re-init retry timeout\n"); 321 return 0; 322 } 323 324 mmc->has_init = 0; 325 if (mmc_init(mmc)) 326 return 0; 327 328 if (mmc_read_blocks(mmc, dst, start, cur) != cur) { 329 printf("%s: Re-init mmc_read_blocks error\n", 330 __func__); 331 goto re_init_retry; 332 } 333 } 334 blocks_todo -= cur; 335 start += cur; 336 dst += cur * mmc->read_bl_len; 337 } while (blocks_todo > 0); 338 339 return blkcnt; 340 } 341 342 void mmc_set_clock(struct mmc *mmc, uint clock) 343 { 344 if (clock > mmc->cfg->f_max) 345 clock = mmc->cfg->f_max; 346 347 if (clock < mmc->cfg->f_min) 348 clock = mmc->cfg->f_min; 349 350 mmc->clock = clock; 351 352 mmc_set_ios(mmc); 353 } 354 355 static void mmc_set_bus_width(struct mmc *mmc, uint width) 356 { 357 mmc->bus_width = width; 358 359 mmc_set_ios(mmc); 360 } 361 362 static void mmc_set_timing(struct mmc *mmc, uint timing) 363 { 364 mmc->timing = timing; 365 mmc_set_ios(mmc); 366 } 367 368 static int mmc_go_idle(struct mmc *mmc) 369 { 370 struct mmc_cmd cmd; 371 int err; 372 373 udelay(1000); 374 375 cmd.cmdidx = MMC_CMD_GO_IDLE_STATE; 376 cmd.cmdarg = 0; 377 cmd.resp_type = MMC_RSP_NONE; 378 379 err = mmc_send_cmd(mmc, &cmd, NULL); 380 381 if (err) 382 return err; 383 384 udelay(2000); 385 386 return 0; 387 } 388 389 #ifndef CONFIG_MMC_USE_PRE_CONFIG 390 static int sd_send_op_cond(struct mmc *mmc) 391 { 392 int timeout = 1000; 393 int err; 394 struct mmc_cmd cmd; 395 396 while (1) { 397 cmd.cmdidx = MMC_CMD_APP_CMD; 398 cmd.resp_type = MMC_RSP_R1; 399 cmd.cmdarg = 0; 400 401 err = mmc_send_cmd(mmc, &cmd, NULL); 402 403 if (err) 404 return err; 405 406 cmd.cmdidx = SD_CMD_APP_SEND_OP_COND; 407 cmd.resp_type = MMC_RSP_R3; 408 409 /* 410 * Most cards do not answer if some reserved bits 411 * in the ocr are set. However, Some controller 412 * can set bit 7 (reserved for low voltages), but 413 * how to manage low voltages SD card is not yet 414 * specified. 415 */ 416 cmd.cmdarg = mmc_host_is_spi(mmc) ? 0 : 417 (mmc->cfg->voltages & 0xff8000); 418 419 if (mmc->version == SD_VERSION_2) 420 cmd.cmdarg |= OCR_HCS; 421 422 err = mmc_send_cmd(mmc, &cmd, NULL); 423 424 if (err) 425 return err; 426 427 if (cmd.response[0] & OCR_BUSY) 428 break; 429 430 if (timeout-- <= 0) 431 return -EOPNOTSUPP; 432 433 udelay(1000); 434 } 435 436 if (mmc->version != SD_VERSION_2) 437 mmc->version = SD_VERSION_1_0; 438 439 if (mmc_host_is_spi(mmc)) { /* read OCR for spi */ 440 cmd.cmdidx = MMC_CMD_SPI_READ_OCR; 441 cmd.resp_type = MMC_RSP_R3; 442 cmd.cmdarg = 0; 443 444 err = mmc_send_cmd(mmc, &cmd, NULL); 445 446 if (err) 447 return err; 448 } 449 450 mmc->ocr = cmd.response[0]; 451 452 mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS); 453 mmc->rca = 0; 454 455 return 0; 456 } 457 #endif 458 459 static int mmc_send_op_cond_iter(struct mmc *mmc, int use_arg) 460 { 461 struct mmc_cmd cmd; 462 int err; 463 464 cmd.cmdidx = MMC_CMD_SEND_OP_COND; 465 cmd.resp_type = MMC_RSP_R3; 466 cmd.cmdarg = 0; 467 if (use_arg && !mmc_host_is_spi(mmc)) 468 cmd.cmdarg = OCR_HCS | 469 (mmc->cfg->voltages & 470 (mmc->ocr & OCR_VOLTAGE_MASK)) | 471 (mmc->ocr & OCR_ACCESS_MODE); 472 473 err = mmc_send_cmd(mmc, &cmd, NULL); 474 if (err) 475 return err; 476 mmc->ocr = cmd.response[0]; 477 return 0; 478 } 479 480 #ifndef CONFIG_MMC_USE_PRE_CONFIG 481 static int mmc_send_op_cond(struct mmc *mmc) 482 { 483 int err, i; 484 485 /* Some cards seem to need this */ 486 mmc_go_idle(mmc); 487 488 /* Asking to the card its capabilities */ 489 for (i = 0; i < 2; i++) { 490 err = mmc_send_op_cond_iter(mmc, i != 0); 491 if (err) 492 return err; 493 494 /* exit if not busy (flag seems to be inverted) */ 495 if (mmc->ocr & OCR_BUSY) 496 break; 497 } 498 mmc->op_cond_pending = 1; 499 return 0; 500 } 501 #endif 502 static int mmc_complete_op_cond(struct mmc *mmc) 503 { 504 struct mmc_cmd cmd; 505 int timeout = 1000; 506 uint start; 507 int err; 508 509 mmc->op_cond_pending = 0; 510 if (!(mmc->ocr & OCR_BUSY)) { 511 /* Some cards seem to need this */ 512 mmc_go_idle(mmc); 513 514 start = get_timer(0); 515 while (1) { 516 err = mmc_send_op_cond_iter(mmc, 1); 517 if (err) 518 return err; 519 if (mmc->ocr & OCR_BUSY) 520 break; 521 if (get_timer(start) > timeout) 522 return -EOPNOTSUPP; 523 udelay(100); 524 } 525 } 526 527 if (mmc_host_is_spi(mmc)) { /* read OCR for spi */ 528 cmd.cmdidx = MMC_CMD_SPI_READ_OCR; 529 cmd.resp_type = MMC_RSP_R3; 530 cmd.cmdarg = 0; 531 532 err = mmc_send_cmd(mmc, &cmd, NULL); 533 534 if (err) 535 return err; 536 537 mmc->ocr = cmd.response[0]; 538 } 539 540 mmc->version = MMC_VERSION_UNKNOWN; 541 542 mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS); 543 mmc->rca = 1; 544 545 return 0; 546 } 547 548 549 static int mmc_send_ext_csd(struct mmc *mmc, u8 *ext_csd) 550 { 551 static int initialized; 552 struct mmc_cmd cmd; 553 struct mmc_data data; 554 int err; 555 556 if (initialized) { 557 memcpy(ext_csd, mmc_ext_csd, 512); 558 return 0; 559 } 560 561 initialized = 1; 562 563 /* Get the Card Status Register */ 564 cmd.cmdidx = MMC_CMD_SEND_EXT_CSD; 565 cmd.resp_type = MMC_RSP_R1; 566 cmd.cmdarg = 0; 567 568 data.dest = (char *)ext_csd; 569 data.blocks = 1; 570 data.blocksize = MMC_MAX_BLOCK_LEN; 571 data.flags = MMC_DATA_READ; 572 573 err = mmc_send_cmd(mmc, &cmd, &data); 574 memcpy(mmc_ext_csd, ext_csd, 512); 575 576 return err; 577 } 578 579 static int mmc_poll_for_busy(struct mmc *mmc, u8 send_status) 580 { 581 struct mmc_cmd cmd; 582 u8 busy = true; 583 uint start; 584 int ret; 585 int timeout = 1000; 586 587 cmd.cmdidx = MMC_CMD_SEND_STATUS; 588 cmd.resp_type = MMC_RSP_R1; 589 cmd.cmdarg = mmc->rca << 16; 590 591 start = get_timer(0); 592 593 if (!send_status && !mmc_can_card_busy(mmc)) { 594 mdelay(timeout); 595 return 0; 596 } 597 598 do { 599 if (!send_status) { 600 busy = mmc_card_busy(mmc); 601 } else { 602 ret = mmc_send_cmd(mmc, &cmd, NULL); 603 604 if (ret) 605 return ret; 606 607 if (cmd.response[0] & MMC_STATUS_SWITCH_ERROR) 608 return -EBADMSG; 609 busy = (cmd.response[0] & MMC_STATUS_CURR_STATE) == 610 MMC_STATE_PRG; 611 } 612 613 if (get_timer(start) > timeout && busy) 614 return -ETIMEDOUT; 615 } while (busy); 616 617 return 0; 618 } 619 620 static int __mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value, 621 u8 send_status) 622 { 623 struct mmc_cmd cmd; 624 int retries = 3; 625 int ret; 626 627 cmd.cmdidx = MMC_CMD_SWITCH; 628 cmd.resp_type = MMC_RSP_R1b; 629 cmd.cmdarg = (MMC_SWITCH_MODE_WRITE_BYTE << 24) | 630 (index << 16) | 631 (value << 8); 632 633 do { 634 ret = mmc_send_cmd(mmc, &cmd, NULL); 635 636 if (!ret) 637 return mmc_poll_for_busy(mmc, send_status); 638 } while (--retries > 0 && ret); 639 640 return ret; 641 } 642 643 int mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value) 644 { 645 return __mmc_switch(mmc, set, index, value, true); 646 } 647 648 static int mmc_select_bus_width(struct mmc *mmc) 649 { 650 u32 ext_csd_bits[] = { 651 EXT_CSD_BUS_WIDTH_8, 652 EXT_CSD_BUS_WIDTH_4, 653 }; 654 u32 bus_widths[] = { 655 MMC_BUS_WIDTH_8BIT, 656 MMC_BUS_WIDTH_4BIT, 657 }; 658 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN); 659 ALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, MMC_MAX_BLOCK_LEN); 660 u32 idx, bus_width = 0; 661 int err = 0; 662 663 if (mmc->version < MMC_VERSION_4 || 664 !(mmc->cfg->host_caps & (MMC_MODE_4BIT | MMC_MODE_8BIT))) 665 return 0; 666 667 err = mmc_send_ext_csd(mmc, ext_csd); 668 669 if (err) 670 return err; 671 672 idx = (mmc->cfg->host_caps & MMC_MODE_8BIT) ? 0 : 1; 673 674 /* 675 * Unlike SD, MMC cards dont have a configuration register to notify 676 * supported bus width. So bus test command should be run to identify 677 * the supported bus width or compare the ext csd values of current 678 * bus width and ext csd values of 1 bit mode read earlier. 679 */ 680 for (; idx < ARRAY_SIZE(bus_widths); idx++) { 681 /* 682 * Host is capable of 8bit transfer, then switch 683 * the device to work in 8bit transfer mode. If the 684 * mmc switch command returns error then switch to 685 * 4bit transfer mode. On success set the corresponding 686 * bus width on the host. 687 */ 688 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, 689 EXT_CSD_BUS_WIDTH, ext_csd_bits[idx]); 690 if (err) 691 continue; 692 693 bus_width = bus_widths[idx]; 694 mmc_set_bus_width(mmc, bus_width); 695 696 err = mmc_send_ext_csd(mmc, test_csd); 697 698 if (err) 699 continue; 700 701 /* Only compare read only fields */ 702 if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] == 703 test_csd[EXT_CSD_PARTITIONING_SUPPORT]) && 704 (ext_csd[EXT_CSD_HC_WP_GRP_SIZE] == 705 test_csd[EXT_CSD_HC_WP_GRP_SIZE]) && 706 (ext_csd[EXT_CSD_REV] == test_csd[EXT_CSD_REV]) && 707 (ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] == 708 test_csd[EXT_CSD_HC_ERASE_GRP_SIZE]) && 709 !memcmp(&ext_csd[EXT_CSD_SEC_CNT], 710 &test_csd[EXT_CSD_SEC_CNT], 4)) { 711 err = bus_width; 712 break; 713 } else { 714 err = -EBADMSG; 715 } 716 } 717 718 return err; 719 } 720 721 static const u8 tuning_blk_pattern_4bit[] = { 722 0xff, 0x0f, 0xff, 0x00, 0xff, 0xcc, 0xc3, 0xcc, 723 0xc3, 0x3c, 0xcc, 0xff, 0xfe, 0xff, 0xfe, 0xef, 724 0xff, 0xdf, 0xff, 0xdd, 0xff, 0xfb, 0xff, 0xfb, 725 0xbf, 0xff, 0x7f, 0xff, 0x77, 0xf7, 0xbd, 0xef, 726 0xff, 0xf0, 0xff, 0xf0, 0x0f, 0xfc, 0xcc, 0x3c, 727 0xcc, 0x33, 0xcc, 0xcf, 0xff, 0xef, 0xff, 0xee, 728 0xff, 0xfd, 0xff, 0xfd, 0xdf, 0xff, 0xbf, 0xff, 729 0xbb, 0xff, 0xf7, 0xff, 0xf7, 0x7f, 0x7b, 0xde, 730 }; 731 732 static const u8 tuning_blk_pattern_8bit[] = { 733 0xff, 0xff, 0x00, 0xff, 0xff, 0xff, 0x00, 0x00, 734 0xff, 0xff, 0xcc, 0xcc, 0xcc, 0x33, 0xcc, 0xcc, 735 0xcc, 0x33, 0x33, 0xcc, 0xcc, 0xcc, 0xff, 0xff, 736 0xff, 0xee, 0xff, 0xff, 0xff, 0xee, 0xee, 0xff, 737 0xff, 0xff, 0xdd, 0xff, 0xff, 0xff, 0xdd, 0xdd, 738 0xff, 0xff, 0xff, 0xbb, 0xff, 0xff, 0xff, 0xbb, 739 0xbb, 0xff, 0xff, 0xff, 0x77, 0xff, 0xff, 0xff, 740 0x77, 0x77, 0xff, 0x77, 0xbb, 0xdd, 0xee, 0xff, 741 0xff, 0xff, 0xff, 0x00, 0xff, 0xff, 0xff, 0x00, 742 0x00, 0xff, 0xff, 0xcc, 0xcc, 0xcc, 0x33, 0xcc, 743 0xcc, 0xcc, 0x33, 0x33, 0xcc, 0xcc, 0xcc, 0xff, 744 0xff, 0xff, 0xee, 0xff, 0xff, 0xff, 0xee, 0xee, 745 0xff, 0xff, 0xff, 0xdd, 0xff, 0xff, 0xff, 0xdd, 746 0xdd, 0xff, 0xff, 0xff, 0xbb, 0xff, 0xff, 0xff, 747 0xbb, 0xbb, 0xff, 0xff, 0xff, 0x77, 0xff, 0xff, 748 0xff, 0x77, 0x77, 0xff, 0x77, 0xbb, 0xdd, 0xee, 749 }; 750 751 int mmc_send_tuning(struct mmc *mmc, u32 opcode) 752 { 753 struct mmc_cmd cmd; 754 struct mmc_data data; 755 const u8 *tuning_block_pattern; 756 int size, err = 0; 757 u8 *data_buf; 758 759 if (mmc->bus_width == MMC_BUS_WIDTH_8BIT) { 760 tuning_block_pattern = tuning_blk_pattern_8bit; 761 size = sizeof(tuning_blk_pattern_8bit); 762 } else if (mmc->bus_width == MMC_BUS_WIDTH_4BIT) { 763 tuning_block_pattern = tuning_blk_pattern_4bit; 764 size = sizeof(tuning_blk_pattern_4bit); 765 } else { 766 return -EINVAL; 767 } 768 769 data_buf = calloc(1, size); 770 if (!data_buf) 771 return -ENOMEM; 772 773 cmd.cmdidx = opcode; 774 cmd.resp_type = MMC_RSP_R1; 775 cmd.cmdarg = 0; 776 777 data.dest = (char *)data_buf; 778 data.blocksize = size; 779 data.blocks = 1; 780 data.flags = MMC_DATA_READ; 781 782 err = mmc_send_cmd(mmc, &cmd, &data); 783 if (err) 784 goto out; 785 786 if (memcmp(data_buf, tuning_block_pattern, size)) 787 err = -EIO; 788 out: 789 free(data_buf); 790 return err; 791 } 792 793 static int mmc_execute_tuning(struct mmc *mmc) 794 { 795 #ifdef CONFIG_DM_MMC 796 struct dm_mmc_ops *ops = mmc_get_ops(mmc->dev); 797 #endif 798 u32 opcode; 799 800 if (IS_SD(mmc)) 801 opcode = MMC_SEND_TUNING_BLOCK; 802 else 803 opcode = MMC_SEND_TUNING_BLOCK_HS200; 804 805 #ifndef CONFIG_DM_MMC 806 if (mmc->cfg->ops->execute_tuning) { 807 return mmc->cfg->ops->execute_tuning(mmc, opcode); 808 #else 809 if (ops->execute_tuning) { 810 return ops->execute_tuning(mmc->dev, opcode); 811 #endif 812 } else { 813 debug("Tuning feature required for HS200 mode.\n"); 814 return -EIO; 815 } 816 } 817 818 static int mmc_hs200_tuning(struct mmc *mmc) 819 { 820 return mmc_execute_tuning(mmc); 821 } 822 823 static int mmc_select_hs(struct mmc *mmc) 824 { 825 int ret; 826 827 ret = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, 828 EXT_CSD_HS_TIMING, EXT_CSD_TIMING_HS); 829 830 if (!ret) 831 mmc_set_timing(mmc, MMC_TIMING_MMC_HS); 832 833 return ret; 834 } 835 836 static int mmc_select_hs_ddr(struct mmc *mmc) 837 { 838 u32 ext_csd_bits; 839 int err = 0; 840 841 if (mmc->bus_width == MMC_BUS_WIDTH_1BIT) 842 return 0; 843 844 ext_csd_bits = (mmc->bus_width == MMC_BUS_WIDTH_8BIT) ? 845 EXT_CSD_DDR_BUS_WIDTH_8 : EXT_CSD_DDR_BUS_WIDTH_4; 846 847 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, 848 EXT_CSD_BUS_WIDTH, ext_csd_bits); 849 if (err) 850 return err; 851 852 mmc_set_timing(mmc, MMC_TIMING_MMC_DDR52); 853 854 return 0; 855 } 856 857 static int mmc_select_hs200(struct mmc *mmc) 858 { 859 int ret; 860 861 /* 862 * Set the bus width(4 or 8) with host's support and 863 * switch to HS200 mode if bus width is set successfully. 864 */ 865 ret = mmc_select_bus_width(mmc); 866 867 if (ret > 0) { 868 ret = __mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, 869 EXT_CSD_HS_TIMING, 870 EXT_CSD_TIMING_HS200, false); 871 872 if (ret) 873 return ret; 874 875 mmc_set_timing(mmc, MMC_TIMING_MMC_HS200); 876 } 877 878 return ret; 879 } 880 881 static int mmc_select_hs400(struct mmc *mmc) 882 { 883 int ret; 884 885 /* Switch card to HS mode */ 886 ret = __mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, 887 EXT_CSD_HS_TIMING, EXT_CSD_TIMING_HS, false); 888 if (ret) 889 return ret; 890 891 /* Set host controller to HS timing */ 892 mmc_set_timing(mmc, MMC_TIMING_MMC_HS); 893 894 /* Reduce frequency to HS frequency */ 895 mmc_set_clock(mmc, MMC_HIGH_52_MAX_DTR); 896 897 ret = mmc_send_status(mmc, 1000); 898 if (ret) 899 return ret; 900 901 /* Switch card to DDR */ 902 ret = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, 903 EXT_CSD_BUS_WIDTH, 904 EXT_CSD_DDR_BUS_WIDTH_8); 905 if (ret) 906 return ret; 907 908 /* Switch card to HS400 */ 909 ret = __mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, 910 EXT_CSD_HS_TIMING, EXT_CSD_TIMING_HS400, false); 911 if (ret) 912 return ret; 913 914 /* Set host controller to HS400 timing and frequency */ 915 mmc_set_timing(mmc, MMC_TIMING_MMC_HS400); 916 917 return ret; 918 } 919 920 static u32 mmc_select_card_type(struct mmc *mmc, u8 *ext_csd) 921 { 922 u8 card_type; 923 u32 host_caps, avail_type = 0; 924 925 card_type = ext_csd[EXT_CSD_CARD_TYPE]; 926 host_caps = mmc->cfg->host_caps; 927 928 if ((host_caps & MMC_MODE_HS) && 929 (card_type & EXT_CSD_CARD_TYPE_26)) 930 avail_type |= EXT_CSD_CARD_TYPE_26; 931 932 if ((host_caps & MMC_MODE_HS) && 933 (card_type & EXT_CSD_CARD_TYPE_52)) 934 avail_type |= EXT_CSD_CARD_TYPE_52; 935 936 /* 937 * For the moment, u-boot doesn't support signal voltage 938 * switch, therefor we assume that host support ddr52 939 * at 1.8v or 3.3v I/O(1.2v I/O not supported, hs200 and 940 * hs400 are the same). 941 */ 942 if ((host_caps & MMC_MODE_DDR_52MHz) && 943 (card_type & EXT_CSD_CARD_TYPE_DDR_1_8V)) 944 avail_type |= EXT_CSD_CARD_TYPE_DDR_1_8V; 945 946 if ((host_caps & MMC_MODE_HS200) && 947 (card_type & EXT_CSD_CARD_TYPE_HS200_1_8V)) 948 avail_type |= EXT_CSD_CARD_TYPE_HS200_1_8V; 949 950 /* 951 * If host can support HS400, it means that host can also 952 * support HS200. 953 */ 954 if ((host_caps & MMC_MODE_HS400) && 955 (host_caps & MMC_MODE_8BIT) && 956 (card_type & EXT_CSD_CARD_TYPE_HS400_1_8V)) 957 avail_type |= EXT_CSD_CARD_TYPE_HS200_1_8V | 958 EXT_CSD_CARD_TYPE_HS400_1_8V; 959 960 if ((host_caps & MMC_MODE_HS400ES) && 961 (host_caps & MMC_MODE_8BIT) && 962 ext_csd[EXT_CSD_STROBE_SUPPORT] && 963 (avail_type & EXT_CSD_CARD_TYPE_HS400_1_8V)) 964 avail_type |= EXT_CSD_CARD_TYPE_HS200_1_8V | 965 EXT_CSD_CARD_TYPE_HS400_1_8V | 966 EXT_CSD_CARD_TYPE_HS400ES; 967 968 return avail_type; 969 } 970 971 static void mmc_set_bus_speed(struct mmc *mmc, u8 avail_type) 972 { 973 int clock = 0; 974 975 if (mmc_card_hs(mmc)) 976 clock = (avail_type & EXT_CSD_CARD_TYPE_52) ? 977 MMC_HIGH_52_MAX_DTR : MMC_HIGH_26_MAX_DTR; 978 else if (mmc_card_hs200(mmc) || 979 mmc_card_hs400(mmc) || 980 mmc_card_hs400es(mmc)) 981 clock = MMC_HS200_MAX_DTR; 982 983 mmc_set_clock(mmc, clock); 984 } 985 986 static int mmc_change_freq(struct mmc *mmc) 987 { 988 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN); 989 u32 avail_type; 990 int err; 991 992 mmc->card_caps = 0; 993 994 if (mmc_host_is_spi(mmc)) 995 return 0; 996 997 /* Only version 4 supports high-speed */ 998 if (mmc->version < MMC_VERSION_4) 999 return 0; 1000 1001 mmc->card_caps |= MMC_MODE_4BIT | MMC_MODE_8BIT; 1002 1003 err = mmc_send_ext_csd(mmc, ext_csd); 1004 1005 if (err) 1006 return err; 1007 1008 avail_type = mmc_select_card_type(mmc, ext_csd); 1009 1010 if (avail_type & EXT_CSD_CARD_TYPE_HS200) 1011 err = mmc_select_hs200(mmc); 1012 else if (avail_type & EXT_CSD_CARD_TYPE_HS) 1013 err = mmc_select_hs(mmc); 1014 else 1015 err = -EINVAL; 1016 1017 if (err) 1018 return err; 1019 1020 mmc_set_bus_speed(mmc, avail_type); 1021 1022 if (mmc_card_hs200(mmc)) { 1023 err = mmc_hs200_tuning(mmc); 1024 if (avail_type & EXT_CSD_CARD_TYPE_HS400 && 1025 mmc->bus_width == MMC_BUS_WIDTH_8BIT) { 1026 err = mmc_select_hs400(mmc); 1027 mmc_set_bus_speed(mmc, avail_type); 1028 } 1029 } else if (!mmc_card_hs400es(mmc)) { 1030 err = mmc_select_bus_width(mmc) > 0 ? 0 : err; 1031 if (!err && avail_type & EXT_CSD_CARD_TYPE_DDR_52) 1032 err = mmc_select_hs_ddr(mmc); 1033 } 1034 1035 return err; 1036 } 1037 1038 static int mmc_set_capacity(struct mmc *mmc, int part_num) 1039 { 1040 switch (part_num) { 1041 case 0: 1042 mmc->capacity = mmc->capacity_user; 1043 break; 1044 case 1: 1045 case 2: 1046 mmc->capacity = mmc->capacity_boot; 1047 break; 1048 case 3: 1049 mmc->capacity = mmc->capacity_rpmb; 1050 break; 1051 case 4: 1052 case 5: 1053 case 6: 1054 case 7: 1055 mmc->capacity = mmc->capacity_gp[part_num - 4]; 1056 break; 1057 default: 1058 return -1; 1059 } 1060 1061 mmc_get_blk_desc(mmc)->lba = lldiv(mmc->capacity, mmc->read_bl_len); 1062 1063 return 0; 1064 } 1065 1066 int mmc_switch_part(struct mmc *mmc, unsigned int part_num) 1067 { 1068 int ret; 1069 1070 ret = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_PART_CONF, 1071 (mmc->part_config & ~PART_ACCESS_MASK) 1072 | (part_num & PART_ACCESS_MASK)); 1073 1074 /* 1075 * Set the capacity if the switch succeeded or was intended 1076 * to return to representing the raw device. 1077 */ 1078 if ((ret == 0) || ((ret == -ENODEV) && (part_num == 0))) { 1079 ret = mmc_set_capacity(mmc, part_num); 1080 mmc_get_blk_desc(mmc)->hwpart = part_num; 1081 } 1082 1083 return ret; 1084 } 1085 1086 int mmc_hwpart_config(struct mmc *mmc, 1087 const struct mmc_hwpart_conf *conf, 1088 enum mmc_hwpart_conf_mode mode) 1089 { 1090 u8 part_attrs = 0; 1091 u32 enh_size_mult; 1092 u32 enh_start_addr; 1093 u32 gp_size_mult[4]; 1094 u32 max_enh_size_mult; 1095 u32 tot_enh_size_mult = 0; 1096 u8 wr_rel_set; 1097 int i, pidx, err; 1098 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN); 1099 1100 if (mode < MMC_HWPART_CONF_CHECK || mode > MMC_HWPART_CONF_COMPLETE) 1101 return -EINVAL; 1102 1103 if (IS_SD(mmc) || (mmc->version < MMC_VERSION_4_41)) { 1104 printf("eMMC >= 4.4 required for enhanced user data area\n"); 1105 return -EMEDIUMTYPE; 1106 } 1107 1108 if (!(mmc->part_support & PART_SUPPORT)) { 1109 printf("Card does not support partitioning\n"); 1110 return -EMEDIUMTYPE; 1111 } 1112 1113 if (!mmc->hc_wp_grp_size) { 1114 printf("Card does not define HC WP group size\n"); 1115 return -EMEDIUMTYPE; 1116 } 1117 1118 /* check partition alignment and total enhanced size */ 1119 if (conf->user.enh_size) { 1120 if (conf->user.enh_size % mmc->hc_wp_grp_size || 1121 conf->user.enh_start % mmc->hc_wp_grp_size) { 1122 printf("User data enhanced area not HC WP group " 1123 "size aligned\n"); 1124 return -EINVAL; 1125 } 1126 part_attrs |= EXT_CSD_ENH_USR; 1127 enh_size_mult = conf->user.enh_size / mmc->hc_wp_grp_size; 1128 if (mmc->high_capacity) { 1129 enh_start_addr = conf->user.enh_start; 1130 } else { 1131 enh_start_addr = (conf->user.enh_start << 9); 1132 } 1133 } else { 1134 enh_size_mult = 0; 1135 enh_start_addr = 0; 1136 } 1137 tot_enh_size_mult += enh_size_mult; 1138 1139 for (pidx = 0; pidx < 4; pidx++) { 1140 if (conf->gp_part[pidx].size % mmc->hc_wp_grp_size) { 1141 printf("GP%i partition not HC WP group size " 1142 "aligned\n", pidx+1); 1143 return -EINVAL; 1144 } 1145 gp_size_mult[pidx] = conf->gp_part[pidx].size / mmc->hc_wp_grp_size; 1146 if (conf->gp_part[pidx].size && conf->gp_part[pidx].enhanced) { 1147 part_attrs |= EXT_CSD_ENH_GP(pidx); 1148 tot_enh_size_mult += gp_size_mult[pidx]; 1149 } 1150 } 1151 1152 if (part_attrs && ! (mmc->part_support & ENHNCD_SUPPORT)) { 1153 printf("Card does not support enhanced attribute\n"); 1154 return -EMEDIUMTYPE; 1155 } 1156 1157 err = mmc_send_ext_csd(mmc, ext_csd); 1158 if (err) 1159 return err; 1160 1161 max_enh_size_mult = 1162 (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+2] << 16) + 1163 (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+1] << 8) + 1164 ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT]; 1165 if (tot_enh_size_mult > max_enh_size_mult) { 1166 printf("Total enhanced size exceeds maximum (%u > %u)\n", 1167 tot_enh_size_mult, max_enh_size_mult); 1168 return -EMEDIUMTYPE; 1169 } 1170 1171 /* The default value of EXT_CSD_WR_REL_SET is device 1172 * dependent, the values can only be changed if the 1173 * EXT_CSD_HS_CTRL_REL bit is set. The values can be 1174 * changed only once and before partitioning is completed. */ 1175 wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET]; 1176 if (conf->user.wr_rel_change) { 1177 if (conf->user.wr_rel_set) 1178 wr_rel_set |= EXT_CSD_WR_DATA_REL_USR; 1179 else 1180 wr_rel_set &= ~EXT_CSD_WR_DATA_REL_USR; 1181 } 1182 for (pidx = 0; pidx < 4; pidx++) { 1183 if (conf->gp_part[pidx].wr_rel_change) { 1184 if (conf->gp_part[pidx].wr_rel_set) 1185 wr_rel_set |= EXT_CSD_WR_DATA_REL_GP(pidx); 1186 else 1187 wr_rel_set &= ~EXT_CSD_WR_DATA_REL_GP(pidx); 1188 } 1189 } 1190 1191 if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET] && 1192 !(ext_csd[EXT_CSD_WR_REL_PARAM] & EXT_CSD_HS_CTRL_REL)) { 1193 puts("Card does not support host controlled partition write " 1194 "reliability settings\n"); 1195 return -EMEDIUMTYPE; 1196 } 1197 1198 if (ext_csd[EXT_CSD_PARTITION_SETTING] & 1199 EXT_CSD_PARTITION_SETTING_COMPLETED) { 1200 printf("Card already partitioned\n"); 1201 return -EPERM; 1202 } 1203 1204 if (mode == MMC_HWPART_CONF_CHECK) 1205 return 0; 1206 1207 /* Partitioning requires high-capacity size definitions */ 1208 if (!(ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01)) { 1209 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, 1210 EXT_CSD_ERASE_GROUP_DEF, 1); 1211 1212 if (err) 1213 return err; 1214 1215 ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1; 1216 1217 /* update erase group size to be high-capacity */ 1218 mmc->erase_grp_size = 1219 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024; 1220 1221 } 1222 1223 /* all OK, write the configuration */ 1224 for (i = 0; i < 4; i++) { 1225 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, 1226 EXT_CSD_ENH_START_ADDR+i, 1227 (enh_start_addr >> (i*8)) & 0xFF); 1228 if (err) 1229 return err; 1230 } 1231 for (i = 0; i < 3; i++) { 1232 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, 1233 EXT_CSD_ENH_SIZE_MULT+i, 1234 (enh_size_mult >> (i*8)) & 0xFF); 1235 if (err) 1236 return err; 1237 } 1238 for (pidx = 0; pidx < 4; pidx++) { 1239 for (i = 0; i < 3; i++) { 1240 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, 1241 EXT_CSD_GP_SIZE_MULT+pidx*3+i, 1242 (gp_size_mult[pidx] >> (i*8)) & 0xFF); 1243 if (err) 1244 return err; 1245 } 1246 } 1247 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, 1248 EXT_CSD_PARTITIONS_ATTRIBUTE, part_attrs); 1249 if (err) 1250 return err; 1251 1252 if (mode == MMC_HWPART_CONF_SET) 1253 return 0; 1254 1255 /* The WR_REL_SET is a write-once register but shall be 1256 * written before setting PART_SETTING_COMPLETED. As it is 1257 * write-once we can only write it when completing the 1258 * partitioning. */ 1259 if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET]) { 1260 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, 1261 EXT_CSD_WR_REL_SET, wr_rel_set); 1262 if (err) 1263 return err; 1264 } 1265 1266 /* Setting PART_SETTING_COMPLETED confirms the partition 1267 * configuration but it only becomes effective after power 1268 * cycle, so we do not adjust the partition related settings 1269 * in the mmc struct. */ 1270 1271 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, 1272 EXT_CSD_PARTITION_SETTING, 1273 EXT_CSD_PARTITION_SETTING_COMPLETED); 1274 if (err) 1275 return err; 1276 1277 return 0; 1278 } 1279 1280 #if !CONFIG_IS_ENABLED(DM_MMC) 1281 int mmc_getcd(struct mmc *mmc) 1282 { 1283 int cd; 1284 1285 cd = board_mmc_getcd(mmc); 1286 1287 if (cd < 0) { 1288 if (mmc->cfg->ops->getcd) 1289 cd = mmc->cfg->ops->getcd(mmc); 1290 else 1291 cd = 1; 1292 } 1293 1294 return cd; 1295 } 1296 #endif 1297 1298 static int sd_switch(struct mmc *mmc, int mode, int group, u8 value, u8 *resp) 1299 { 1300 struct mmc_cmd cmd; 1301 struct mmc_data data; 1302 1303 /* Switch the frequency */ 1304 cmd.cmdidx = SD_CMD_SWITCH_FUNC; 1305 cmd.resp_type = MMC_RSP_R1; 1306 cmd.cmdarg = (mode << 31) | 0xffffff; 1307 cmd.cmdarg &= ~(0xf << (group * 4)); 1308 cmd.cmdarg |= value << (group * 4); 1309 1310 data.dest = (char *)resp; 1311 data.blocksize = 64; 1312 data.blocks = 1; 1313 data.flags = MMC_DATA_READ; 1314 1315 return mmc_send_cmd(mmc, &cmd, &data); 1316 } 1317 1318 1319 static int sd_change_freq(struct mmc *mmc) 1320 { 1321 int err; 1322 struct mmc_cmd cmd; 1323 ALLOC_CACHE_ALIGN_BUFFER(uint, scr, 2); 1324 ALLOC_CACHE_ALIGN_BUFFER(uint, switch_status, 16); 1325 struct mmc_data data; 1326 int timeout; 1327 1328 mmc->card_caps = 0; 1329 1330 if (mmc_host_is_spi(mmc)) 1331 return 0; 1332 1333 /* Read the SCR to find out if this card supports higher speeds */ 1334 cmd.cmdidx = MMC_CMD_APP_CMD; 1335 cmd.resp_type = MMC_RSP_R1; 1336 cmd.cmdarg = mmc->rca << 16; 1337 1338 err = mmc_send_cmd(mmc, &cmd, NULL); 1339 1340 if (err) 1341 return err; 1342 1343 cmd.cmdidx = SD_CMD_APP_SEND_SCR; 1344 cmd.resp_type = MMC_RSP_R1; 1345 cmd.cmdarg = 0; 1346 1347 timeout = 3; 1348 1349 retry_scr: 1350 data.dest = (char *)scr; 1351 data.blocksize = 8; 1352 data.blocks = 1; 1353 data.flags = MMC_DATA_READ; 1354 1355 err = mmc_send_cmd(mmc, &cmd, &data); 1356 1357 if (err) { 1358 if (timeout--) 1359 goto retry_scr; 1360 1361 return err; 1362 } 1363 1364 mmc->scr[0] = __be32_to_cpu(scr[0]); 1365 mmc->scr[1] = __be32_to_cpu(scr[1]); 1366 1367 switch ((mmc->scr[0] >> 24) & 0xf) { 1368 case 0: 1369 mmc->version = SD_VERSION_1_0; 1370 break; 1371 case 1: 1372 mmc->version = SD_VERSION_1_10; 1373 break; 1374 case 2: 1375 mmc->version = SD_VERSION_2; 1376 if ((mmc->scr[0] >> 15) & 0x1) 1377 mmc->version = SD_VERSION_3; 1378 break; 1379 default: 1380 mmc->version = SD_VERSION_1_0; 1381 break; 1382 } 1383 1384 if (mmc->scr[0] & SD_DATA_4BIT) 1385 mmc->card_caps |= MMC_MODE_4BIT; 1386 1387 /* Version 1.0 doesn't support switching */ 1388 if (mmc->version == SD_VERSION_1_0) 1389 return 0; 1390 1391 timeout = 4; 1392 while (timeout--) { 1393 err = sd_switch(mmc, SD_SWITCH_CHECK, 0, 1, 1394 (u8 *)switch_status); 1395 1396 if (err) 1397 return err; 1398 1399 /* The high-speed function is busy. Try again */ 1400 if (!(__be32_to_cpu(switch_status[7]) & SD_HIGHSPEED_BUSY)) 1401 break; 1402 } 1403 1404 /* If high-speed isn't supported, we return */ 1405 if (!(__be32_to_cpu(switch_status[3]) & SD_HIGHSPEED_SUPPORTED)) 1406 return 0; 1407 1408 /* 1409 * If the host doesn't support SD_HIGHSPEED, do not switch card to 1410 * HIGHSPEED mode even if the card support SD_HIGHSPPED. 1411 * This can avoid furthur problem when the card runs in different 1412 * mode between the host. 1413 */ 1414 if (!((mmc->cfg->host_caps & MMC_MODE_HS_52MHz) && 1415 (mmc->cfg->host_caps & MMC_MODE_HS))) 1416 return 0; 1417 1418 err = sd_switch(mmc, SD_SWITCH_SWITCH, 0, 1, (u8 *)switch_status); 1419 1420 if (err) 1421 return err; 1422 1423 if ((__be32_to_cpu(switch_status[4]) & 0x0f000000) == 0x01000000) 1424 mmc->card_caps |= MMC_MODE_HS; 1425 1426 return 0; 1427 } 1428 1429 static int sd_read_ssr(struct mmc *mmc) 1430 { 1431 int err, i; 1432 struct mmc_cmd cmd; 1433 ALLOC_CACHE_ALIGN_BUFFER(uint, ssr, 16); 1434 struct mmc_data data; 1435 int timeout = 3; 1436 unsigned int au, eo, et, es; 1437 1438 cmd.cmdidx = MMC_CMD_APP_CMD; 1439 cmd.resp_type = MMC_RSP_R1; 1440 cmd.cmdarg = mmc->rca << 16; 1441 1442 err = mmc_send_cmd(mmc, &cmd, NULL); 1443 if (err) 1444 return err; 1445 1446 cmd.cmdidx = SD_CMD_APP_SD_STATUS; 1447 cmd.resp_type = MMC_RSP_R1; 1448 cmd.cmdarg = 0; 1449 1450 retry_ssr: 1451 data.dest = (char *)ssr; 1452 data.blocksize = 64; 1453 data.blocks = 1; 1454 data.flags = MMC_DATA_READ; 1455 1456 err = mmc_send_cmd(mmc, &cmd, &data); 1457 if (err) { 1458 if (timeout--) 1459 goto retry_ssr; 1460 1461 return err; 1462 } 1463 1464 for (i = 0; i < 16; i++) 1465 ssr[i] = be32_to_cpu(ssr[i]); 1466 1467 au = (ssr[2] >> 12) & 0xF; 1468 if ((au <= 9) || (mmc->version == SD_VERSION_3)) { 1469 mmc->ssr.au = sd_au_size[au]; 1470 es = (ssr[3] >> 24) & 0xFF; 1471 es |= (ssr[2] & 0xFF) << 8; 1472 et = (ssr[3] >> 18) & 0x3F; 1473 if (es && et) { 1474 eo = (ssr[3] >> 16) & 0x3; 1475 mmc->ssr.erase_timeout = (et * 1000) / es; 1476 mmc->ssr.erase_offset = eo * 1000; 1477 } 1478 } else { 1479 debug("Invalid Allocation Unit Size.\n"); 1480 } 1481 1482 return 0; 1483 } 1484 1485 /* frequency bases */ 1486 /* divided by 10 to be nice to platforms without floating point */ 1487 static const int fbase[] = { 1488 10000, 1489 100000, 1490 1000000, 1491 10000000, 1492 }; 1493 1494 /* Multiplier values for TRAN_SPEED. Multiplied by 10 to be nice 1495 * to platforms without floating point. 1496 */ 1497 static const u8 multipliers[] = { 1498 0, /* reserved */ 1499 10, 1500 12, 1501 13, 1502 15, 1503 20, 1504 25, 1505 30, 1506 35, 1507 40, 1508 45, 1509 50, 1510 55, 1511 60, 1512 70, 1513 80, 1514 }; 1515 1516 #if !CONFIG_IS_ENABLED(DM_MMC) 1517 static void mmc_set_ios(struct mmc *mmc) 1518 { 1519 if (mmc->cfg->ops->set_ios) 1520 mmc->cfg->ops->set_ios(mmc); 1521 } 1522 1523 static bool mmc_card_busy(struct mmc *mmc) 1524 { 1525 if (!mmc->cfg->ops->card_busy) 1526 return -ENOSYS; 1527 1528 return mmc->cfg->ops->card_busy(mmc); 1529 } 1530 1531 static bool mmc_can_card_busy(struct mmc *) 1532 { 1533 return !!mmc->cfg->ops->card_busy; 1534 } 1535 #endif 1536 1537 static int mmc_startup(struct mmc *mmc) 1538 { 1539 int err, i; 1540 uint mult, freq, tran_speed; 1541 u64 cmult, csize, capacity; 1542 struct mmc_cmd cmd; 1543 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN); 1544 bool has_parts = false; 1545 bool part_completed; 1546 struct blk_desc *bdesc; 1547 1548 #ifdef CONFIG_MMC_SPI_CRC_ON 1549 if (mmc_host_is_spi(mmc)) { /* enable CRC check for spi */ 1550 cmd.cmdidx = MMC_CMD_SPI_CRC_ON_OFF; 1551 cmd.resp_type = MMC_RSP_R1; 1552 cmd.cmdarg = 1; 1553 err = mmc_send_cmd(mmc, &cmd, NULL); 1554 1555 if (err) 1556 return err; 1557 } 1558 #endif 1559 #ifndef CONFIG_MMC_USE_PRE_CONFIG 1560 /* Put the Card in Identify Mode */ 1561 cmd.cmdidx = mmc_host_is_spi(mmc) ? MMC_CMD_SEND_CID : 1562 MMC_CMD_ALL_SEND_CID; /* cmd not supported in spi */ 1563 cmd.resp_type = MMC_RSP_R2; 1564 cmd.cmdarg = 0; 1565 1566 err = mmc_send_cmd(mmc, &cmd, NULL); 1567 1568 if (err) 1569 return err; 1570 1571 memcpy(mmc->cid, cmd.response, 16); 1572 1573 /* 1574 * For MMC cards, set the Relative Address. 1575 * For SD cards, get the Relatvie Address. 1576 * This also puts the cards into Standby State 1577 */ 1578 if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */ 1579 cmd.cmdidx = SD_CMD_SEND_RELATIVE_ADDR; 1580 cmd.cmdarg = mmc->rca << 16; 1581 cmd.resp_type = MMC_RSP_R6; 1582 1583 err = mmc_send_cmd(mmc, &cmd, NULL); 1584 1585 if (err) 1586 return err; 1587 1588 if (IS_SD(mmc)) 1589 mmc->rca = (cmd.response[0] >> 16) & 0xffff; 1590 } 1591 #endif 1592 /* Get the Card-Specific Data */ 1593 cmd.cmdidx = MMC_CMD_SEND_CSD; 1594 cmd.resp_type = MMC_RSP_R2; 1595 cmd.cmdarg = mmc->rca << 16; 1596 1597 err = mmc_send_cmd(mmc, &cmd, NULL); 1598 1599 if (err) 1600 return err; 1601 1602 mmc->csd[0] = cmd.response[0]; 1603 mmc->csd[1] = cmd.response[1]; 1604 mmc->csd[2] = cmd.response[2]; 1605 mmc->csd[3] = cmd.response[3]; 1606 1607 if (mmc->version == MMC_VERSION_UNKNOWN) { 1608 int version = (cmd.response[0] >> 26) & 0xf; 1609 1610 switch (version) { 1611 case 0: 1612 mmc->version = MMC_VERSION_1_2; 1613 break; 1614 case 1: 1615 mmc->version = MMC_VERSION_1_4; 1616 break; 1617 case 2: 1618 mmc->version = MMC_VERSION_2_2; 1619 break; 1620 case 3: 1621 mmc->version = MMC_VERSION_3; 1622 break; 1623 case 4: 1624 mmc->version = MMC_VERSION_4; 1625 break; 1626 default: 1627 mmc->version = MMC_VERSION_1_2; 1628 break; 1629 } 1630 } 1631 1632 /* divide frequency by 10, since the mults are 10x bigger */ 1633 freq = fbase[(cmd.response[0] & 0x7)]; 1634 mult = multipliers[((cmd.response[0] >> 3) & 0xf)]; 1635 1636 tran_speed = freq * mult; 1637 1638 mmc->dsr_imp = ((cmd.response[1] >> 12) & 0x1); 1639 mmc->read_bl_len = 1 << ((cmd.response[1] >> 16) & 0xf); 1640 1641 if (IS_SD(mmc)) 1642 mmc->write_bl_len = mmc->read_bl_len; 1643 else 1644 mmc->write_bl_len = 1 << ((cmd.response[3] >> 22) & 0xf); 1645 1646 if (mmc->high_capacity) { 1647 csize = (mmc->csd[1] & 0x3f) << 16 1648 | (mmc->csd[2] & 0xffff0000) >> 16; 1649 cmult = 8; 1650 } else { 1651 csize = (mmc->csd[1] & 0x3ff) << 2 1652 | (mmc->csd[2] & 0xc0000000) >> 30; 1653 cmult = (mmc->csd[2] & 0x00038000) >> 15; 1654 } 1655 1656 mmc->capacity_user = (csize + 1) << (cmult + 2); 1657 mmc->capacity_user *= mmc->read_bl_len; 1658 mmc->capacity_boot = 0; 1659 mmc->capacity_rpmb = 0; 1660 for (i = 0; i < 4; i++) 1661 mmc->capacity_gp[i] = 0; 1662 1663 if (mmc->read_bl_len > MMC_MAX_BLOCK_LEN) 1664 mmc->read_bl_len = MMC_MAX_BLOCK_LEN; 1665 1666 if (mmc->write_bl_len > MMC_MAX_BLOCK_LEN) 1667 mmc->write_bl_len = MMC_MAX_BLOCK_LEN; 1668 1669 if ((mmc->dsr_imp) && (0xffffffff != mmc->dsr)) { 1670 cmd.cmdidx = MMC_CMD_SET_DSR; 1671 cmd.cmdarg = (mmc->dsr & 0xffff) << 16; 1672 cmd.resp_type = MMC_RSP_NONE; 1673 if (mmc_send_cmd(mmc, &cmd, NULL)) 1674 printf("MMC: SET_DSR failed\n"); 1675 } 1676 1677 /* Select the card, and put it into Transfer Mode */ 1678 if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */ 1679 cmd.cmdidx = MMC_CMD_SELECT_CARD; 1680 cmd.resp_type = MMC_RSP_R1; 1681 cmd.cmdarg = mmc->rca << 16; 1682 err = mmc_send_cmd(mmc, &cmd, NULL); 1683 1684 if (err) 1685 return err; 1686 } 1687 1688 /* 1689 * For SD, its erase group is always one sector 1690 */ 1691 mmc->erase_grp_size = 1; 1692 mmc->part_config = MMCPART_NOAVAILABLE; 1693 if (!IS_SD(mmc) && (mmc->version >= MMC_VERSION_4)) { 1694 /* check ext_csd version and capacity */ 1695 err = mmc_send_ext_csd(mmc, ext_csd); 1696 if (err) 1697 return err; 1698 if (ext_csd[EXT_CSD_REV] >= 2) { 1699 /* 1700 * According to the JEDEC Standard, the value of 1701 * ext_csd's capacity is valid if the value is more 1702 * than 2GB 1703 */ 1704 capacity = ext_csd[EXT_CSD_SEC_CNT] << 0 1705 | ext_csd[EXT_CSD_SEC_CNT + 1] << 8 1706 | ext_csd[EXT_CSD_SEC_CNT + 2] << 16 1707 | ext_csd[EXT_CSD_SEC_CNT + 3] << 24; 1708 capacity *= MMC_MAX_BLOCK_LEN; 1709 if ((capacity >> 20) > 2 * 1024) 1710 mmc->capacity_user = capacity; 1711 } 1712 1713 switch (ext_csd[EXT_CSD_REV]) { 1714 case 1: 1715 mmc->version = MMC_VERSION_4_1; 1716 break; 1717 case 2: 1718 mmc->version = MMC_VERSION_4_2; 1719 break; 1720 case 3: 1721 mmc->version = MMC_VERSION_4_3; 1722 break; 1723 case 5: 1724 mmc->version = MMC_VERSION_4_41; 1725 break; 1726 case 6: 1727 mmc->version = MMC_VERSION_4_5; 1728 break; 1729 case 7: 1730 mmc->version = MMC_VERSION_5_0; 1731 break; 1732 case 8: 1733 mmc->version = MMC_VERSION_5_1; 1734 break; 1735 } 1736 1737 /* The partition data may be non-zero but it is only 1738 * effective if PARTITION_SETTING_COMPLETED is set in 1739 * EXT_CSD, so ignore any data if this bit is not set, 1740 * except for enabling the high-capacity group size 1741 * definition (see below). */ 1742 part_completed = !!(ext_csd[EXT_CSD_PARTITION_SETTING] & 1743 EXT_CSD_PARTITION_SETTING_COMPLETED); 1744 1745 /* store the partition info of emmc */ 1746 mmc->part_support = ext_csd[EXT_CSD_PARTITIONING_SUPPORT]; 1747 if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) || 1748 ext_csd[EXT_CSD_BOOT_MULT]) 1749 mmc->part_config = ext_csd[EXT_CSD_PART_CONF]; 1750 if (part_completed && 1751 (ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & ENHNCD_SUPPORT)) 1752 mmc->part_attr = ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE]; 1753 if (ext_csd[EXT_CSD_SEC_FEATURE_SUPPORT] & EXT_CSD_SEC_GB_CL_EN) 1754 mmc->esr.mmc_can_trim = 1; 1755 1756 mmc->capacity_boot = ext_csd[EXT_CSD_BOOT_MULT] << 17; 1757 1758 mmc->capacity_rpmb = ext_csd[EXT_CSD_RPMB_MULT] << 17; 1759 1760 for (i = 0; i < 4; i++) { 1761 int idx = EXT_CSD_GP_SIZE_MULT + i * 3; 1762 uint mult = (ext_csd[idx + 2] << 16) + 1763 (ext_csd[idx + 1] << 8) + ext_csd[idx]; 1764 if (mult) 1765 has_parts = true; 1766 if (!part_completed) 1767 continue; 1768 mmc->capacity_gp[i] = mult; 1769 mmc->capacity_gp[i] *= 1770 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]; 1771 mmc->capacity_gp[i] *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE]; 1772 mmc->capacity_gp[i] <<= 19; 1773 } 1774 1775 if (part_completed) { 1776 mmc->enh_user_size = 1777 (ext_csd[EXT_CSD_ENH_SIZE_MULT+2] << 16) + 1778 (ext_csd[EXT_CSD_ENH_SIZE_MULT+1] << 8) + 1779 ext_csd[EXT_CSD_ENH_SIZE_MULT]; 1780 mmc->enh_user_size *= ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]; 1781 mmc->enh_user_size *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE]; 1782 mmc->enh_user_size <<= 19; 1783 mmc->enh_user_start = 1784 (ext_csd[EXT_CSD_ENH_START_ADDR+3] << 24) + 1785 (ext_csd[EXT_CSD_ENH_START_ADDR+2] << 16) + 1786 (ext_csd[EXT_CSD_ENH_START_ADDR+1] << 8) + 1787 ext_csd[EXT_CSD_ENH_START_ADDR]; 1788 if (mmc->high_capacity) 1789 mmc->enh_user_start <<= 9; 1790 } 1791 1792 /* 1793 * Host needs to enable ERASE_GRP_DEF bit if device is 1794 * partitioned. This bit will be lost every time after a reset 1795 * or power off. This will affect erase size. 1796 */ 1797 if (part_completed) 1798 has_parts = true; 1799 if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) && 1800 (ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE] & PART_ENH_ATTRIB)) 1801 has_parts = true; 1802 if (has_parts) { 1803 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, 1804 EXT_CSD_ERASE_GROUP_DEF, 1); 1805 1806 if (err) 1807 return err; 1808 else 1809 ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1; 1810 } 1811 1812 if (ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01) { 1813 /* Read out group size from ext_csd */ 1814 mmc->erase_grp_size = 1815 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024; 1816 /* 1817 * if high capacity and partition setting completed 1818 * SEC_COUNT is valid even if it is smaller than 2 GiB 1819 * JEDEC Standard JESD84-B45, 6.2.4 1820 */ 1821 if (mmc->high_capacity && part_completed) { 1822 capacity = (ext_csd[EXT_CSD_SEC_CNT]) | 1823 (ext_csd[EXT_CSD_SEC_CNT + 1] << 8) | 1824 (ext_csd[EXT_CSD_SEC_CNT + 2] << 16) | 1825 (ext_csd[EXT_CSD_SEC_CNT + 3] << 24); 1826 capacity *= MMC_MAX_BLOCK_LEN; 1827 mmc->capacity_user = capacity; 1828 } 1829 } else { 1830 /* Calculate the group size from the csd value. */ 1831 int erase_gsz, erase_gmul; 1832 erase_gsz = (mmc->csd[2] & 0x00007c00) >> 10; 1833 erase_gmul = (mmc->csd[2] & 0x000003e0) >> 5; 1834 mmc->erase_grp_size = (erase_gsz + 1) 1835 * (erase_gmul + 1); 1836 } 1837 1838 mmc->hc_wp_grp_size = 1024 1839 * ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] 1840 * ext_csd[EXT_CSD_HC_WP_GRP_SIZE]; 1841 1842 mmc->wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET]; 1843 } 1844 1845 err = mmc_set_capacity(mmc, mmc_get_blk_desc(mmc)->hwpart); 1846 if (err) 1847 return err; 1848 1849 if (IS_SD(mmc)) 1850 err = sd_change_freq(mmc); 1851 else 1852 err = mmc_change_freq(mmc); 1853 1854 if (err) 1855 return err; 1856 1857 /* Restrict card's capabilities by what the host can do */ 1858 mmc->card_caps &= mmc->cfg->host_caps; 1859 1860 if (IS_SD(mmc)) { 1861 if (mmc->card_caps & MMC_MODE_4BIT) { 1862 cmd.cmdidx = MMC_CMD_APP_CMD; 1863 cmd.resp_type = MMC_RSP_R1; 1864 cmd.cmdarg = mmc->rca << 16; 1865 1866 err = mmc_send_cmd(mmc, &cmd, NULL); 1867 if (err) 1868 return err; 1869 1870 cmd.cmdidx = SD_CMD_APP_SET_BUS_WIDTH; 1871 cmd.resp_type = MMC_RSP_R1; 1872 cmd.cmdarg = 2; 1873 err = mmc_send_cmd(mmc, &cmd, NULL); 1874 if (err) 1875 return err; 1876 1877 mmc_set_bus_width(mmc, 4); 1878 } 1879 1880 err = sd_read_ssr(mmc); 1881 if (err) 1882 return err; 1883 1884 if (mmc->card_caps & MMC_MODE_HS) 1885 tran_speed = 50000000; 1886 else 1887 tran_speed = 25000000; 1888 1889 mmc_set_clock(mmc, tran_speed); 1890 } 1891 1892 /* Fix the block length for DDR mode */ 1893 if (mmc_card_ddr(mmc)) { 1894 mmc->read_bl_len = MMC_MAX_BLOCK_LEN; 1895 mmc->write_bl_len = MMC_MAX_BLOCK_LEN; 1896 } 1897 1898 /* fill in device description */ 1899 bdesc = mmc_get_blk_desc(mmc); 1900 bdesc->lun = 0; 1901 bdesc->hwpart = 0; 1902 bdesc->type = 0; 1903 bdesc->blksz = mmc->read_bl_len; 1904 bdesc->log2blksz = LOG2(bdesc->blksz); 1905 bdesc->lba = lldiv(mmc->capacity, mmc->read_bl_len); 1906 #if !defined(CONFIG_SPL_BUILD) || \ 1907 (defined(CONFIG_SPL_LIBCOMMON_SUPPORT) && \ 1908 !defined(CONFIG_USE_TINY_PRINTF)) 1909 sprintf(bdesc->vendor, "Man %06x Snr %04x%04x", 1910 mmc->cid[0] >> 24, (mmc->cid[2] & 0xffff), 1911 (mmc->cid[3] >> 16) & 0xffff); 1912 sprintf(bdesc->product, "%c%c%c%c%c%c", mmc->cid[0] & 0xff, 1913 (mmc->cid[1] >> 24), (mmc->cid[1] >> 16) & 0xff, 1914 (mmc->cid[1] >> 8) & 0xff, mmc->cid[1] & 0xff, 1915 (mmc->cid[2] >> 24) & 0xff); 1916 sprintf(bdesc->revision, "%d.%d", (mmc->cid[2] >> 20) & 0xf, 1917 (mmc->cid[2] >> 16) & 0xf); 1918 #else 1919 bdesc->vendor[0] = 0; 1920 bdesc->product[0] = 0; 1921 bdesc->revision[0] = 0; 1922 #endif 1923 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBDISK_SUPPORT) 1924 part_init(bdesc); 1925 #endif 1926 1927 return 0; 1928 } 1929 1930 #ifndef CONFIG_MMC_USE_PRE_CONFIG 1931 static int mmc_send_if_cond(struct mmc *mmc) 1932 { 1933 struct mmc_cmd cmd; 1934 int err; 1935 1936 cmd.cmdidx = SD_CMD_SEND_IF_COND; 1937 /* We set the bit if the host supports voltages between 2.7 and 3.6 V */ 1938 cmd.cmdarg = ((mmc->cfg->voltages & 0xff8000) != 0) << 8 | 0xaa; 1939 cmd.resp_type = MMC_RSP_R7; 1940 1941 err = mmc_send_cmd(mmc, &cmd, NULL); 1942 1943 if (err) 1944 return err; 1945 1946 if ((cmd.response[0] & 0xff) != 0xaa) 1947 return -EOPNOTSUPP; 1948 else 1949 mmc->version = SD_VERSION_2; 1950 1951 return 0; 1952 } 1953 #endif 1954 1955 #if !CONFIG_IS_ENABLED(DM_MMC) 1956 /* board-specific MMC power initializations. */ 1957 __weak void board_mmc_power_init(void) 1958 { 1959 } 1960 #endif 1961 1962 #ifndef CONFIG_MMC_USE_PRE_CONFIG 1963 static int mmc_power_init(struct mmc *mmc) 1964 { 1965 #if CONFIG_IS_ENABLED(DM_MMC) 1966 #if defined(CONFIG_DM_REGULATOR) && !defined(CONFIG_SPL_BUILD) 1967 struct udevice *vmmc_supply; 1968 int ret; 1969 1970 ret = device_get_supply_regulator(mmc->dev, "vmmc-supply", 1971 &vmmc_supply); 1972 if (ret) { 1973 debug("%s: No vmmc supply\n", mmc->dev->name); 1974 return 0; 1975 } 1976 1977 ret = regulator_set_enable(vmmc_supply, true); 1978 if (ret) { 1979 puts("Error enabling VMMC supply\n"); 1980 return ret; 1981 } 1982 #endif 1983 #else /* !CONFIG_DM_MMC */ 1984 /* 1985 * Driver model should use a regulator, as above, rather than calling 1986 * out to board code. 1987 */ 1988 board_mmc_power_init(); 1989 #endif 1990 return 0; 1991 } 1992 #endif 1993 #ifdef CONFIG_MMC_USE_PRE_CONFIG 1994 static int mmc_select_card(struct mmc *mmc, int n) 1995 { 1996 struct mmc_cmd cmd; 1997 int err = 0; 1998 1999 memset(&cmd, 0, sizeof(struct mmc_cmd)); 2000 if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */ 2001 mmc->rca = n; 2002 cmd.cmdidx = MMC_CMD_SELECT_CARD; 2003 cmd.resp_type = MMC_RSP_R1; 2004 cmd.cmdarg = mmc->rca << 16; 2005 err = mmc_send_cmd(mmc, &cmd, NULL); 2006 } 2007 2008 return err; 2009 } 2010 2011 int mmc_start_init(struct mmc *mmc) 2012 { 2013 /* 2014 * We use the MMC config set by the bootrom. 2015 * So it is no need to reset the eMMC device. 2016 */ 2017 mmc_set_bus_width(mmc, 8); 2018 mmc_set_clock(mmc, 1); 2019 mmc_set_timing(mmc, MMC_TIMING_LEGACY); 2020 /* Send cmd7 to return stand-by state*/ 2021 mmc_select_card(mmc, 0); 2022 mmc->version = MMC_VERSION_UNKNOWN; 2023 mmc->high_capacity = 1; 2024 /* 2025 * The RCA is set to 2 by rockchip bootrom, use the default 2026 * value here. 2027 */ 2028 #ifdef CONFIG_ARCH_ROCKCHIP 2029 mmc->rca = 2; 2030 #else 2031 mmc->rca = 1; 2032 #endif 2033 return 0; 2034 } 2035 #else 2036 int mmc_start_init(struct mmc *mmc) 2037 { 2038 bool no_card; 2039 int err; 2040 2041 /* we pretend there's no card when init is NULL */ 2042 no_card = mmc_getcd(mmc) == 0; 2043 #if !CONFIG_IS_ENABLED(DM_MMC) 2044 no_card = no_card || (mmc->cfg->ops->init == NULL); 2045 #endif 2046 if (no_card) { 2047 mmc->has_init = 0; 2048 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) 2049 printf("MMC: no card present\n"); 2050 #endif 2051 return -ENOMEDIUM; 2052 } 2053 2054 if (mmc->has_init) 2055 return 0; 2056 2057 #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT 2058 mmc_adapter_card_type_ident(); 2059 #endif 2060 err = mmc_power_init(mmc); 2061 if (err) 2062 return err; 2063 2064 #if CONFIG_IS_ENABLED(DM_MMC) 2065 /* The device has already been probed ready for use */ 2066 #else 2067 /* made sure it's not NULL earlier */ 2068 err = mmc->cfg->ops->init(mmc); 2069 if (err) 2070 return err; 2071 #endif 2072 mmc_set_bus_width(mmc, 1); 2073 mmc_set_clock(mmc, 1); 2074 mmc_set_timing(mmc, MMC_TIMING_LEGACY); 2075 2076 /* Reset the Card */ 2077 err = mmc_go_idle(mmc); 2078 2079 if (err) 2080 return err; 2081 2082 /* The internal partition reset to user partition(0) at every CMD0*/ 2083 mmc_get_blk_desc(mmc)->hwpart = 0; 2084 2085 /* Test for SD version 2 */ 2086 err = mmc_send_if_cond(mmc); 2087 2088 /* Now try to get the SD card's operating condition */ 2089 err = sd_send_op_cond(mmc); 2090 2091 /* If the command timed out, we check for an MMC card */ 2092 if (err == -ETIMEDOUT) { 2093 err = mmc_send_op_cond(mmc); 2094 2095 if (err) { 2096 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) 2097 printf("Card did not respond to voltage select!\n"); 2098 #endif 2099 return -EOPNOTSUPP; 2100 } 2101 } 2102 2103 if (!err) 2104 mmc->init_in_progress = 1; 2105 2106 return err; 2107 } 2108 #endif 2109 2110 static int mmc_complete_init(struct mmc *mmc) 2111 { 2112 int err = 0; 2113 2114 mmc->init_in_progress = 0; 2115 if (mmc->op_cond_pending) 2116 err = mmc_complete_op_cond(mmc); 2117 2118 if (!err) 2119 err = mmc_startup(mmc); 2120 if (err) 2121 mmc->has_init = 0; 2122 else 2123 mmc->has_init = 1; 2124 return err; 2125 } 2126 2127 int mmc_init(struct mmc *mmc) 2128 { 2129 int err = 0; 2130 __maybe_unused unsigned start; 2131 #if CONFIG_IS_ENABLED(DM_MMC) 2132 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(mmc->dev); 2133 2134 upriv->mmc = mmc; 2135 #endif 2136 if (mmc->has_init) 2137 return 0; 2138 2139 start = get_timer(0); 2140 2141 if (!mmc->init_in_progress) 2142 err = mmc_start_init(mmc); 2143 2144 if (!err) 2145 err = mmc_complete_init(mmc); 2146 if (err) 2147 printf("%s: %d, time %lu\n", __func__, err, get_timer(start)); 2148 2149 return err; 2150 } 2151 2152 int mmc_set_dsr(struct mmc *mmc, u16 val) 2153 { 2154 mmc->dsr = val; 2155 return 0; 2156 } 2157 2158 /* CPU-specific MMC initializations */ 2159 __weak int cpu_mmc_init(bd_t *bis) 2160 { 2161 return -1; 2162 } 2163 2164 /* board-specific MMC initializations. */ 2165 __weak int board_mmc_init(bd_t *bis) 2166 { 2167 return -1; 2168 } 2169 2170 void mmc_set_preinit(struct mmc *mmc, int preinit) 2171 { 2172 mmc->preinit = preinit; 2173 } 2174 2175 #if CONFIG_IS_ENABLED(DM_MMC) && defined(CONFIG_SPL_BUILD) 2176 static int mmc_probe(bd_t *bis) 2177 { 2178 return 0; 2179 } 2180 #elif CONFIG_IS_ENABLED(DM_MMC) 2181 static int mmc_probe(bd_t *bis) 2182 { 2183 int ret, i; 2184 struct uclass *uc; 2185 struct udevice *dev; 2186 2187 ret = uclass_get(UCLASS_MMC, &uc); 2188 if (ret) 2189 return ret; 2190 2191 /* 2192 * Try to add them in sequence order. Really with driver model we 2193 * should allow holes, but the current MMC list does not allow that. 2194 * So if we request 0, 1, 3 we will get 0, 1, 2. 2195 */ 2196 for (i = 0; ; i++) { 2197 ret = uclass_get_device_by_seq(UCLASS_MMC, i, &dev); 2198 if (ret == -ENODEV) 2199 break; 2200 } 2201 uclass_foreach_dev(dev, uc) { 2202 ret = device_probe(dev); 2203 if (ret) 2204 printf("%s - probe failed: %d\n", dev->name, ret); 2205 } 2206 2207 return 0; 2208 } 2209 #else 2210 static int mmc_probe(bd_t *bis) 2211 { 2212 if (board_mmc_init(bis) < 0) 2213 cpu_mmc_init(bis); 2214 2215 return 0; 2216 } 2217 #endif 2218 2219 int mmc_initialize(bd_t *bis) 2220 { 2221 static int initialized = 0; 2222 int ret; 2223 if (initialized) /* Avoid initializing mmc multiple times */ 2224 return 0; 2225 initialized = 1; 2226 2227 #if !CONFIG_IS_ENABLED(BLK) 2228 #if !CONFIG_IS_ENABLED(MMC_TINY) 2229 mmc_list_init(); 2230 #endif 2231 #endif 2232 ret = mmc_probe(bis); 2233 if (ret) 2234 return ret; 2235 2236 #ifndef CONFIG_SPL_BUILD 2237 print_mmc_devices(','); 2238 #endif 2239 2240 mmc_do_preinit(); 2241 return 0; 2242 } 2243 2244 #ifdef CONFIG_CMD_BKOPS_ENABLE 2245 int mmc_set_bkops_enable(struct mmc *mmc) 2246 { 2247 int err; 2248 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN); 2249 2250 err = mmc_send_ext_csd(mmc, ext_csd); 2251 if (err) { 2252 puts("Could not get ext_csd register values\n"); 2253 return err; 2254 } 2255 2256 if (!(ext_csd[EXT_CSD_BKOPS_SUPPORT] & 0x1)) { 2257 puts("Background operations not supported on device\n"); 2258 return -EMEDIUMTYPE; 2259 } 2260 2261 if (ext_csd[EXT_CSD_BKOPS_EN] & 0x1) { 2262 puts("Background operations already enabled\n"); 2263 return 0; 2264 } 2265 2266 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BKOPS_EN, 1); 2267 if (err) { 2268 puts("Failed to enable manual background operations\n"); 2269 return err; 2270 } 2271 2272 puts("Enabled manual background operations\n"); 2273 2274 return 0; 2275 } 2276 #endif 2277