1 /* 2 * Copyright 2008, Freescale Semiconductor, Inc 3 * Andy Fleming 4 * 5 * Based vaguely on the Linux code 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #include <config.h> 11 #include <common.h> 12 #include <command.h> 13 #include <dm.h> 14 #include <dm/device-internal.h> 15 #include <errno.h> 16 #include <mmc.h> 17 #include <part.h> 18 #include <malloc.h> 19 #include <memalign.h> 20 #include <linux/list.h> 21 #include <div64.h> 22 #include "mmc_private.h" 23 24 static struct list_head mmc_devices; 25 static int cur_dev_num = -1; 26 27 __weak int board_mmc_getwp(struct mmc *mmc) 28 { 29 return -1; 30 } 31 32 int mmc_getwp(struct mmc *mmc) 33 { 34 int wp; 35 36 wp = board_mmc_getwp(mmc); 37 38 if (wp < 0) { 39 if (mmc->cfg->ops->getwp) 40 wp = mmc->cfg->ops->getwp(mmc); 41 else 42 wp = 0; 43 } 44 45 return wp; 46 } 47 48 __weak int board_mmc_getcd(struct mmc *mmc) 49 { 50 return -1; 51 } 52 53 int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) 54 { 55 int ret; 56 57 #ifdef CONFIG_MMC_TRACE 58 int i; 59 u8 *ptr; 60 61 printf("CMD_SEND:%d\n", cmd->cmdidx); 62 printf("\t\tARG\t\t\t 0x%08X\n", cmd->cmdarg); 63 ret = mmc->cfg->ops->send_cmd(mmc, cmd, data); 64 if (ret) { 65 printf("\t\tRET\t\t\t %d\n", ret); 66 } else { 67 switch (cmd->resp_type) { 68 case MMC_RSP_NONE: 69 printf("\t\tMMC_RSP_NONE\n"); 70 break; 71 case MMC_RSP_R1: 72 printf("\t\tMMC_RSP_R1,5,6,7 \t 0x%08X \n", 73 cmd->response[0]); 74 break; 75 case MMC_RSP_R1b: 76 printf("\t\tMMC_RSP_R1b\t\t 0x%08X \n", 77 cmd->response[0]); 78 break; 79 case MMC_RSP_R2: 80 printf("\t\tMMC_RSP_R2\t\t 0x%08X \n", 81 cmd->response[0]); 82 printf("\t\t \t\t 0x%08X \n", 83 cmd->response[1]); 84 printf("\t\t \t\t 0x%08X \n", 85 cmd->response[2]); 86 printf("\t\t \t\t 0x%08X \n", 87 cmd->response[3]); 88 printf("\n"); 89 printf("\t\t\t\t\tDUMPING DATA\n"); 90 for (i = 0; i < 4; i++) { 91 int j; 92 printf("\t\t\t\t\t%03d - ", i*4); 93 ptr = (u8 *)&cmd->response[i]; 94 ptr += 3; 95 for (j = 0; j < 4; j++) 96 printf("%02X ", *ptr--); 97 printf("\n"); 98 } 99 break; 100 case MMC_RSP_R3: 101 printf("\t\tMMC_RSP_R3,4\t\t 0x%08X \n", 102 cmd->response[0]); 103 break; 104 default: 105 printf("\t\tERROR MMC rsp not supported\n"); 106 break; 107 } 108 } 109 #else 110 ret = mmc->cfg->ops->send_cmd(mmc, cmd, data); 111 #endif 112 return ret; 113 } 114 115 int mmc_send_status(struct mmc *mmc, int timeout) 116 { 117 struct mmc_cmd cmd; 118 int err, retries = 5; 119 #ifdef CONFIG_MMC_TRACE 120 int status; 121 #endif 122 123 cmd.cmdidx = MMC_CMD_SEND_STATUS; 124 cmd.resp_type = MMC_RSP_R1; 125 if (!mmc_host_is_spi(mmc)) 126 cmd.cmdarg = mmc->rca << 16; 127 128 while (1) { 129 err = mmc_send_cmd(mmc, &cmd, NULL); 130 if (!err) { 131 if ((cmd.response[0] & MMC_STATUS_RDY_FOR_DATA) && 132 (cmd.response[0] & MMC_STATUS_CURR_STATE) != 133 MMC_STATE_PRG) 134 break; 135 else if (cmd.response[0] & MMC_STATUS_MASK) { 136 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) 137 printf("Status Error: 0x%08X\n", 138 cmd.response[0]); 139 #endif 140 return COMM_ERR; 141 } 142 } else if (--retries < 0) 143 return err; 144 145 if (timeout-- <= 0) 146 break; 147 148 udelay(1000); 149 } 150 151 #ifdef CONFIG_MMC_TRACE 152 status = (cmd.response[0] & MMC_STATUS_CURR_STATE) >> 9; 153 printf("CURR STATE:%d\n", status); 154 #endif 155 if (timeout <= 0) { 156 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) 157 printf("Timeout waiting card ready\n"); 158 #endif 159 return TIMEOUT; 160 } 161 if (cmd.response[0] & MMC_STATUS_SWITCH_ERROR) 162 return SWITCH_ERR; 163 164 return 0; 165 } 166 167 int mmc_set_blocklen(struct mmc *mmc, int len) 168 { 169 struct mmc_cmd cmd; 170 171 if (mmc->ddr_mode) 172 return 0; 173 174 cmd.cmdidx = MMC_CMD_SET_BLOCKLEN; 175 cmd.resp_type = MMC_RSP_R1; 176 cmd.cmdarg = len; 177 178 return mmc_send_cmd(mmc, &cmd, NULL); 179 } 180 181 struct mmc *find_mmc_device(int dev_num) 182 { 183 struct mmc *m; 184 struct list_head *entry; 185 186 list_for_each(entry, &mmc_devices) { 187 m = list_entry(entry, struct mmc, link); 188 189 if (m->block_dev.devnum == dev_num) 190 return m; 191 } 192 193 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) 194 printf("MMC Device %d not found\n", dev_num); 195 #endif 196 197 return NULL; 198 } 199 200 static int mmc_read_blocks(struct mmc *mmc, void *dst, lbaint_t start, 201 lbaint_t blkcnt) 202 { 203 struct mmc_cmd cmd; 204 struct mmc_data data; 205 206 if (blkcnt > 1) 207 cmd.cmdidx = MMC_CMD_READ_MULTIPLE_BLOCK; 208 else 209 cmd.cmdidx = MMC_CMD_READ_SINGLE_BLOCK; 210 211 if (mmc->high_capacity) 212 cmd.cmdarg = start; 213 else 214 cmd.cmdarg = start * mmc->read_bl_len; 215 216 cmd.resp_type = MMC_RSP_R1; 217 218 data.dest = dst; 219 data.blocks = blkcnt; 220 data.blocksize = mmc->read_bl_len; 221 data.flags = MMC_DATA_READ; 222 223 if (mmc_send_cmd(mmc, &cmd, &data)) 224 return 0; 225 226 if (blkcnt > 1) { 227 cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION; 228 cmd.cmdarg = 0; 229 cmd.resp_type = MMC_RSP_R1b; 230 if (mmc_send_cmd(mmc, &cmd, NULL)) { 231 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) 232 printf("mmc fail to send stop cmd\n"); 233 #endif 234 return 0; 235 } 236 } 237 238 return blkcnt; 239 } 240 241 static ulong mmc_bread(struct blk_desc *block_dev, lbaint_t start, 242 lbaint_t blkcnt, void *dst) 243 { 244 int dev_num = block_dev->devnum; 245 int err; 246 lbaint_t cur, blocks_todo = blkcnt; 247 248 if (blkcnt == 0) 249 return 0; 250 251 struct mmc *mmc = find_mmc_device(dev_num); 252 if (!mmc) 253 return 0; 254 255 err = mmc_select_hwpart(dev_num, block_dev->hwpart); 256 if (err < 0) 257 return 0; 258 259 if ((start + blkcnt) > mmc->block_dev.lba) { 260 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) 261 printf("MMC: block number 0x" LBAF " exceeds max(0x" LBAF ")\n", 262 start + blkcnt, mmc->block_dev.lba); 263 #endif 264 return 0; 265 } 266 267 if (mmc_set_blocklen(mmc, mmc->read_bl_len)) { 268 debug("%s: Failed to set blocklen\n", __func__); 269 return 0; 270 } 271 272 do { 273 cur = (blocks_todo > mmc->cfg->b_max) ? 274 mmc->cfg->b_max : blocks_todo; 275 if (mmc_read_blocks(mmc, dst, start, cur) != cur) { 276 debug("%s: Failed to read blocks\n", __func__); 277 return 0; 278 } 279 blocks_todo -= cur; 280 start += cur; 281 dst += cur * mmc->read_bl_len; 282 } while (blocks_todo > 0); 283 284 return blkcnt; 285 } 286 287 static int mmc_go_idle(struct mmc *mmc) 288 { 289 struct mmc_cmd cmd; 290 int err; 291 292 udelay(1000); 293 294 cmd.cmdidx = MMC_CMD_GO_IDLE_STATE; 295 cmd.cmdarg = 0; 296 cmd.resp_type = MMC_RSP_NONE; 297 298 err = mmc_send_cmd(mmc, &cmd, NULL); 299 300 if (err) 301 return err; 302 303 udelay(2000); 304 305 return 0; 306 } 307 308 static int sd_send_op_cond(struct mmc *mmc) 309 { 310 int timeout = 1000; 311 int err; 312 struct mmc_cmd cmd; 313 314 while (1) { 315 cmd.cmdidx = MMC_CMD_APP_CMD; 316 cmd.resp_type = MMC_RSP_R1; 317 cmd.cmdarg = 0; 318 319 err = mmc_send_cmd(mmc, &cmd, NULL); 320 321 if (err) 322 return err; 323 324 cmd.cmdidx = SD_CMD_APP_SEND_OP_COND; 325 cmd.resp_type = MMC_RSP_R3; 326 327 /* 328 * Most cards do not answer if some reserved bits 329 * in the ocr are set. However, Some controller 330 * can set bit 7 (reserved for low voltages), but 331 * how to manage low voltages SD card is not yet 332 * specified. 333 */ 334 cmd.cmdarg = mmc_host_is_spi(mmc) ? 0 : 335 (mmc->cfg->voltages & 0xff8000); 336 337 if (mmc->version == SD_VERSION_2) 338 cmd.cmdarg |= OCR_HCS; 339 340 err = mmc_send_cmd(mmc, &cmd, NULL); 341 342 if (err) 343 return err; 344 345 if (cmd.response[0] & OCR_BUSY) 346 break; 347 348 if (timeout-- <= 0) 349 return UNUSABLE_ERR; 350 351 udelay(1000); 352 } 353 354 if (mmc->version != SD_VERSION_2) 355 mmc->version = SD_VERSION_1_0; 356 357 if (mmc_host_is_spi(mmc)) { /* read OCR for spi */ 358 cmd.cmdidx = MMC_CMD_SPI_READ_OCR; 359 cmd.resp_type = MMC_RSP_R3; 360 cmd.cmdarg = 0; 361 362 err = mmc_send_cmd(mmc, &cmd, NULL); 363 364 if (err) 365 return err; 366 } 367 368 mmc->ocr = cmd.response[0]; 369 370 mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS); 371 mmc->rca = 0; 372 373 return 0; 374 } 375 376 static int mmc_send_op_cond_iter(struct mmc *mmc, int use_arg) 377 { 378 struct mmc_cmd cmd; 379 int err; 380 381 cmd.cmdidx = MMC_CMD_SEND_OP_COND; 382 cmd.resp_type = MMC_RSP_R3; 383 cmd.cmdarg = 0; 384 if (use_arg && !mmc_host_is_spi(mmc)) 385 cmd.cmdarg = OCR_HCS | 386 (mmc->cfg->voltages & 387 (mmc->ocr & OCR_VOLTAGE_MASK)) | 388 (mmc->ocr & OCR_ACCESS_MODE); 389 390 err = mmc_send_cmd(mmc, &cmd, NULL); 391 if (err) 392 return err; 393 mmc->ocr = cmd.response[0]; 394 return 0; 395 } 396 397 static int mmc_send_op_cond(struct mmc *mmc) 398 { 399 int err, i; 400 401 /* Some cards seem to need this */ 402 mmc_go_idle(mmc); 403 404 /* Asking to the card its capabilities */ 405 for (i = 0; i < 2; i++) { 406 err = mmc_send_op_cond_iter(mmc, i != 0); 407 if (err) 408 return err; 409 410 /* exit if not busy (flag seems to be inverted) */ 411 if (mmc->ocr & OCR_BUSY) 412 break; 413 } 414 mmc->op_cond_pending = 1; 415 return 0; 416 } 417 418 static int mmc_complete_op_cond(struct mmc *mmc) 419 { 420 struct mmc_cmd cmd; 421 int timeout = 1000; 422 uint start; 423 int err; 424 425 mmc->op_cond_pending = 0; 426 if (!(mmc->ocr & OCR_BUSY)) { 427 start = get_timer(0); 428 while (1) { 429 err = mmc_send_op_cond_iter(mmc, 1); 430 if (err) 431 return err; 432 if (mmc->ocr & OCR_BUSY) 433 break; 434 if (get_timer(start) > timeout) 435 return UNUSABLE_ERR; 436 udelay(100); 437 } 438 } 439 440 if (mmc_host_is_spi(mmc)) { /* read OCR for spi */ 441 cmd.cmdidx = MMC_CMD_SPI_READ_OCR; 442 cmd.resp_type = MMC_RSP_R3; 443 cmd.cmdarg = 0; 444 445 err = mmc_send_cmd(mmc, &cmd, NULL); 446 447 if (err) 448 return err; 449 450 mmc->ocr = cmd.response[0]; 451 } 452 453 mmc->version = MMC_VERSION_UNKNOWN; 454 455 mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS); 456 mmc->rca = 1; 457 458 return 0; 459 } 460 461 462 static int mmc_send_ext_csd(struct mmc *mmc, u8 *ext_csd) 463 { 464 struct mmc_cmd cmd; 465 struct mmc_data data; 466 int err; 467 468 /* Get the Card Status Register */ 469 cmd.cmdidx = MMC_CMD_SEND_EXT_CSD; 470 cmd.resp_type = MMC_RSP_R1; 471 cmd.cmdarg = 0; 472 473 data.dest = (char *)ext_csd; 474 data.blocks = 1; 475 data.blocksize = MMC_MAX_BLOCK_LEN; 476 data.flags = MMC_DATA_READ; 477 478 err = mmc_send_cmd(mmc, &cmd, &data); 479 480 return err; 481 } 482 483 484 static int mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value) 485 { 486 struct mmc_cmd cmd; 487 int timeout = 1000; 488 int ret; 489 490 cmd.cmdidx = MMC_CMD_SWITCH; 491 cmd.resp_type = MMC_RSP_R1b; 492 cmd.cmdarg = (MMC_SWITCH_MODE_WRITE_BYTE << 24) | 493 (index << 16) | 494 (value << 8); 495 496 ret = mmc_send_cmd(mmc, &cmd, NULL); 497 498 /* Waiting for the ready status */ 499 if (!ret) 500 ret = mmc_send_status(mmc, timeout); 501 502 return ret; 503 504 } 505 506 static int mmc_change_freq(struct mmc *mmc) 507 { 508 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN); 509 char cardtype; 510 int err; 511 512 mmc->card_caps = 0; 513 514 if (mmc_host_is_spi(mmc)) 515 return 0; 516 517 /* Only version 4 supports high-speed */ 518 if (mmc->version < MMC_VERSION_4) 519 return 0; 520 521 mmc->card_caps |= MMC_MODE_4BIT | MMC_MODE_8BIT; 522 523 err = mmc_send_ext_csd(mmc, ext_csd); 524 525 if (err) 526 return err; 527 528 cardtype = ext_csd[EXT_CSD_CARD_TYPE] & 0xf; 529 530 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_HS_TIMING, 1); 531 532 if (err) 533 return err == SWITCH_ERR ? 0 : err; 534 535 /* Now check to see that it worked */ 536 err = mmc_send_ext_csd(mmc, ext_csd); 537 538 if (err) 539 return err; 540 541 /* No high-speed support */ 542 if (!ext_csd[EXT_CSD_HS_TIMING]) 543 return 0; 544 545 /* High Speed is set, there are two types: 52MHz and 26MHz */ 546 if (cardtype & EXT_CSD_CARD_TYPE_52) { 547 if (cardtype & EXT_CSD_CARD_TYPE_DDR_1_8V) 548 mmc->card_caps |= MMC_MODE_DDR_52MHz; 549 mmc->card_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS; 550 } else { 551 mmc->card_caps |= MMC_MODE_HS; 552 } 553 554 return 0; 555 } 556 557 static int mmc_set_capacity(struct mmc *mmc, int part_num) 558 { 559 switch (part_num) { 560 case 0: 561 mmc->capacity = mmc->capacity_user; 562 break; 563 case 1: 564 case 2: 565 mmc->capacity = mmc->capacity_boot; 566 break; 567 case 3: 568 mmc->capacity = mmc->capacity_rpmb; 569 break; 570 case 4: 571 case 5: 572 case 6: 573 case 7: 574 mmc->capacity = mmc->capacity_gp[part_num - 4]; 575 break; 576 default: 577 return -1; 578 } 579 580 mmc->block_dev.lba = lldiv(mmc->capacity, mmc->read_bl_len); 581 582 return 0; 583 } 584 585 int mmc_switch_part(int dev_num, unsigned int part_num) 586 { 587 struct mmc *mmc = find_mmc_device(dev_num); 588 int ret; 589 590 if (!mmc) 591 return -1; 592 593 ret = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_PART_CONF, 594 (mmc->part_config & ~PART_ACCESS_MASK) 595 | (part_num & PART_ACCESS_MASK)); 596 597 /* 598 * Set the capacity if the switch succeeded or was intended 599 * to return to representing the raw device. 600 */ 601 if ((ret == 0) || ((ret == -ENODEV) && (part_num == 0))) { 602 ret = mmc_set_capacity(mmc, part_num); 603 mmc->block_dev.hwpart = part_num; 604 } 605 606 return ret; 607 } 608 609 static int mmc_select_hwpartp(struct blk_desc *desc, int hwpart) 610 { 611 struct mmc *mmc = find_mmc_device(desc->devnum); 612 int ret; 613 614 if (!mmc) 615 return -ENODEV; 616 617 if (mmc->block_dev.hwpart == hwpart) 618 return 0; 619 620 if (mmc->part_config == MMCPART_NOAVAILABLE) 621 return -EMEDIUMTYPE; 622 623 ret = mmc_switch_part(desc->devnum, hwpart); 624 if (ret) 625 return ret; 626 627 return 0; 628 } 629 630 int mmc_select_hwpart(int dev_num, int hwpart) 631 { 632 struct mmc *mmc = find_mmc_device(dev_num); 633 int ret; 634 635 if (!mmc) 636 return -ENODEV; 637 638 if (mmc->block_dev.hwpart == hwpart) 639 return 0; 640 641 if (mmc->part_config == MMCPART_NOAVAILABLE) 642 return -EMEDIUMTYPE; 643 644 ret = mmc_switch_part(dev_num, hwpart); 645 if (ret) 646 return ret; 647 648 return 0; 649 } 650 651 int mmc_hwpart_config(struct mmc *mmc, 652 const struct mmc_hwpart_conf *conf, 653 enum mmc_hwpart_conf_mode mode) 654 { 655 u8 part_attrs = 0; 656 u32 enh_size_mult; 657 u32 enh_start_addr; 658 u32 gp_size_mult[4]; 659 u32 max_enh_size_mult; 660 u32 tot_enh_size_mult = 0; 661 u8 wr_rel_set; 662 int i, pidx, err; 663 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN); 664 665 if (mode < MMC_HWPART_CONF_CHECK || mode > MMC_HWPART_CONF_COMPLETE) 666 return -EINVAL; 667 668 if (IS_SD(mmc) || (mmc->version < MMC_VERSION_4_41)) { 669 printf("eMMC >= 4.4 required for enhanced user data area\n"); 670 return -EMEDIUMTYPE; 671 } 672 673 if (!(mmc->part_support & PART_SUPPORT)) { 674 printf("Card does not support partitioning\n"); 675 return -EMEDIUMTYPE; 676 } 677 678 if (!mmc->hc_wp_grp_size) { 679 printf("Card does not define HC WP group size\n"); 680 return -EMEDIUMTYPE; 681 } 682 683 /* check partition alignment and total enhanced size */ 684 if (conf->user.enh_size) { 685 if (conf->user.enh_size % mmc->hc_wp_grp_size || 686 conf->user.enh_start % mmc->hc_wp_grp_size) { 687 printf("User data enhanced area not HC WP group " 688 "size aligned\n"); 689 return -EINVAL; 690 } 691 part_attrs |= EXT_CSD_ENH_USR; 692 enh_size_mult = conf->user.enh_size / mmc->hc_wp_grp_size; 693 if (mmc->high_capacity) { 694 enh_start_addr = conf->user.enh_start; 695 } else { 696 enh_start_addr = (conf->user.enh_start << 9); 697 } 698 } else { 699 enh_size_mult = 0; 700 enh_start_addr = 0; 701 } 702 tot_enh_size_mult += enh_size_mult; 703 704 for (pidx = 0; pidx < 4; pidx++) { 705 if (conf->gp_part[pidx].size % mmc->hc_wp_grp_size) { 706 printf("GP%i partition not HC WP group size " 707 "aligned\n", pidx+1); 708 return -EINVAL; 709 } 710 gp_size_mult[pidx] = conf->gp_part[pidx].size / mmc->hc_wp_grp_size; 711 if (conf->gp_part[pidx].size && conf->gp_part[pidx].enhanced) { 712 part_attrs |= EXT_CSD_ENH_GP(pidx); 713 tot_enh_size_mult += gp_size_mult[pidx]; 714 } 715 } 716 717 if (part_attrs && ! (mmc->part_support & ENHNCD_SUPPORT)) { 718 printf("Card does not support enhanced attribute\n"); 719 return -EMEDIUMTYPE; 720 } 721 722 err = mmc_send_ext_csd(mmc, ext_csd); 723 if (err) 724 return err; 725 726 max_enh_size_mult = 727 (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+2] << 16) + 728 (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+1] << 8) + 729 ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT]; 730 if (tot_enh_size_mult > max_enh_size_mult) { 731 printf("Total enhanced size exceeds maximum (%u > %u)\n", 732 tot_enh_size_mult, max_enh_size_mult); 733 return -EMEDIUMTYPE; 734 } 735 736 /* The default value of EXT_CSD_WR_REL_SET is device 737 * dependent, the values can only be changed if the 738 * EXT_CSD_HS_CTRL_REL bit is set. The values can be 739 * changed only once and before partitioning is completed. */ 740 wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET]; 741 if (conf->user.wr_rel_change) { 742 if (conf->user.wr_rel_set) 743 wr_rel_set |= EXT_CSD_WR_DATA_REL_USR; 744 else 745 wr_rel_set &= ~EXT_CSD_WR_DATA_REL_USR; 746 } 747 for (pidx = 0; pidx < 4; pidx++) { 748 if (conf->gp_part[pidx].wr_rel_change) { 749 if (conf->gp_part[pidx].wr_rel_set) 750 wr_rel_set |= EXT_CSD_WR_DATA_REL_GP(pidx); 751 else 752 wr_rel_set &= ~EXT_CSD_WR_DATA_REL_GP(pidx); 753 } 754 } 755 756 if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET] && 757 !(ext_csd[EXT_CSD_WR_REL_PARAM] & EXT_CSD_HS_CTRL_REL)) { 758 puts("Card does not support host controlled partition write " 759 "reliability settings\n"); 760 return -EMEDIUMTYPE; 761 } 762 763 if (ext_csd[EXT_CSD_PARTITION_SETTING] & 764 EXT_CSD_PARTITION_SETTING_COMPLETED) { 765 printf("Card already partitioned\n"); 766 return -EPERM; 767 } 768 769 if (mode == MMC_HWPART_CONF_CHECK) 770 return 0; 771 772 /* Partitioning requires high-capacity size definitions */ 773 if (!(ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01)) { 774 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, 775 EXT_CSD_ERASE_GROUP_DEF, 1); 776 777 if (err) 778 return err; 779 780 ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1; 781 782 /* update erase group size to be high-capacity */ 783 mmc->erase_grp_size = 784 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024; 785 786 } 787 788 /* all OK, write the configuration */ 789 for (i = 0; i < 4; i++) { 790 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, 791 EXT_CSD_ENH_START_ADDR+i, 792 (enh_start_addr >> (i*8)) & 0xFF); 793 if (err) 794 return err; 795 } 796 for (i = 0; i < 3; i++) { 797 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, 798 EXT_CSD_ENH_SIZE_MULT+i, 799 (enh_size_mult >> (i*8)) & 0xFF); 800 if (err) 801 return err; 802 } 803 for (pidx = 0; pidx < 4; pidx++) { 804 for (i = 0; i < 3; i++) { 805 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, 806 EXT_CSD_GP_SIZE_MULT+pidx*3+i, 807 (gp_size_mult[pidx] >> (i*8)) & 0xFF); 808 if (err) 809 return err; 810 } 811 } 812 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, 813 EXT_CSD_PARTITIONS_ATTRIBUTE, part_attrs); 814 if (err) 815 return err; 816 817 if (mode == MMC_HWPART_CONF_SET) 818 return 0; 819 820 /* The WR_REL_SET is a write-once register but shall be 821 * written before setting PART_SETTING_COMPLETED. As it is 822 * write-once we can only write it when completing the 823 * partitioning. */ 824 if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET]) { 825 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, 826 EXT_CSD_WR_REL_SET, wr_rel_set); 827 if (err) 828 return err; 829 } 830 831 /* Setting PART_SETTING_COMPLETED confirms the partition 832 * configuration but it only becomes effective after power 833 * cycle, so we do not adjust the partition related settings 834 * in the mmc struct. */ 835 836 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, 837 EXT_CSD_PARTITION_SETTING, 838 EXT_CSD_PARTITION_SETTING_COMPLETED); 839 if (err) 840 return err; 841 842 return 0; 843 } 844 845 int mmc_getcd(struct mmc *mmc) 846 { 847 int cd; 848 849 cd = board_mmc_getcd(mmc); 850 851 if (cd < 0) { 852 if (mmc->cfg->ops->getcd) 853 cd = mmc->cfg->ops->getcd(mmc); 854 else 855 cd = 1; 856 } 857 858 return cd; 859 } 860 861 static int sd_switch(struct mmc *mmc, int mode, int group, u8 value, u8 *resp) 862 { 863 struct mmc_cmd cmd; 864 struct mmc_data data; 865 866 /* Switch the frequency */ 867 cmd.cmdidx = SD_CMD_SWITCH_FUNC; 868 cmd.resp_type = MMC_RSP_R1; 869 cmd.cmdarg = (mode << 31) | 0xffffff; 870 cmd.cmdarg &= ~(0xf << (group * 4)); 871 cmd.cmdarg |= value << (group * 4); 872 873 data.dest = (char *)resp; 874 data.blocksize = 64; 875 data.blocks = 1; 876 data.flags = MMC_DATA_READ; 877 878 return mmc_send_cmd(mmc, &cmd, &data); 879 } 880 881 882 static int sd_change_freq(struct mmc *mmc) 883 { 884 int err; 885 struct mmc_cmd cmd; 886 ALLOC_CACHE_ALIGN_BUFFER(uint, scr, 2); 887 ALLOC_CACHE_ALIGN_BUFFER(uint, switch_status, 16); 888 struct mmc_data data; 889 int timeout; 890 891 mmc->card_caps = 0; 892 893 if (mmc_host_is_spi(mmc)) 894 return 0; 895 896 /* Read the SCR to find out if this card supports higher speeds */ 897 cmd.cmdidx = MMC_CMD_APP_CMD; 898 cmd.resp_type = MMC_RSP_R1; 899 cmd.cmdarg = mmc->rca << 16; 900 901 err = mmc_send_cmd(mmc, &cmd, NULL); 902 903 if (err) 904 return err; 905 906 cmd.cmdidx = SD_CMD_APP_SEND_SCR; 907 cmd.resp_type = MMC_RSP_R1; 908 cmd.cmdarg = 0; 909 910 timeout = 3; 911 912 retry_scr: 913 data.dest = (char *)scr; 914 data.blocksize = 8; 915 data.blocks = 1; 916 data.flags = MMC_DATA_READ; 917 918 err = mmc_send_cmd(mmc, &cmd, &data); 919 920 if (err) { 921 if (timeout--) 922 goto retry_scr; 923 924 return err; 925 } 926 927 mmc->scr[0] = __be32_to_cpu(scr[0]); 928 mmc->scr[1] = __be32_to_cpu(scr[1]); 929 930 switch ((mmc->scr[0] >> 24) & 0xf) { 931 case 0: 932 mmc->version = SD_VERSION_1_0; 933 break; 934 case 1: 935 mmc->version = SD_VERSION_1_10; 936 break; 937 case 2: 938 mmc->version = SD_VERSION_2; 939 if ((mmc->scr[0] >> 15) & 0x1) 940 mmc->version = SD_VERSION_3; 941 break; 942 default: 943 mmc->version = SD_VERSION_1_0; 944 break; 945 } 946 947 if (mmc->scr[0] & SD_DATA_4BIT) 948 mmc->card_caps |= MMC_MODE_4BIT; 949 950 /* Version 1.0 doesn't support switching */ 951 if (mmc->version == SD_VERSION_1_0) 952 return 0; 953 954 timeout = 4; 955 while (timeout--) { 956 err = sd_switch(mmc, SD_SWITCH_CHECK, 0, 1, 957 (u8 *)switch_status); 958 959 if (err) 960 return err; 961 962 /* The high-speed function is busy. Try again */ 963 if (!(__be32_to_cpu(switch_status[7]) & SD_HIGHSPEED_BUSY)) 964 break; 965 } 966 967 /* If high-speed isn't supported, we return */ 968 if (!(__be32_to_cpu(switch_status[3]) & SD_HIGHSPEED_SUPPORTED)) 969 return 0; 970 971 /* 972 * If the host doesn't support SD_HIGHSPEED, do not switch card to 973 * HIGHSPEED mode even if the card support SD_HIGHSPPED. 974 * This can avoid furthur problem when the card runs in different 975 * mode between the host. 976 */ 977 if (!((mmc->cfg->host_caps & MMC_MODE_HS_52MHz) && 978 (mmc->cfg->host_caps & MMC_MODE_HS))) 979 return 0; 980 981 err = sd_switch(mmc, SD_SWITCH_SWITCH, 0, 1, (u8 *)switch_status); 982 983 if (err) 984 return err; 985 986 if ((__be32_to_cpu(switch_status[4]) & 0x0f000000) == 0x01000000) 987 mmc->card_caps |= MMC_MODE_HS; 988 989 return 0; 990 } 991 992 /* frequency bases */ 993 /* divided by 10 to be nice to platforms without floating point */ 994 static const int fbase[] = { 995 10000, 996 100000, 997 1000000, 998 10000000, 999 }; 1000 1001 /* Multiplier values for TRAN_SPEED. Multiplied by 10 to be nice 1002 * to platforms without floating point. 1003 */ 1004 static const int multipliers[] = { 1005 0, /* reserved */ 1006 10, 1007 12, 1008 13, 1009 15, 1010 20, 1011 25, 1012 30, 1013 35, 1014 40, 1015 45, 1016 50, 1017 55, 1018 60, 1019 70, 1020 80, 1021 }; 1022 1023 static void mmc_set_ios(struct mmc *mmc) 1024 { 1025 if (mmc->cfg->ops->set_ios) 1026 mmc->cfg->ops->set_ios(mmc); 1027 } 1028 1029 void mmc_set_clock(struct mmc *mmc, uint clock) 1030 { 1031 if (clock > mmc->cfg->f_max) 1032 clock = mmc->cfg->f_max; 1033 1034 if (clock < mmc->cfg->f_min) 1035 clock = mmc->cfg->f_min; 1036 1037 mmc->clock = clock; 1038 1039 mmc_set_ios(mmc); 1040 } 1041 1042 static void mmc_set_bus_width(struct mmc *mmc, uint width) 1043 { 1044 mmc->bus_width = width; 1045 1046 mmc_set_ios(mmc); 1047 } 1048 1049 static int mmc_startup(struct mmc *mmc) 1050 { 1051 int err, i; 1052 uint mult, freq; 1053 u64 cmult, csize, capacity; 1054 struct mmc_cmd cmd; 1055 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN); 1056 ALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, MMC_MAX_BLOCK_LEN); 1057 int timeout = 1000; 1058 bool has_parts = false; 1059 bool part_completed; 1060 1061 #ifdef CONFIG_MMC_SPI_CRC_ON 1062 if (mmc_host_is_spi(mmc)) { /* enable CRC check for spi */ 1063 cmd.cmdidx = MMC_CMD_SPI_CRC_ON_OFF; 1064 cmd.resp_type = MMC_RSP_R1; 1065 cmd.cmdarg = 1; 1066 err = mmc_send_cmd(mmc, &cmd, NULL); 1067 1068 if (err) 1069 return err; 1070 } 1071 #endif 1072 1073 /* Put the Card in Identify Mode */ 1074 cmd.cmdidx = mmc_host_is_spi(mmc) ? MMC_CMD_SEND_CID : 1075 MMC_CMD_ALL_SEND_CID; /* cmd not supported in spi */ 1076 cmd.resp_type = MMC_RSP_R2; 1077 cmd.cmdarg = 0; 1078 1079 err = mmc_send_cmd(mmc, &cmd, NULL); 1080 1081 if (err) 1082 return err; 1083 1084 memcpy(mmc->cid, cmd.response, 16); 1085 1086 /* 1087 * For MMC cards, set the Relative Address. 1088 * For SD cards, get the Relatvie Address. 1089 * This also puts the cards into Standby State 1090 */ 1091 if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */ 1092 cmd.cmdidx = SD_CMD_SEND_RELATIVE_ADDR; 1093 cmd.cmdarg = mmc->rca << 16; 1094 cmd.resp_type = MMC_RSP_R6; 1095 1096 err = mmc_send_cmd(mmc, &cmd, NULL); 1097 1098 if (err) 1099 return err; 1100 1101 if (IS_SD(mmc)) 1102 mmc->rca = (cmd.response[0] >> 16) & 0xffff; 1103 } 1104 1105 /* Get the Card-Specific Data */ 1106 cmd.cmdidx = MMC_CMD_SEND_CSD; 1107 cmd.resp_type = MMC_RSP_R2; 1108 cmd.cmdarg = mmc->rca << 16; 1109 1110 err = mmc_send_cmd(mmc, &cmd, NULL); 1111 1112 /* Waiting for the ready status */ 1113 mmc_send_status(mmc, timeout); 1114 1115 if (err) 1116 return err; 1117 1118 mmc->csd[0] = cmd.response[0]; 1119 mmc->csd[1] = cmd.response[1]; 1120 mmc->csd[2] = cmd.response[2]; 1121 mmc->csd[3] = cmd.response[3]; 1122 1123 if (mmc->version == MMC_VERSION_UNKNOWN) { 1124 int version = (cmd.response[0] >> 26) & 0xf; 1125 1126 switch (version) { 1127 case 0: 1128 mmc->version = MMC_VERSION_1_2; 1129 break; 1130 case 1: 1131 mmc->version = MMC_VERSION_1_4; 1132 break; 1133 case 2: 1134 mmc->version = MMC_VERSION_2_2; 1135 break; 1136 case 3: 1137 mmc->version = MMC_VERSION_3; 1138 break; 1139 case 4: 1140 mmc->version = MMC_VERSION_4; 1141 break; 1142 default: 1143 mmc->version = MMC_VERSION_1_2; 1144 break; 1145 } 1146 } 1147 1148 /* divide frequency by 10, since the mults are 10x bigger */ 1149 freq = fbase[(cmd.response[0] & 0x7)]; 1150 mult = multipliers[((cmd.response[0] >> 3) & 0xf)]; 1151 1152 mmc->tran_speed = freq * mult; 1153 1154 mmc->dsr_imp = ((cmd.response[1] >> 12) & 0x1); 1155 mmc->read_bl_len = 1 << ((cmd.response[1] >> 16) & 0xf); 1156 1157 if (IS_SD(mmc)) 1158 mmc->write_bl_len = mmc->read_bl_len; 1159 else 1160 mmc->write_bl_len = 1 << ((cmd.response[3] >> 22) & 0xf); 1161 1162 if (mmc->high_capacity) { 1163 csize = (mmc->csd[1] & 0x3f) << 16 1164 | (mmc->csd[2] & 0xffff0000) >> 16; 1165 cmult = 8; 1166 } else { 1167 csize = (mmc->csd[1] & 0x3ff) << 2 1168 | (mmc->csd[2] & 0xc0000000) >> 30; 1169 cmult = (mmc->csd[2] & 0x00038000) >> 15; 1170 } 1171 1172 mmc->capacity_user = (csize + 1) << (cmult + 2); 1173 mmc->capacity_user *= mmc->read_bl_len; 1174 mmc->capacity_boot = 0; 1175 mmc->capacity_rpmb = 0; 1176 for (i = 0; i < 4; i++) 1177 mmc->capacity_gp[i] = 0; 1178 1179 if (mmc->read_bl_len > MMC_MAX_BLOCK_LEN) 1180 mmc->read_bl_len = MMC_MAX_BLOCK_LEN; 1181 1182 if (mmc->write_bl_len > MMC_MAX_BLOCK_LEN) 1183 mmc->write_bl_len = MMC_MAX_BLOCK_LEN; 1184 1185 if ((mmc->dsr_imp) && (0xffffffff != mmc->dsr)) { 1186 cmd.cmdidx = MMC_CMD_SET_DSR; 1187 cmd.cmdarg = (mmc->dsr & 0xffff) << 16; 1188 cmd.resp_type = MMC_RSP_NONE; 1189 if (mmc_send_cmd(mmc, &cmd, NULL)) 1190 printf("MMC: SET_DSR failed\n"); 1191 } 1192 1193 /* Select the card, and put it into Transfer Mode */ 1194 if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */ 1195 cmd.cmdidx = MMC_CMD_SELECT_CARD; 1196 cmd.resp_type = MMC_RSP_R1; 1197 cmd.cmdarg = mmc->rca << 16; 1198 err = mmc_send_cmd(mmc, &cmd, NULL); 1199 1200 if (err) 1201 return err; 1202 } 1203 1204 /* 1205 * For SD, its erase group is always one sector 1206 */ 1207 mmc->erase_grp_size = 1; 1208 mmc->part_config = MMCPART_NOAVAILABLE; 1209 if (!IS_SD(mmc) && (mmc->version >= MMC_VERSION_4)) { 1210 /* check ext_csd version and capacity */ 1211 err = mmc_send_ext_csd(mmc, ext_csd); 1212 if (err) 1213 return err; 1214 if (ext_csd[EXT_CSD_REV] >= 2) { 1215 /* 1216 * According to the JEDEC Standard, the value of 1217 * ext_csd's capacity is valid if the value is more 1218 * than 2GB 1219 */ 1220 capacity = ext_csd[EXT_CSD_SEC_CNT] << 0 1221 | ext_csd[EXT_CSD_SEC_CNT + 1] << 8 1222 | ext_csd[EXT_CSD_SEC_CNT + 2] << 16 1223 | ext_csd[EXT_CSD_SEC_CNT + 3] << 24; 1224 capacity *= MMC_MAX_BLOCK_LEN; 1225 if ((capacity >> 20) > 2 * 1024) 1226 mmc->capacity_user = capacity; 1227 } 1228 1229 switch (ext_csd[EXT_CSD_REV]) { 1230 case 1: 1231 mmc->version = MMC_VERSION_4_1; 1232 break; 1233 case 2: 1234 mmc->version = MMC_VERSION_4_2; 1235 break; 1236 case 3: 1237 mmc->version = MMC_VERSION_4_3; 1238 break; 1239 case 5: 1240 mmc->version = MMC_VERSION_4_41; 1241 break; 1242 case 6: 1243 mmc->version = MMC_VERSION_4_5; 1244 break; 1245 case 7: 1246 mmc->version = MMC_VERSION_5_0; 1247 break; 1248 } 1249 1250 /* The partition data may be non-zero but it is only 1251 * effective if PARTITION_SETTING_COMPLETED is set in 1252 * EXT_CSD, so ignore any data if this bit is not set, 1253 * except for enabling the high-capacity group size 1254 * definition (see below). */ 1255 part_completed = !!(ext_csd[EXT_CSD_PARTITION_SETTING] & 1256 EXT_CSD_PARTITION_SETTING_COMPLETED); 1257 1258 /* store the partition info of emmc */ 1259 mmc->part_support = ext_csd[EXT_CSD_PARTITIONING_SUPPORT]; 1260 if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) || 1261 ext_csd[EXT_CSD_BOOT_MULT]) 1262 mmc->part_config = ext_csd[EXT_CSD_PART_CONF]; 1263 if (part_completed && 1264 (ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & ENHNCD_SUPPORT)) 1265 mmc->part_attr = ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE]; 1266 1267 mmc->capacity_boot = ext_csd[EXT_CSD_BOOT_MULT] << 17; 1268 1269 mmc->capacity_rpmb = ext_csd[EXT_CSD_RPMB_MULT] << 17; 1270 1271 for (i = 0; i < 4; i++) { 1272 int idx = EXT_CSD_GP_SIZE_MULT + i * 3; 1273 uint mult = (ext_csd[idx + 2] << 16) + 1274 (ext_csd[idx + 1] << 8) + ext_csd[idx]; 1275 if (mult) 1276 has_parts = true; 1277 if (!part_completed) 1278 continue; 1279 mmc->capacity_gp[i] = mult; 1280 mmc->capacity_gp[i] *= 1281 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]; 1282 mmc->capacity_gp[i] *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE]; 1283 mmc->capacity_gp[i] <<= 19; 1284 } 1285 1286 if (part_completed) { 1287 mmc->enh_user_size = 1288 (ext_csd[EXT_CSD_ENH_SIZE_MULT+2] << 16) + 1289 (ext_csd[EXT_CSD_ENH_SIZE_MULT+1] << 8) + 1290 ext_csd[EXT_CSD_ENH_SIZE_MULT]; 1291 mmc->enh_user_size *= ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]; 1292 mmc->enh_user_size *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE]; 1293 mmc->enh_user_size <<= 19; 1294 mmc->enh_user_start = 1295 (ext_csd[EXT_CSD_ENH_START_ADDR+3] << 24) + 1296 (ext_csd[EXT_CSD_ENH_START_ADDR+2] << 16) + 1297 (ext_csd[EXT_CSD_ENH_START_ADDR+1] << 8) + 1298 ext_csd[EXT_CSD_ENH_START_ADDR]; 1299 if (mmc->high_capacity) 1300 mmc->enh_user_start <<= 9; 1301 } 1302 1303 /* 1304 * Host needs to enable ERASE_GRP_DEF bit if device is 1305 * partitioned. This bit will be lost every time after a reset 1306 * or power off. This will affect erase size. 1307 */ 1308 if (part_completed) 1309 has_parts = true; 1310 if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) && 1311 (ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE] & PART_ENH_ATTRIB)) 1312 has_parts = true; 1313 if (has_parts) { 1314 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, 1315 EXT_CSD_ERASE_GROUP_DEF, 1); 1316 1317 if (err) 1318 return err; 1319 else 1320 ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1; 1321 } 1322 1323 if (ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01) { 1324 /* Read out group size from ext_csd */ 1325 mmc->erase_grp_size = 1326 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024; 1327 /* 1328 * if high capacity and partition setting completed 1329 * SEC_COUNT is valid even if it is smaller than 2 GiB 1330 * JEDEC Standard JESD84-B45, 6.2.4 1331 */ 1332 if (mmc->high_capacity && part_completed) { 1333 capacity = (ext_csd[EXT_CSD_SEC_CNT]) | 1334 (ext_csd[EXT_CSD_SEC_CNT + 1] << 8) | 1335 (ext_csd[EXT_CSD_SEC_CNT + 2] << 16) | 1336 (ext_csd[EXT_CSD_SEC_CNT + 3] << 24); 1337 capacity *= MMC_MAX_BLOCK_LEN; 1338 mmc->capacity_user = capacity; 1339 } 1340 } else { 1341 /* Calculate the group size from the csd value. */ 1342 int erase_gsz, erase_gmul; 1343 erase_gsz = (mmc->csd[2] & 0x00007c00) >> 10; 1344 erase_gmul = (mmc->csd[2] & 0x000003e0) >> 5; 1345 mmc->erase_grp_size = (erase_gsz + 1) 1346 * (erase_gmul + 1); 1347 } 1348 1349 mmc->hc_wp_grp_size = 1024 1350 * ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] 1351 * ext_csd[EXT_CSD_HC_WP_GRP_SIZE]; 1352 1353 mmc->wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET]; 1354 } 1355 1356 err = mmc_set_capacity(mmc, mmc->block_dev.hwpart); 1357 if (err) 1358 return err; 1359 1360 if (IS_SD(mmc)) 1361 err = sd_change_freq(mmc); 1362 else 1363 err = mmc_change_freq(mmc); 1364 1365 if (err) 1366 return err; 1367 1368 /* Restrict card's capabilities by what the host can do */ 1369 mmc->card_caps &= mmc->cfg->host_caps; 1370 1371 if (IS_SD(mmc)) { 1372 if (mmc->card_caps & MMC_MODE_4BIT) { 1373 cmd.cmdidx = MMC_CMD_APP_CMD; 1374 cmd.resp_type = MMC_RSP_R1; 1375 cmd.cmdarg = mmc->rca << 16; 1376 1377 err = mmc_send_cmd(mmc, &cmd, NULL); 1378 if (err) 1379 return err; 1380 1381 cmd.cmdidx = SD_CMD_APP_SET_BUS_WIDTH; 1382 cmd.resp_type = MMC_RSP_R1; 1383 cmd.cmdarg = 2; 1384 err = mmc_send_cmd(mmc, &cmd, NULL); 1385 if (err) 1386 return err; 1387 1388 mmc_set_bus_width(mmc, 4); 1389 } 1390 1391 if (mmc->card_caps & MMC_MODE_HS) 1392 mmc->tran_speed = 50000000; 1393 else 1394 mmc->tran_speed = 25000000; 1395 } else if (mmc->version >= MMC_VERSION_4) { 1396 /* Only version 4 of MMC supports wider bus widths */ 1397 int idx; 1398 1399 /* An array of possible bus widths in order of preference */ 1400 static unsigned ext_csd_bits[] = { 1401 EXT_CSD_DDR_BUS_WIDTH_8, 1402 EXT_CSD_DDR_BUS_WIDTH_4, 1403 EXT_CSD_BUS_WIDTH_8, 1404 EXT_CSD_BUS_WIDTH_4, 1405 EXT_CSD_BUS_WIDTH_1, 1406 }; 1407 1408 /* An array to map CSD bus widths to host cap bits */ 1409 static unsigned ext_to_hostcaps[] = { 1410 [EXT_CSD_DDR_BUS_WIDTH_4] = 1411 MMC_MODE_DDR_52MHz | MMC_MODE_4BIT, 1412 [EXT_CSD_DDR_BUS_WIDTH_8] = 1413 MMC_MODE_DDR_52MHz | MMC_MODE_8BIT, 1414 [EXT_CSD_BUS_WIDTH_4] = MMC_MODE_4BIT, 1415 [EXT_CSD_BUS_WIDTH_8] = MMC_MODE_8BIT, 1416 }; 1417 1418 /* An array to map chosen bus width to an integer */ 1419 static unsigned widths[] = { 1420 8, 4, 8, 4, 1, 1421 }; 1422 1423 for (idx=0; idx < ARRAY_SIZE(ext_csd_bits); idx++) { 1424 unsigned int extw = ext_csd_bits[idx]; 1425 unsigned int caps = ext_to_hostcaps[extw]; 1426 1427 /* 1428 * If the bus width is still not changed, 1429 * don't try to set the default again. 1430 * Otherwise, recover from switch attempts 1431 * by switching to 1-bit bus width. 1432 */ 1433 if (extw == EXT_CSD_BUS_WIDTH_1 && 1434 mmc->bus_width == 1) { 1435 err = 0; 1436 break; 1437 } 1438 1439 /* 1440 * Check to make sure the card and controller support 1441 * these capabilities 1442 */ 1443 if ((mmc->card_caps & caps) != caps) 1444 continue; 1445 1446 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, 1447 EXT_CSD_BUS_WIDTH, extw); 1448 1449 if (err) 1450 continue; 1451 1452 mmc->ddr_mode = (caps & MMC_MODE_DDR_52MHz) ? 1 : 0; 1453 mmc_set_bus_width(mmc, widths[idx]); 1454 1455 err = mmc_send_ext_csd(mmc, test_csd); 1456 1457 if (err) 1458 continue; 1459 1460 /* Only compare read only fields */ 1461 if (ext_csd[EXT_CSD_PARTITIONING_SUPPORT] 1462 == test_csd[EXT_CSD_PARTITIONING_SUPPORT] && 1463 ext_csd[EXT_CSD_HC_WP_GRP_SIZE] 1464 == test_csd[EXT_CSD_HC_WP_GRP_SIZE] && 1465 ext_csd[EXT_CSD_REV] 1466 == test_csd[EXT_CSD_REV] && 1467 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] 1468 == test_csd[EXT_CSD_HC_ERASE_GRP_SIZE] && 1469 memcmp(&ext_csd[EXT_CSD_SEC_CNT], 1470 &test_csd[EXT_CSD_SEC_CNT], 4) == 0) 1471 break; 1472 else 1473 err = SWITCH_ERR; 1474 } 1475 1476 if (err) 1477 return err; 1478 1479 if (mmc->card_caps & MMC_MODE_HS) { 1480 if (mmc->card_caps & MMC_MODE_HS_52MHz) 1481 mmc->tran_speed = 52000000; 1482 else 1483 mmc->tran_speed = 26000000; 1484 } 1485 } 1486 1487 mmc_set_clock(mmc, mmc->tran_speed); 1488 1489 /* Fix the block length for DDR mode */ 1490 if (mmc->ddr_mode) { 1491 mmc->read_bl_len = MMC_MAX_BLOCK_LEN; 1492 mmc->write_bl_len = MMC_MAX_BLOCK_LEN; 1493 } 1494 1495 /* fill in device description */ 1496 mmc->block_dev.lun = 0; 1497 mmc->block_dev.hwpart = 0; 1498 mmc->block_dev.type = 0; 1499 mmc->block_dev.blksz = mmc->read_bl_len; 1500 mmc->block_dev.log2blksz = LOG2(mmc->block_dev.blksz); 1501 mmc->block_dev.lba = lldiv(mmc->capacity, mmc->read_bl_len); 1502 #if !defined(CONFIG_SPL_BUILD) || \ 1503 (defined(CONFIG_SPL_LIBCOMMON_SUPPORT) && \ 1504 !defined(CONFIG_USE_TINY_PRINTF)) 1505 sprintf(mmc->block_dev.vendor, "Man %06x Snr %04x%04x", 1506 mmc->cid[0] >> 24, (mmc->cid[2] & 0xffff), 1507 (mmc->cid[3] >> 16) & 0xffff); 1508 sprintf(mmc->block_dev.product, "%c%c%c%c%c%c", mmc->cid[0] & 0xff, 1509 (mmc->cid[1] >> 24), (mmc->cid[1] >> 16) & 0xff, 1510 (mmc->cid[1] >> 8) & 0xff, mmc->cid[1] & 0xff, 1511 (mmc->cid[2] >> 24) & 0xff); 1512 sprintf(mmc->block_dev.revision, "%d.%d", (mmc->cid[2] >> 20) & 0xf, 1513 (mmc->cid[2] >> 16) & 0xf); 1514 #else 1515 mmc->block_dev.vendor[0] = 0; 1516 mmc->block_dev.product[0] = 0; 1517 mmc->block_dev.revision[0] = 0; 1518 #endif 1519 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBDISK_SUPPORT) 1520 part_init(&mmc->block_dev); 1521 #endif 1522 1523 return 0; 1524 } 1525 1526 static int mmc_send_if_cond(struct mmc *mmc) 1527 { 1528 struct mmc_cmd cmd; 1529 int err; 1530 1531 cmd.cmdidx = SD_CMD_SEND_IF_COND; 1532 /* We set the bit if the host supports voltages between 2.7 and 3.6 V */ 1533 cmd.cmdarg = ((mmc->cfg->voltages & 0xff8000) != 0) << 8 | 0xaa; 1534 cmd.resp_type = MMC_RSP_R7; 1535 1536 err = mmc_send_cmd(mmc, &cmd, NULL); 1537 1538 if (err) 1539 return err; 1540 1541 if ((cmd.response[0] & 0xff) != 0xaa) 1542 return UNUSABLE_ERR; 1543 else 1544 mmc->version = SD_VERSION_2; 1545 1546 return 0; 1547 } 1548 1549 /* not used any more */ 1550 int __deprecated mmc_register(struct mmc *mmc) 1551 { 1552 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) 1553 printf("%s is deprecated! use mmc_create() instead.\n", __func__); 1554 #endif 1555 return -1; 1556 } 1557 1558 struct mmc *mmc_create(const struct mmc_config *cfg, void *priv) 1559 { 1560 struct mmc *mmc; 1561 1562 /* quick validation */ 1563 if (cfg == NULL || cfg->ops == NULL || cfg->ops->send_cmd == NULL || 1564 cfg->f_min == 0 || cfg->f_max == 0 || cfg->b_max == 0) 1565 return NULL; 1566 1567 mmc = calloc(1, sizeof(*mmc)); 1568 if (mmc == NULL) 1569 return NULL; 1570 1571 mmc->cfg = cfg; 1572 mmc->priv = priv; 1573 1574 /* the following chunk was mmc_register() */ 1575 1576 /* Setup dsr related values */ 1577 mmc->dsr_imp = 0; 1578 mmc->dsr = 0xffffffff; 1579 /* Setup the universal parts of the block interface just once */ 1580 mmc->block_dev.if_type = IF_TYPE_MMC; 1581 mmc->block_dev.devnum = cur_dev_num++; 1582 mmc->block_dev.removable = 1; 1583 mmc->block_dev.block_read = mmc_bread; 1584 mmc->block_dev.block_write = mmc_bwrite; 1585 mmc->block_dev.block_erase = mmc_berase; 1586 1587 /* setup initial part type */ 1588 mmc->block_dev.part_type = mmc->cfg->part_type; 1589 1590 INIT_LIST_HEAD(&mmc->link); 1591 1592 list_add_tail(&mmc->link, &mmc_devices); 1593 1594 return mmc; 1595 } 1596 1597 void mmc_destroy(struct mmc *mmc) 1598 { 1599 /* only freeing memory for now */ 1600 free(mmc); 1601 } 1602 1603 static int mmc_get_dev(int dev, struct blk_desc **descp) 1604 { 1605 struct mmc *mmc = find_mmc_device(dev); 1606 int ret; 1607 1608 if (!mmc) 1609 return -ENODEV; 1610 ret = mmc_init(mmc); 1611 if (ret) 1612 return ret; 1613 1614 *descp = &mmc->block_dev; 1615 1616 return 0; 1617 } 1618 1619 /* board-specific MMC power initializations. */ 1620 __weak void board_mmc_power_init(void) 1621 { 1622 } 1623 1624 int mmc_start_init(struct mmc *mmc) 1625 { 1626 int err; 1627 1628 /* we pretend there's no card when init is NULL */ 1629 if (mmc_getcd(mmc) == 0 || mmc->cfg->ops->init == NULL) { 1630 mmc->has_init = 0; 1631 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) 1632 printf("MMC: no card present\n"); 1633 #endif 1634 return NO_CARD_ERR; 1635 } 1636 1637 if (mmc->has_init) 1638 return 0; 1639 1640 #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT 1641 mmc_adapter_card_type_ident(); 1642 #endif 1643 board_mmc_power_init(); 1644 1645 /* made sure it's not NULL earlier */ 1646 err = mmc->cfg->ops->init(mmc); 1647 1648 if (err) 1649 return err; 1650 1651 mmc->ddr_mode = 0; 1652 mmc_set_bus_width(mmc, 1); 1653 mmc_set_clock(mmc, 1); 1654 1655 /* Reset the Card */ 1656 err = mmc_go_idle(mmc); 1657 1658 if (err) 1659 return err; 1660 1661 /* The internal partition reset to user partition(0) at every CMD0*/ 1662 mmc->block_dev.hwpart = 0; 1663 1664 /* Test for SD version 2 */ 1665 err = mmc_send_if_cond(mmc); 1666 1667 /* Now try to get the SD card's operating condition */ 1668 err = sd_send_op_cond(mmc); 1669 1670 /* If the command timed out, we check for an MMC card */ 1671 if (err == TIMEOUT) { 1672 err = mmc_send_op_cond(mmc); 1673 1674 if (err) { 1675 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) 1676 printf("Card did not respond to voltage select!\n"); 1677 #endif 1678 return UNUSABLE_ERR; 1679 } 1680 } 1681 1682 if (!err) 1683 mmc->init_in_progress = 1; 1684 1685 return err; 1686 } 1687 1688 static int mmc_complete_init(struct mmc *mmc) 1689 { 1690 int err = 0; 1691 1692 mmc->init_in_progress = 0; 1693 if (mmc->op_cond_pending) 1694 err = mmc_complete_op_cond(mmc); 1695 1696 if (!err) 1697 err = mmc_startup(mmc); 1698 if (err) 1699 mmc->has_init = 0; 1700 else 1701 mmc->has_init = 1; 1702 return err; 1703 } 1704 1705 int mmc_init(struct mmc *mmc) 1706 { 1707 int err = 0; 1708 unsigned start; 1709 1710 if (mmc->has_init) 1711 return 0; 1712 1713 start = get_timer(0); 1714 1715 if (!mmc->init_in_progress) 1716 err = mmc_start_init(mmc); 1717 1718 if (!err) 1719 err = mmc_complete_init(mmc); 1720 debug("%s: %d, time %lu\n", __func__, err, get_timer(start)); 1721 return err; 1722 } 1723 1724 int mmc_set_dsr(struct mmc *mmc, u16 val) 1725 { 1726 mmc->dsr = val; 1727 return 0; 1728 } 1729 1730 /* CPU-specific MMC initializations */ 1731 __weak int cpu_mmc_init(bd_t *bis) 1732 { 1733 return -1; 1734 } 1735 1736 /* board-specific MMC initializations. */ 1737 __weak int board_mmc_init(bd_t *bis) 1738 { 1739 return -1; 1740 } 1741 1742 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) 1743 1744 void print_mmc_devices(char separator) 1745 { 1746 struct mmc *m; 1747 struct list_head *entry; 1748 char *mmc_type; 1749 1750 list_for_each(entry, &mmc_devices) { 1751 m = list_entry(entry, struct mmc, link); 1752 1753 if (m->has_init) 1754 mmc_type = IS_SD(m) ? "SD" : "eMMC"; 1755 else 1756 mmc_type = NULL; 1757 1758 printf("%s: %d", m->cfg->name, m->block_dev.devnum); 1759 if (mmc_type) 1760 printf(" (%s)", mmc_type); 1761 1762 if (entry->next != &mmc_devices) { 1763 printf("%c", separator); 1764 if (separator != '\n') 1765 puts (" "); 1766 } 1767 } 1768 1769 printf("\n"); 1770 } 1771 1772 #else 1773 void print_mmc_devices(char separator) { } 1774 #endif 1775 1776 int get_mmc_num(void) 1777 { 1778 return cur_dev_num; 1779 } 1780 1781 void mmc_set_preinit(struct mmc *mmc, int preinit) 1782 { 1783 mmc->preinit = preinit; 1784 } 1785 1786 static void do_preinit(void) 1787 { 1788 struct mmc *m; 1789 struct list_head *entry; 1790 1791 list_for_each(entry, &mmc_devices) { 1792 m = list_entry(entry, struct mmc, link); 1793 1794 #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT 1795 mmc_set_preinit(m, 1); 1796 #endif 1797 if (m->preinit) 1798 mmc_start_init(m); 1799 } 1800 } 1801 1802 #if defined(CONFIG_DM_MMC) && defined(CONFIG_SPL_BUILD) 1803 static int mmc_probe(bd_t *bis) 1804 { 1805 return 0; 1806 } 1807 #elif defined(CONFIG_DM_MMC) 1808 static int mmc_probe(bd_t *bis) 1809 { 1810 int ret, i; 1811 struct uclass *uc; 1812 struct udevice *dev; 1813 1814 ret = uclass_get(UCLASS_MMC, &uc); 1815 if (ret) 1816 return ret; 1817 1818 /* 1819 * Try to add them in sequence order. Really with driver model we 1820 * should allow holes, but the current MMC list does not allow that. 1821 * So if we request 0, 1, 3 we will get 0, 1, 2. 1822 */ 1823 for (i = 0; ; i++) { 1824 ret = uclass_get_device_by_seq(UCLASS_MMC, i, &dev); 1825 if (ret == -ENODEV) 1826 break; 1827 } 1828 uclass_foreach_dev(dev, uc) { 1829 ret = device_probe(dev); 1830 if (ret) 1831 printf("%s - probe failed: %d\n", dev->name, ret); 1832 } 1833 1834 return 0; 1835 } 1836 #else 1837 static int mmc_probe(bd_t *bis) 1838 { 1839 if (board_mmc_init(bis) < 0) 1840 cpu_mmc_init(bis); 1841 1842 return 0; 1843 } 1844 #endif 1845 1846 int mmc_initialize(bd_t *bis) 1847 { 1848 static int initialized = 0; 1849 int ret; 1850 if (initialized) /* Avoid initializing mmc multiple times */ 1851 return 0; 1852 initialized = 1; 1853 1854 INIT_LIST_HEAD (&mmc_devices); 1855 cur_dev_num = 0; 1856 1857 ret = mmc_probe(bis); 1858 if (ret) 1859 return ret; 1860 1861 #ifndef CONFIG_SPL_BUILD 1862 print_mmc_devices(','); 1863 #endif 1864 1865 do_preinit(); 1866 return 0; 1867 } 1868 1869 #ifdef CONFIG_SUPPORT_EMMC_BOOT 1870 /* 1871 * This function changes the size of boot partition and the size of rpmb 1872 * partition present on EMMC devices. 1873 * 1874 * Input Parameters: 1875 * struct *mmc: pointer for the mmc device strcuture 1876 * bootsize: size of boot partition 1877 * rpmbsize: size of rpmb partition 1878 * 1879 * Returns 0 on success. 1880 */ 1881 1882 int mmc_boot_partition_size_change(struct mmc *mmc, unsigned long bootsize, 1883 unsigned long rpmbsize) 1884 { 1885 int err; 1886 struct mmc_cmd cmd; 1887 1888 /* Only use this command for raw EMMC moviNAND. Enter backdoor mode */ 1889 cmd.cmdidx = MMC_CMD_RES_MAN; 1890 cmd.resp_type = MMC_RSP_R1b; 1891 cmd.cmdarg = MMC_CMD62_ARG1; 1892 1893 err = mmc_send_cmd(mmc, &cmd, NULL); 1894 if (err) { 1895 debug("mmc_boot_partition_size_change: Error1 = %d\n", err); 1896 return err; 1897 } 1898 1899 /* Boot partition changing mode */ 1900 cmd.cmdidx = MMC_CMD_RES_MAN; 1901 cmd.resp_type = MMC_RSP_R1b; 1902 cmd.cmdarg = MMC_CMD62_ARG2; 1903 1904 err = mmc_send_cmd(mmc, &cmd, NULL); 1905 if (err) { 1906 debug("mmc_boot_partition_size_change: Error2 = %d\n", err); 1907 return err; 1908 } 1909 /* boot partition size is multiple of 128KB */ 1910 bootsize = (bootsize * 1024) / 128; 1911 1912 /* Arg: boot partition size */ 1913 cmd.cmdidx = MMC_CMD_RES_MAN; 1914 cmd.resp_type = MMC_RSP_R1b; 1915 cmd.cmdarg = bootsize; 1916 1917 err = mmc_send_cmd(mmc, &cmd, NULL); 1918 if (err) { 1919 debug("mmc_boot_partition_size_change: Error3 = %d\n", err); 1920 return err; 1921 } 1922 /* RPMB partition size is multiple of 128KB */ 1923 rpmbsize = (rpmbsize * 1024) / 128; 1924 /* Arg: RPMB partition size */ 1925 cmd.cmdidx = MMC_CMD_RES_MAN; 1926 cmd.resp_type = MMC_RSP_R1b; 1927 cmd.cmdarg = rpmbsize; 1928 1929 err = mmc_send_cmd(mmc, &cmd, NULL); 1930 if (err) { 1931 debug("mmc_boot_partition_size_change: Error4 = %d\n", err); 1932 return err; 1933 } 1934 return 0; 1935 } 1936 1937 /* 1938 * Modify EXT_CSD[177] which is BOOT_BUS_WIDTH 1939 * based on the passed in values for BOOT_BUS_WIDTH, RESET_BOOT_BUS_WIDTH 1940 * and BOOT_MODE. 1941 * 1942 * Returns 0 on success. 1943 */ 1944 int mmc_set_boot_bus_width(struct mmc *mmc, u8 width, u8 reset, u8 mode) 1945 { 1946 int err; 1947 1948 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BOOT_BUS_WIDTH, 1949 EXT_CSD_BOOT_BUS_WIDTH_MODE(mode) | 1950 EXT_CSD_BOOT_BUS_WIDTH_RESET(reset) | 1951 EXT_CSD_BOOT_BUS_WIDTH_WIDTH(width)); 1952 1953 if (err) 1954 return err; 1955 return 0; 1956 } 1957 1958 /* 1959 * Modify EXT_CSD[179] which is PARTITION_CONFIG (formerly BOOT_CONFIG) 1960 * based on the passed in values for BOOT_ACK, BOOT_PARTITION_ENABLE and 1961 * PARTITION_ACCESS. 1962 * 1963 * Returns 0 on success. 1964 */ 1965 int mmc_set_part_conf(struct mmc *mmc, u8 ack, u8 part_num, u8 access) 1966 { 1967 int err; 1968 1969 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_PART_CONF, 1970 EXT_CSD_BOOT_ACK(ack) | 1971 EXT_CSD_BOOT_PART_NUM(part_num) | 1972 EXT_CSD_PARTITION_ACCESS(access)); 1973 1974 if (err) 1975 return err; 1976 return 0; 1977 } 1978 1979 /* 1980 * Modify EXT_CSD[162] which is RST_n_FUNCTION based on the given value 1981 * for enable. Note that this is a write-once field for non-zero values. 1982 * 1983 * Returns 0 on success. 1984 */ 1985 int mmc_set_rst_n_function(struct mmc *mmc, u8 enable) 1986 { 1987 return mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_RST_N_FUNCTION, 1988 enable); 1989 } 1990 #endif 1991 1992 U_BOOT_LEGACY_BLK(mmc) = { 1993 .if_typename = "mmc", 1994 .if_type = IF_TYPE_MMC, 1995 .max_devs = -1, 1996 .get_dev = mmc_get_dev, 1997 .select_hwpart = mmc_select_hwpartp, 1998 }; 1999