1 /* 2 * Copyright 2008, Freescale Semiconductor, Inc 3 * Andy Fleming 4 * 5 * Based vaguely on the Linux code 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #include <config.h> 11 #include <common.h> 12 #include <command.h> 13 #include <dm.h> 14 #include <dm/device-internal.h> 15 #include <errno.h> 16 #include <mmc.h> 17 #include <part.h> 18 #include <malloc.h> 19 #include <memalign.h> 20 #include <linux/list.h> 21 #include <div64.h> 22 #include "mmc_private.h" 23 24 __weak int board_mmc_getwp(struct mmc *mmc) 25 { 26 return -1; 27 } 28 29 int mmc_getwp(struct mmc *mmc) 30 { 31 int wp; 32 33 wp = board_mmc_getwp(mmc); 34 35 if (wp < 0) { 36 if (mmc->cfg->ops->getwp) 37 wp = mmc->cfg->ops->getwp(mmc); 38 else 39 wp = 0; 40 } 41 42 return wp; 43 } 44 45 __weak int board_mmc_getcd(struct mmc *mmc) 46 { 47 return -1; 48 } 49 50 #ifdef CONFIG_MMC_TRACE 51 void mmmc_trace_before_send(struct mmc *mmc, struct mmc_cmd *cmd) 52 { 53 printf("CMD_SEND:%d\n", cmd->cmdidx); 54 printf("\t\tARG\t\t\t 0x%08X\n", cmd->cmdarg); 55 } 56 57 void mmmc_trace_after_send(struct mmc *mmc, struct mmc_cmd *cmd, int ret) 58 { 59 int i; 60 u8 *ptr; 61 62 if (ret) { 63 printf("\t\tRET\t\t\t %d\n", ret); 64 } else { 65 switch (cmd->resp_type) { 66 case MMC_RSP_NONE: 67 printf("\t\tMMC_RSP_NONE\n"); 68 break; 69 case MMC_RSP_R1: 70 printf("\t\tMMC_RSP_R1,5,6,7 \t 0x%08X \n", 71 cmd->response[0]); 72 break; 73 case MMC_RSP_R1b: 74 printf("\t\tMMC_RSP_R1b\t\t 0x%08X \n", 75 cmd->response[0]); 76 break; 77 case MMC_RSP_R2: 78 printf("\t\tMMC_RSP_R2\t\t 0x%08X \n", 79 cmd->response[0]); 80 printf("\t\t \t\t 0x%08X \n", 81 cmd->response[1]); 82 printf("\t\t \t\t 0x%08X \n", 83 cmd->response[2]); 84 printf("\t\t \t\t 0x%08X \n", 85 cmd->response[3]); 86 printf("\n"); 87 printf("\t\t\t\t\tDUMPING DATA\n"); 88 for (i = 0; i < 4; i++) { 89 int j; 90 printf("\t\t\t\t\t%03d - ", i*4); 91 ptr = (u8 *)&cmd->response[i]; 92 ptr += 3; 93 for (j = 0; j < 4; j++) 94 printf("%02X ", *ptr--); 95 printf("\n"); 96 } 97 break; 98 case MMC_RSP_R3: 99 printf("\t\tMMC_RSP_R3,4\t\t 0x%08X \n", 100 cmd->response[0]); 101 break; 102 default: 103 printf("\t\tERROR MMC rsp not supported\n"); 104 break; 105 } 106 } 107 } 108 109 void mmc_trace_state(struct mmc *mmc, struct mmc_cmd *cmd) 110 { 111 int status; 112 113 status = (cmd->response[0] & MMC_STATUS_CURR_STATE) >> 9; 114 printf("CURR STATE:%d\n", status); 115 } 116 #endif 117 118 int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) 119 { 120 int ret; 121 122 mmmc_trace_before_send(mmc, cmd); 123 ret = mmc->cfg->ops->send_cmd(mmc, cmd, data); 124 mmmc_trace_after_send(mmc, cmd, ret); 125 126 return ret; 127 } 128 129 int mmc_send_status(struct mmc *mmc, int timeout) 130 { 131 struct mmc_cmd cmd; 132 int err, retries = 5; 133 134 cmd.cmdidx = MMC_CMD_SEND_STATUS; 135 cmd.resp_type = MMC_RSP_R1; 136 if (!mmc_host_is_spi(mmc)) 137 cmd.cmdarg = mmc->rca << 16; 138 139 while (1) { 140 err = mmc_send_cmd(mmc, &cmd, NULL); 141 if (!err) { 142 if ((cmd.response[0] & MMC_STATUS_RDY_FOR_DATA) && 143 (cmd.response[0] & MMC_STATUS_CURR_STATE) != 144 MMC_STATE_PRG) 145 break; 146 else if (cmd.response[0] & MMC_STATUS_MASK) { 147 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) 148 printf("Status Error: 0x%08X\n", 149 cmd.response[0]); 150 #endif 151 return COMM_ERR; 152 } 153 } else if (--retries < 0) 154 return err; 155 156 if (timeout-- <= 0) 157 break; 158 159 udelay(1000); 160 } 161 162 mmc_trace_state(mmc, &cmd); 163 if (timeout <= 0) { 164 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) 165 printf("Timeout waiting card ready\n"); 166 #endif 167 return TIMEOUT; 168 } 169 170 return 0; 171 } 172 173 int mmc_set_blocklen(struct mmc *mmc, int len) 174 { 175 struct mmc_cmd cmd; 176 177 if (mmc->ddr_mode) 178 return 0; 179 180 cmd.cmdidx = MMC_CMD_SET_BLOCKLEN; 181 cmd.resp_type = MMC_RSP_R1; 182 cmd.cmdarg = len; 183 184 return mmc_send_cmd(mmc, &cmd, NULL); 185 } 186 187 static int mmc_read_blocks(struct mmc *mmc, void *dst, lbaint_t start, 188 lbaint_t blkcnt) 189 { 190 struct mmc_cmd cmd; 191 struct mmc_data data; 192 193 if (blkcnt > 1) 194 cmd.cmdidx = MMC_CMD_READ_MULTIPLE_BLOCK; 195 else 196 cmd.cmdidx = MMC_CMD_READ_SINGLE_BLOCK; 197 198 if (mmc->high_capacity) 199 cmd.cmdarg = start; 200 else 201 cmd.cmdarg = start * mmc->read_bl_len; 202 203 cmd.resp_type = MMC_RSP_R1; 204 205 data.dest = dst; 206 data.blocks = blkcnt; 207 data.blocksize = mmc->read_bl_len; 208 data.flags = MMC_DATA_READ; 209 210 if (mmc_send_cmd(mmc, &cmd, &data)) 211 return 0; 212 213 if (blkcnt > 1) { 214 cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION; 215 cmd.cmdarg = 0; 216 cmd.resp_type = MMC_RSP_R1b; 217 if (mmc_send_cmd(mmc, &cmd, NULL)) { 218 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) 219 printf("mmc fail to send stop cmd\n"); 220 #endif 221 return 0; 222 } 223 } 224 225 return blkcnt; 226 } 227 228 #ifdef CONFIG_BLK 229 ulong mmc_bread(struct udevice *dev, lbaint_t start, lbaint_t blkcnt, void *dst) 230 #else 231 ulong mmc_bread(struct blk_desc *block_dev, lbaint_t start, lbaint_t blkcnt, 232 void *dst) 233 #endif 234 { 235 #ifdef CONFIG_BLK 236 struct blk_desc *block_dev = dev_get_uclass_platdata(dev); 237 #endif 238 int dev_num = block_dev->devnum; 239 int err; 240 lbaint_t cur, blocks_todo = blkcnt; 241 242 if (blkcnt == 0) 243 return 0; 244 245 struct mmc *mmc = find_mmc_device(dev_num); 246 if (!mmc) 247 return 0; 248 249 err = blk_dselect_hwpart(block_dev, block_dev->hwpart); 250 if (err < 0) 251 return 0; 252 253 if ((start + blkcnt) > block_dev->lba) { 254 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) 255 printf("MMC: block number 0x" LBAF " exceeds max(0x" LBAF ")\n", 256 start + blkcnt, block_dev->lba); 257 #endif 258 return 0; 259 } 260 261 if (mmc_set_blocklen(mmc, mmc->read_bl_len)) { 262 debug("%s: Failed to set blocklen\n", __func__); 263 return 0; 264 } 265 266 do { 267 cur = (blocks_todo > mmc->cfg->b_max) ? 268 mmc->cfg->b_max : blocks_todo; 269 if (mmc_read_blocks(mmc, dst, start, cur) != cur) { 270 debug("%s: Failed to read blocks\n", __func__); 271 return 0; 272 } 273 blocks_todo -= cur; 274 start += cur; 275 dst += cur * mmc->read_bl_len; 276 } while (blocks_todo > 0); 277 278 return blkcnt; 279 } 280 281 static int mmc_go_idle(struct mmc *mmc) 282 { 283 struct mmc_cmd cmd; 284 int err; 285 286 udelay(1000); 287 288 cmd.cmdidx = MMC_CMD_GO_IDLE_STATE; 289 cmd.cmdarg = 0; 290 cmd.resp_type = MMC_RSP_NONE; 291 292 err = mmc_send_cmd(mmc, &cmd, NULL); 293 294 if (err) 295 return err; 296 297 udelay(2000); 298 299 return 0; 300 } 301 302 static int sd_send_op_cond(struct mmc *mmc) 303 { 304 int timeout = 1000; 305 int err; 306 struct mmc_cmd cmd; 307 308 while (1) { 309 cmd.cmdidx = MMC_CMD_APP_CMD; 310 cmd.resp_type = MMC_RSP_R1; 311 cmd.cmdarg = 0; 312 313 err = mmc_send_cmd(mmc, &cmd, NULL); 314 315 if (err) 316 return err; 317 318 cmd.cmdidx = SD_CMD_APP_SEND_OP_COND; 319 cmd.resp_type = MMC_RSP_R3; 320 321 /* 322 * Most cards do not answer if some reserved bits 323 * in the ocr are set. However, Some controller 324 * can set bit 7 (reserved for low voltages), but 325 * how to manage low voltages SD card is not yet 326 * specified. 327 */ 328 cmd.cmdarg = mmc_host_is_spi(mmc) ? 0 : 329 (mmc->cfg->voltages & 0xff8000); 330 331 if (mmc->version == SD_VERSION_2) 332 cmd.cmdarg |= OCR_HCS; 333 334 err = mmc_send_cmd(mmc, &cmd, NULL); 335 336 if (err) 337 return err; 338 339 if (cmd.response[0] & OCR_BUSY) 340 break; 341 342 if (timeout-- <= 0) 343 return UNUSABLE_ERR; 344 345 udelay(1000); 346 } 347 348 if (mmc->version != SD_VERSION_2) 349 mmc->version = SD_VERSION_1_0; 350 351 if (mmc_host_is_spi(mmc)) { /* read OCR for spi */ 352 cmd.cmdidx = MMC_CMD_SPI_READ_OCR; 353 cmd.resp_type = MMC_RSP_R3; 354 cmd.cmdarg = 0; 355 356 err = mmc_send_cmd(mmc, &cmd, NULL); 357 358 if (err) 359 return err; 360 } 361 362 mmc->ocr = cmd.response[0]; 363 364 mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS); 365 mmc->rca = 0; 366 367 return 0; 368 } 369 370 static int mmc_send_op_cond_iter(struct mmc *mmc, int use_arg) 371 { 372 struct mmc_cmd cmd; 373 int err; 374 375 cmd.cmdidx = MMC_CMD_SEND_OP_COND; 376 cmd.resp_type = MMC_RSP_R3; 377 cmd.cmdarg = 0; 378 if (use_arg && !mmc_host_is_spi(mmc)) 379 cmd.cmdarg = OCR_HCS | 380 (mmc->cfg->voltages & 381 (mmc->ocr & OCR_VOLTAGE_MASK)) | 382 (mmc->ocr & OCR_ACCESS_MODE); 383 384 err = mmc_send_cmd(mmc, &cmd, NULL); 385 if (err) 386 return err; 387 mmc->ocr = cmd.response[0]; 388 return 0; 389 } 390 391 static int mmc_send_op_cond(struct mmc *mmc) 392 { 393 int err, i; 394 395 /* Some cards seem to need this */ 396 mmc_go_idle(mmc); 397 398 /* Asking to the card its capabilities */ 399 for (i = 0; i < 2; i++) { 400 err = mmc_send_op_cond_iter(mmc, i != 0); 401 if (err) 402 return err; 403 404 /* exit if not busy (flag seems to be inverted) */ 405 if (mmc->ocr & OCR_BUSY) 406 break; 407 } 408 mmc->op_cond_pending = 1; 409 return 0; 410 } 411 412 static int mmc_complete_op_cond(struct mmc *mmc) 413 { 414 struct mmc_cmd cmd; 415 int timeout = 1000; 416 uint start; 417 int err; 418 419 mmc->op_cond_pending = 0; 420 if (!(mmc->ocr & OCR_BUSY)) { 421 start = get_timer(0); 422 while (1) { 423 err = mmc_send_op_cond_iter(mmc, 1); 424 if (err) 425 return err; 426 if (mmc->ocr & OCR_BUSY) 427 break; 428 if (get_timer(start) > timeout) 429 return UNUSABLE_ERR; 430 udelay(100); 431 } 432 } 433 434 if (mmc_host_is_spi(mmc)) { /* read OCR for spi */ 435 cmd.cmdidx = MMC_CMD_SPI_READ_OCR; 436 cmd.resp_type = MMC_RSP_R3; 437 cmd.cmdarg = 0; 438 439 err = mmc_send_cmd(mmc, &cmd, NULL); 440 441 if (err) 442 return err; 443 444 mmc->ocr = cmd.response[0]; 445 } 446 447 mmc->version = MMC_VERSION_UNKNOWN; 448 449 mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS); 450 mmc->rca = 1; 451 452 return 0; 453 } 454 455 456 static int mmc_send_ext_csd(struct mmc *mmc, u8 *ext_csd) 457 { 458 struct mmc_cmd cmd; 459 struct mmc_data data; 460 int err; 461 462 /* Get the Card Status Register */ 463 cmd.cmdidx = MMC_CMD_SEND_EXT_CSD; 464 cmd.resp_type = MMC_RSP_R1; 465 cmd.cmdarg = 0; 466 467 data.dest = (char *)ext_csd; 468 data.blocks = 1; 469 data.blocksize = MMC_MAX_BLOCK_LEN; 470 data.flags = MMC_DATA_READ; 471 472 err = mmc_send_cmd(mmc, &cmd, &data); 473 474 return err; 475 } 476 477 int mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value) 478 { 479 struct mmc_cmd cmd; 480 int timeout = 1000; 481 int ret; 482 483 cmd.cmdidx = MMC_CMD_SWITCH; 484 cmd.resp_type = MMC_RSP_R1b; 485 cmd.cmdarg = (MMC_SWITCH_MODE_WRITE_BYTE << 24) | 486 (index << 16) | 487 (value << 8); 488 489 ret = mmc_send_cmd(mmc, &cmd, NULL); 490 491 /* Waiting for the ready status */ 492 if (!ret) 493 ret = mmc_send_status(mmc, timeout); 494 495 return ret; 496 497 } 498 499 static int mmc_change_freq(struct mmc *mmc) 500 { 501 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN); 502 char cardtype; 503 int err; 504 505 mmc->card_caps = 0; 506 507 if (mmc_host_is_spi(mmc)) 508 return 0; 509 510 /* Only version 4 supports high-speed */ 511 if (mmc->version < MMC_VERSION_4) 512 return 0; 513 514 mmc->card_caps |= MMC_MODE_4BIT | MMC_MODE_8BIT; 515 516 err = mmc_send_ext_csd(mmc, ext_csd); 517 518 if (err) 519 return err; 520 521 cardtype = ext_csd[EXT_CSD_CARD_TYPE] & 0xf; 522 523 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_HS_TIMING, 1); 524 525 if (err) 526 return err; 527 528 /* Now check to see that it worked */ 529 err = mmc_send_ext_csd(mmc, ext_csd); 530 531 if (err) 532 return err; 533 534 /* No high-speed support */ 535 if (!ext_csd[EXT_CSD_HS_TIMING]) 536 return 0; 537 538 /* High Speed is set, there are two types: 52MHz and 26MHz */ 539 if (cardtype & EXT_CSD_CARD_TYPE_52) { 540 if (cardtype & EXT_CSD_CARD_TYPE_DDR_1_8V) 541 mmc->card_caps |= MMC_MODE_DDR_52MHz; 542 mmc->card_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS; 543 } else { 544 mmc->card_caps |= MMC_MODE_HS; 545 } 546 547 return 0; 548 } 549 550 static int mmc_set_capacity(struct mmc *mmc, int part_num) 551 { 552 switch (part_num) { 553 case 0: 554 mmc->capacity = mmc->capacity_user; 555 break; 556 case 1: 557 case 2: 558 mmc->capacity = mmc->capacity_boot; 559 break; 560 case 3: 561 mmc->capacity = mmc->capacity_rpmb; 562 break; 563 case 4: 564 case 5: 565 case 6: 566 case 7: 567 mmc->capacity = mmc->capacity_gp[part_num - 4]; 568 break; 569 default: 570 return -1; 571 } 572 573 mmc_get_blk_desc(mmc)->lba = lldiv(mmc->capacity, mmc->read_bl_len); 574 575 return 0; 576 } 577 578 int mmc_switch_part(struct mmc *mmc, unsigned int part_num) 579 { 580 int ret; 581 582 ret = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_PART_CONF, 583 (mmc->part_config & ~PART_ACCESS_MASK) 584 | (part_num & PART_ACCESS_MASK)); 585 586 /* 587 * Set the capacity if the switch succeeded or was intended 588 * to return to representing the raw device. 589 */ 590 if ((ret == 0) || ((ret == -ENODEV) && (part_num == 0))) { 591 ret = mmc_set_capacity(mmc, part_num); 592 mmc_get_blk_desc(mmc)->hwpart = part_num; 593 } 594 595 return ret; 596 } 597 598 int mmc_hwpart_config(struct mmc *mmc, 599 const struct mmc_hwpart_conf *conf, 600 enum mmc_hwpart_conf_mode mode) 601 { 602 u8 part_attrs = 0; 603 u32 enh_size_mult; 604 u32 enh_start_addr; 605 u32 gp_size_mult[4]; 606 u32 max_enh_size_mult; 607 u32 tot_enh_size_mult = 0; 608 u8 wr_rel_set; 609 int i, pidx, err; 610 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN); 611 612 if (mode < MMC_HWPART_CONF_CHECK || mode > MMC_HWPART_CONF_COMPLETE) 613 return -EINVAL; 614 615 if (IS_SD(mmc) || (mmc->version < MMC_VERSION_4_41)) { 616 printf("eMMC >= 4.4 required for enhanced user data area\n"); 617 return -EMEDIUMTYPE; 618 } 619 620 if (!(mmc->part_support & PART_SUPPORT)) { 621 printf("Card does not support partitioning\n"); 622 return -EMEDIUMTYPE; 623 } 624 625 if (!mmc->hc_wp_grp_size) { 626 printf("Card does not define HC WP group size\n"); 627 return -EMEDIUMTYPE; 628 } 629 630 /* check partition alignment and total enhanced size */ 631 if (conf->user.enh_size) { 632 if (conf->user.enh_size % mmc->hc_wp_grp_size || 633 conf->user.enh_start % mmc->hc_wp_grp_size) { 634 printf("User data enhanced area not HC WP group " 635 "size aligned\n"); 636 return -EINVAL; 637 } 638 part_attrs |= EXT_CSD_ENH_USR; 639 enh_size_mult = conf->user.enh_size / mmc->hc_wp_grp_size; 640 if (mmc->high_capacity) { 641 enh_start_addr = conf->user.enh_start; 642 } else { 643 enh_start_addr = (conf->user.enh_start << 9); 644 } 645 } else { 646 enh_size_mult = 0; 647 enh_start_addr = 0; 648 } 649 tot_enh_size_mult += enh_size_mult; 650 651 for (pidx = 0; pidx < 4; pidx++) { 652 if (conf->gp_part[pidx].size % mmc->hc_wp_grp_size) { 653 printf("GP%i partition not HC WP group size " 654 "aligned\n", pidx+1); 655 return -EINVAL; 656 } 657 gp_size_mult[pidx] = conf->gp_part[pidx].size / mmc->hc_wp_grp_size; 658 if (conf->gp_part[pidx].size && conf->gp_part[pidx].enhanced) { 659 part_attrs |= EXT_CSD_ENH_GP(pidx); 660 tot_enh_size_mult += gp_size_mult[pidx]; 661 } 662 } 663 664 if (part_attrs && ! (mmc->part_support & ENHNCD_SUPPORT)) { 665 printf("Card does not support enhanced attribute\n"); 666 return -EMEDIUMTYPE; 667 } 668 669 err = mmc_send_ext_csd(mmc, ext_csd); 670 if (err) 671 return err; 672 673 max_enh_size_mult = 674 (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+2] << 16) + 675 (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+1] << 8) + 676 ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT]; 677 if (tot_enh_size_mult > max_enh_size_mult) { 678 printf("Total enhanced size exceeds maximum (%u > %u)\n", 679 tot_enh_size_mult, max_enh_size_mult); 680 return -EMEDIUMTYPE; 681 } 682 683 /* The default value of EXT_CSD_WR_REL_SET is device 684 * dependent, the values can only be changed if the 685 * EXT_CSD_HS_CTRL_REL bit is set. The values can be 686 * changed only once and before partitioning is completed. */ 687 wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET]; 688 if (conf->user.wr_rel_change) { 689 if (conf->user.wr_rel_set) 690 wr_rel_set |= EXT_CSD_WR_DATA_REL_USR; 691 else 692 wr_rel_set &= ~EXT_CSD_WR_DATA_REL_USR; 693 } 694 for (pidx = 0; pidx < 4; pidx++) { 695 if (conf->gp_part[pidx].wr_rel_change) { 696 if (conf->gp_part[pidx].wr_rel_set) 697 wr_rel_set |= EXT_CSD_WR_DATA_REL_GP(pidx); 698 else 699 wr_rel_set &= ~EXT_CSD_WR_DATA_REL_GP(pidx); 700 } 701 } 702 703 if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET] && 704 !(ext_csd[EXT_CSD_WR_REL_PARAM] & EXT_CSD_HS_CTRL_REL)) { 705 puts("Card does not support host controlled partition write " 706 "reliability settings\n"); 707 return -EMEDIUMTYPE; 708 } 709 710 if (ext_csd[EXT_CSD_PARTITION_SETTING] & 711 EXT_CSD_PARTITION_SETTING_COMPLETED) { 712 printf("Card already partitioned\n"); 713 return -EPERM; 714 } 715 716 if (mode == MMC_HWPART_CONF_CHECK) 717 return 0; 718 719 /* Partitioning requires high-capacity size definitions */ 720 if (!(ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01)) { 721 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, 722 EXT_CSD_ERASE_GROUP_DEF, 1); 723 724 if (err) 725 return err; 726 727 ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1; 728 729 /* update erase group size to be high-capacity */ 730 mmc->erase_grp_size = 731 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024; 732 733 } 734 735 /* all OK, write the configuration */ 736 for (i = 0; i < 4; i++) { 737 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, 738 EXT_CSD_ENH_START_ADDR+i, 739 (enh_start_addr >> (i*8)) & 0xFF); 740 if (err) 741 return err; 742 } 743 for (i = 0; i < 3; i++) { 744 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, 745 EXT_CSD_ENH_SIZE_MULT+i, 746 (enh_size_mult >> (i*8)) & 0xFF); 747 if (err) 748 return err; 749 } 750 for (pidx = 0; pidx < 4; pidx++) { 751 for (i = 0; i < 3; i++) { 752 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, 753 EXT_CSD_GP_SIZE_MULT+pidx*3+i, 754 (gp_size_mult[pidx] >> (i*8)) & 0xFF); 755 if (err) 756 return err; 757 } 758 } 759 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, 760 EXT_CSD_PARTITIONS_ATTRIBUTE, part_attrs); 761 if (err) 762 return err; 763 764 if (mode == MMC_HWPART_CONF_SET) 765 return 0; 766 767 /* The WR_REL_SET is a write-once register but shall be 768 * written before setting PART_SETTING_COMPLETED. As it is 769 * write-once we can only write it when completing the 770 * partitioning. */ 771 if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET]) { 772 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, 773 EXT_CSD_WR_REL_SET, wr_rel_set); 774 if (err) 775 return err; 776 } 777 778 /* Setting PART_SETTING_COMPLETED confirms the partition 779 * configuration but it only becomes effective after power 780 * cycle, so we do not adjust the partition related settings 781 * in the mmc struct. */ 782 783 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, 784 EXT_CSD_PARTITION_SETTING, 785 EXT_CSD_PARTITION_SETTING_COMPLETED); 786 if (err) 787 return err; 788 789 return 0; 790 } 791 792 int mmc_getcd(struct mmc *mmc) 793 { 794 int cd; 795 796 cd = board_mmc_getcd(mmc); 797 798 if (cd < 0) { 799 if (mmc->cfg->ops->getcd) 800 cd = mmc->cfg->ops->getcd(mmc); 801 else 802 cd = 1; 803 } 804 805 return cd; 806 } 807 808 static int sd_switch(struct mmc *mmc, int mode, int group, u8 value, u8 *resp) 809 { 810 struct mmc_cmd cmd; 811 struct mmc_data data; 812 813 /* Switch the frequency */ 814 cmd.cmdidx = SD_CMD_SWITCH_FUNC; 815 cmd.resp_type = MMC_RSP_R1; 816 cmd.cmdarg = (mode << 31) | 0xffffff; 817 cmd.cmdarg &= ~(0xf << (group * 4)); 818 cmd.cmdarg |= value << (group * 4); 819 820 data.dest = (char *)resp; 821 data.blocksize = 64; 822 data.blocks = 1; 823 data.flags = MMC_DATA_READ; 824 825 return mmc_send_cmd(mmc, &cmd, &data); 826 } 827 828 829 static int sd_change_freq(struct mmc *mmc) 830 { 831 int err; 832 struct mmc_cmd cmd; 833 ALLOC_CACHE_ALIGN_BUFFER(uint, scr, 2); 834 ALLOC_CACHE_ALIGN_BUFFER(uint, switch_status, 16); 835 struct mmc_data data; 836 int timeout; 837 838 mmc->card_caps = 0; 839 840 if (mmc_host_is_spi(mmc)) 841 return 0; 842 843 /* Read the SCR to find out if this card supports higher speeds */ 844 cmd.cmdidx = MMC_CMD_APP_CMD; 845 cmd.resp_type = MMC_RSP_R1; 846 cmd.cmdarg = mmc->rca << 16; 847 848 err = mmc_send_cmd(mmc, &cmd, NULL); 849 850 if (err) 851 return err; 852 853 cmd.cmdidx = SD_CMD_APP_SEND_SCR; 854 cmd.resp_type = MMC_RSP_R1; 855 cmd.cmdarg = 0; 856 857 timeout = 3; 858 859 retry_scr: 860 data.dest = (char *)scr; 861 data.blocksize = 8; 862 data.blocks = 1; 863 data.flags = MMC_DATA_READ; 864 865 err = mmc_send_cmd(mmc, &cmd, &data); 866 867 if (err) { 868 if (timeout--) 869 goto retry_scr; 870 871 return err; 872 } 873 874 mmc->scr[0] = __be32_to_cpu(scr[0]); 875 mmc->scr[1] = __be32_to_cpu(scr[1]); 876 877 switch ((mmc->scr[0] >> 24) & 0xf) { 878 case 0: 879 mmc->version = SD_VERSION_1_0; 880 break; 881 case 1: 882 mmc->version = SD_VERSION_1_10; 883 break; 884 case 2: 885 mmc->version = SD_VERSION_2; 886 if ((mmc->scr[0] >> 15) & 0x1) 887 mmc->version = SD_VERSION_3; 888 break; 889 default: 890 mmc->version = SD_VERSION_1_0; 891 break; 892 } 893 894 if (mmc->scr[0] & SD_DATA_4BIT) 895 mmc->card_caps |= MMC_MODE_4BIT; 896 897 /* Version 1.0 doesn't support switching */ 898 if (mmc->version == SD_VERSION_1_0) 899 return 0; 900 901 timeout = 4; 902 while (timeout--) { 903 err = sd_switch(mmc, SD_SWITCH_CHECK, 0, 1, 904 (u8 *)switch_status); 905 906 if (err) 907 return err; 908 909 /* The high-speed function is busy. Try again */ 910 if (!(__be32_to_cpu(switch_status[7]) & SD_HIGHSPEED_BUSY)) 911 break; 912 } 913 914 /* If high-speed isn't supported, we return */ 915 if (!(__be32_to_cpu(switch_status[3]) & SD_HIGHSPEED_SUPPORTED)) 916 return 0; 917 918 /* 919 * If the host doesn't support SD_HIGHSPEED, do not switch card to 920 * HIGHSPEED mode even if the card support SD_HIGHSPPED. 921 * This can avoid furthur problem when the card runs in different 922 * mode between the host. 923 */ 924 if (!((mmc->cfg->host_caps & MMC_MODE_HS_52MHz) && 925 (mmc->cfg->host_caps & MMC_MODE_HS))) 926 return 0; 927 928 err = sd_switch(mmc, SD_SWITCH_SWITCH, 0, 1, (u8 *)switch_status); 929 930 if (err) 931 return err; 932 933 if ((__be32_to_cpu(switch_status[4]) & 0x0f000000) == 0x01000000) 934 mmc->card_caps |= MMC_MODE_HS; 935 936 return 0; 937 } 938 939 /* frequency bases */ 940 /* divided by 10 to be nice to platforms without floating point */ 941 static const int fbase[] = { 942 10000, 943 100000, 944 1000000, 945 10000000, 946 }; 947 948 /* Multiplier values for TRAN_SPEED. Multiplied by 10 to be nice 949 * to platforms without floating point. 950 */ 951 static const u8 multipliers[] = { 952 0, /* reserved */ 953 10, 954 12, 955 13, 956 15, 957 20, 958 25, 959 30, 960 35, 961 40, 962 45, 963 50, 964 55, 965 60, 966 70, 967 80, 968 }; 969 970 static void mmc_set_ios(struct mmc *mmc) 971 { 972 if (mmc->cfg->ops->set_ios) 973 mmc->cfg->ops->set_ios(mmc); 974 } 975 976 void mmc_set_clock(struct mmc *mmc, uint clock) 977 { 978 if (clock > mmc->cfg->f_max) 979 clock = mmc->cfg->f_max; 980 981 if (clock < mmc->cfg->f_min) 982 clock = mmc->cfg->f_min; 983 984 mmc->clock = clock; 985 986 mmc_set_ios(mmc); 987 } 988 989 static void mmc_set_bus_width(struct mmc *mmc, uint width) 990 { 991 mmc->bus_width = width; 992 993 mmc_set_ios(mmc); 994 } 995 996 static int mmc_startup(struct mmc *mmc) 997 { 998 int err, i; 999 uint mult, freq; 1000 u64 cmult, csize, capacity; 1001 struct mmc_cmd cmd; 1002 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN); 1003 ALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, MMC_MAX_BLOCK_LEN); 1004 int timeout = 1000; 1005 bool has_parts = false; 1006 bool part_completed; 1007 struct blk_desc *bdesc; 1008 1009 #ifdef CONFIG_MMC_SPI_CRC_ON 1010 if (mmc_host_is_spi(mmc)) { /* enable CRC check for spi */ 1011 cmd.cmdidx = MMC_CMD_SPI_CRC_ON_OFF; 1012 cmd.resp_type = MMC_RSP_R1; 1013 cmd.cmdarg = 1; 1014 err = mmc_send_cmd(mmc, &cmd, NULL); 1015 1016 if (err) 1017 return err; 1018 } 1019 #endif 1020 1021 /* Put the Card in Identify Mode */ 1022 cmd.cmdidx = mmc_host_is_spi(mmc) ? MMC_CMD_SEND_CID : 1023 MMC_CMD_ALL_SEND_CID; /* cmd not supported in spi */ 1024 cmd.resp_type = MMC_RSP_R2; 1025 cmd.cmdarg = 0; 1026 1027 err = mmc_send_cmd(mmc, &cmd, NULL); 1028 1029 if (err) 1030 return err; 1031 1032 memcpy(mmc->cid, cmd.response, 16); 1033 1034 /* 1035 * For MMC cards, set the Relative Address. 1036 * For SD cards, get the Relatvie Address. 1037 * This also puts the cards into Standby State 1038 */ 1039 if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */ 1040 cmd.cmdidx = SD_CMD_SEND_RELATIVE_ADDR; 1041 cmd.cmdarg = mmc->rca << 16; 1042 cmd.resp_type = MMC_RSP_R6; 1043 1044 err = mmc_send_cmd(mmc, &cmd, NULL); 1045 1046 if (err) 1047 return err; 1048 1049 if (IS_SD(mmc)) 1050 mmc->rca = (cmd.response[0] >> 16) & 0xffff; 1051 } 1052 1053 /* Get the Card-Specific Data */ 1054 cmd.cmdidx = MMC_CMD_SEND_CSD; 1055 cmd.resp_type = MMC_RSP_R2; 1056 cmd.cmdarg = mmc->rca << 16; 1057 1058 err = mmc_send_cmd(mmc, &cmd, NULL); 1059 1060 /* Waiting for the ready status */ 1061 mmc_send_status(mmc, timeout); 1062 1063 if (err) 1064 return err; 1065 1066 mmc->csd[0] = cmd.response[0]; 1067 mmc->csd[1] = cmd.response[1]; 1068 mmc->csd[2] = cmd.response[2]; 1069 mmc->csd[3] = cmd.response[3]; 1070 1071 if (mmc->version == MMC_VERSION_UNKNOWN) { 1072 int version = (cmd.response[0] >> 26) & 0xf; 1073 1074 switch (version) { 1075 case 0: 1076 mmc->version = MMC_VERSION_1_2; 1077 break; 1078 case 1: 1079 mmc->version = MMC_VERSION_1_4; 1080 break; 1081 case 2: 1082 mmc->version = MMC_VERSION_2_2; 1083 break; 1084 case 3: 1085 mmc->version = MMC_VERSION_3; 1086 break; 1087 case 4: 1088 mmc->version = MMC_VERSION_4; 1089 break; 1090 default: 1091 mmc->version = MMC_VERSION_1_2; 1092 break; 1093 } 1094 } 1095 1096 /* divide frequency by 10, since the mults are 10x bigger */ 1097 freq = fbase[(cmd.response[0] & 0x7)]; 1098 mult = multipliers[((cmd.response[0] >> 3) & 0xf)]; 1099 1100 mmc->tran_speed = freq * mult; 1101 1102 mmc->dsr_imp = ((cmd.response[1] >> 12) & 0x1); 1103 mmc->read_bl_len = 1 << ((cmd.response[1] >> 16) & 0xf); 1104 1105 if (IS_SD(mmc)) 1106 mmc->write_bl_len = mmc->read_bl_len; 1107 else 1108 mmc->write_bl_len = 1 << ((cmd.response[3] >> 22) & 0xf); 1109 1110 if (mmc->high_capacity) { 1111 csize = (mmc->csd[1] & 0x3f) << 16 1112 | (mmc->csd[2] & 0xffff0000) >> 16; 1113 cmult = 8; 1114 } else { 1115 csize = (mmc->csd[1] & 0x3ff) << 2 1116 | (mmc->csd[2] & 0xc0000000) >> 30; 1117 cmult = (mmc->csd[2] & 0x00038000) >> 15; 1118 } 1119 1120 mmc->capacity_user = (csize + 1) << (cmult + 2); 1121 mmc->capacity_user *= mmc->read_bl_len; 1122 mmc->capacity_boot = 0; 1123 mmc->capacity_rpmb = 0; 1124 for (i = 0; i < 4; i++) 1125 mmc->capacity_gp[i] = 0; 1126 1127 if (mmc->read_bl_len > MMC_MAX_BLOCK_LEN) 1128 mmc->read_bl_len = MMC_MAX_BLOCK_LEN; 1129 1130 if (mmc->write_bl_len > MMC_MAX_BLOCK_LEN) 1131 mmc->write_bl_len = MMC_MAX_BLOCK_LEN; 1132 1133 if ((mmc->dsr_imp) && (0xffffffff != mmc->dsr)) { 1134 cmd.cmdidx = MMC_CMD_SET_DSR; 1135 cmd.cmdarg = (mmc->dsr & 0xffff) << 16; 1136 cmd.resp_type = MMC_RSP_NONE; 1137 if (mmc_send_cmd(mmc, &cmd, NULL)) 1138 printf("MMC: SET_DSR failed\n"); 1139 } 1140 1141 /* Select the card, and put it into Transfer Mode */ 1142 if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */ 1143 cmd.cmdidx = MMC_CMD_SELECT_CARD; 1144 cmd.resp_type = MMC_RSP_R1; 1145 cmd.cmdarg = mmc->rca << 16; 1146 err = mmc_send_cmd(mmc, &cmd, NULL); 1147 1148 if (err) 1149 return err; 1150 } 1151 1152 /* 1153 * For SD, its erase group is always one sector 1154 */ 1155 mmc->erase_grp_size = 1; 1156 mmc->part_config = MMCPART_NOAVAILABLE; 1157 if (!IS_SD(mmc) && (mmc->version >= MMC_VERSION_4)) { 1158 /* check ext_csd version and capacity */ 1159 err = mmc_send_ext_csd(mmc, ext_csd); 1160 if (err) 1161 return err; 1162 if (ext_csd[EXT_CSD_REV] >= 2) { 1163 /* 1164 * According to the JEDEC Standard, the value of 1165 * ext_csd's capacity is valid if the value is more 1166 * than 2GB 1167 */ 1168 capacity = ext_csd[EXT_CSD_SEC_CNT] << 0 1169 | ext_csd[EXT_CSD_SEC_CNT + 1] << 8 1170 | ext_csd[EXT_CSD_SEC_CNT + 2] << 16 1171 | ext_csd[EXT_CSD_SEC_CNT + 3] << 24; 1172 capacity *= MMC_MAX_BLOCK_LEN; 1173 if ((capacity >> 20) > 2 * 1024) 1174 mmc->capacity_user = capacity; 1175 } 1176 1177 switch (ext_csd[EXT_CSD_REV]) { 1178 case 1: 1179 mmc->version = MMC_VERSION_4_1; 1180 break; 1181 case 2: 1182 mmc->version = MMC_VERSION_4_2; 1183 break; 1184 case 3: 1185 mmc->version = MMC_VERSION_4_3; 1186 break; 1187 case 5: 1188 mmc->version = MMC_VERSION_4_41; 1189 break; 1190 case 6: 1191 mmc->version = MMC_VERSION_4_5; 1192 break; 1193 case 7: 1194 mmc->version = MMC_VERSION_5_0; 1195 break; 1196 case 8: 1197 mmc->version = MMC_VERSION_5_1; 1198 break; 1199 } 1200 1201 /* The partition data may be non-zero but it is only 1202 * effective if PARTITION_SETTING_COMPLETED is set in 1203 * EXT_CSD, so ignore any data if this bit is not set, 1204 * except for enabling the high-capacity group size 1205 * definition (see below). */ 1206 part_completed = !!(ext_csd[EXT_CSD_PARTITION_SETTING] & 1207 EXT_CSD_PARTITION_SETTING_COMPLETED); 1208 1209 /* store the partition info of emmc */ 1210 mmc->part_support = ext_csd[EXT_CSD_PARTITIONING_SUPPORT]; 1211 if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) || 1212 ext_csd[EXT_CSD_BOOT_MULT]) 1213 mmc->part_config = ext_csd[EXT_CSD_PART_CONF]; 1214 if (part_completed && 1215 (ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & ENHNCD_SUPPORT)) 1216 mmc->part_attr = ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE]; 1217 1218 mmc->capacity_boot = ext_csd[EXT_CSD_BOOT_MULT] << 17; 1219 1220 mmc->capacity_rpmb = ext_csd[EXT_CSD_RPMB_MULT] << 17; 1221 1222 for (i = 0; i < 4; i++) { 1223 int idx = EXT_CSD_GP_SIZE_MULT + i * 3; 1224 uint mult = (ext_csd[idx + 2] << 16) + 1225 (ext_csd[idx + 1] << 8) + ext_csd[idx]; 1226 if (mult) 1227 has_parts = true; 1228 if (!part_completed) 1229 continue; 1230 mmc->capacity_gp[i] = mult; 1231 mmc->capacity_gp[i] *= 1232 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]; 1233 mmc->capacity_gp[i] *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE]; 1234 mmc->capacity_gp[i] <<= 19; 1235 } 1236 1237 if (part_completed) { 1238 mmc->enh_user_size = 1239 (ext_csd[EXT_CSD_ENH_SIZE_MULT+2] << 16) + 1240 (ext_csd[EXT_CSD_ENH_SIZE_MULT+1] << 8) + 1241 ext_csd[EXT_CSD_ENH_SIZE_MULT]; 1242 mmc->enh_user_size *= ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]; 1243 mmc->enh_user_size *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE]; 1244 mmc->enh_user_size <<= 19; 1245 mmc->enh_user_start = 1246 (ext_csd[EXT_CSD_ENH_START_ADDR+3] << 24) + 1247 (ext_csd[EXT_CSD_ENH_START_ADDR+2] << 16) + 1248 (ext_csd[EXT_CSD_ENH_START_ADDR+1] << 8) + 1249 ext_csd[EXT_CSD_ENH_START_ADDR]; 1250 if (mmc->high_capacity) 1251 mmc->enh_user_start <<= 9; 1252 } 1253 1254 /* 1255 * Host needs to enable ERASE_GRP_DEF bit if device is 1256 * partitioned. This bit will be lost every time after a reset 1257 * or power off. This will affect erase size. 1258 */ 1259 if (part_completed) 1260 has_parts = true; 1261 if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) && 1262 (ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE] & PART_ENH_ATTRIB)) 1263 has_parts = true; 1264 if (has_parts) { 1265 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, 1266 EXT_CSD_ERASE_GROUP_DEF, 1); 1267 1268 if (err) 1269 return err; 1270 else 1271 ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1; 1272 } 1273 1274 if (ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01) { 1275 /* Read out group size from ext_csd */ 1276 mmc->erase_grp_size = 1277 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024; 1278 /* 1279 * if high capacity and partition setting completed 1280 * SEC_COUNT is valid even if it is smaller than 2 GiB 1281 * JEDEC Standard JESD84-B45, 6.2.4 1282 */ 1283 if (mmc->high_capacity && part_completed) { 1284 capacity = (ext_csd[EXT_CSD_SEC_CNT]) | 1285 (ext_csd[EXT_CSD_SEC_CNT + 1] << 8) | 1286 (ext_csd[EXT_CSD_SEC_CNT + 2] << 16) | 1287 (ext_csd[EXT_CSD_SEC_CNT + 3] << 24); 1288 capacity *= MMC_MAX_BLOCK_LEN; 1289 mmc->capacity_user = capacity; 1290 } 1291 } else { 1292 /* Calculate the group size from the csd value. */ 1293 int erase_gsz, erase_gmul; 1294 erase_gsz = (mmc->csd[2] & 0x00007c00) >> 10; 1295 erase_gmul = (mmc->csd[2] & 0x000003e0) >> 5; 1296 mmc->erase_grp_size = (erase_gsz + 1) 1297 * (erase_gmul + 1); 1298 } 1299 1300 mmc->hc_wp_grp_size = 1024 1301 * ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] 1302 * ext_csd[EXT_CSD_HC_WP_GRP_SIZE]; 1303 1304 mmc->wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET]; 1305 } 1306 1307 err = mmc_set_capacity(mmc, mmc_get_blk_desc(mmc)->hwpart); 1308 if (err) 1309 return err; 1310 1311 if (IS_SD(mmc)) 1312 err = sd_change_freq(mmc); 1313 else 1314 err = mmc_change_freq(mmc); 1315 1316 if (err) 1317 return err; 1318 1319 /* Restrict card's capabilities by what the host can do */ 1320 mmc->card_caps &= mmc->cfg->host_caps; 1321 1322 if (IS_SD(mmc)) { 1323 if (mmc->card_caps & MMC_MODE_4BIT) { 1324 cmd.cmdidx = MMC_CMD_APP_CMD; 1325 cmd.resp_type = MMC_RSP_R1; 1326 cmd.cmdarg = mmc->rca << 16; 1327 1328 err = mmc_send_cmd(mmc, &cmd, NULL); 1329 if (err) 1330 return err; 1331 1332 cmd.cmdidx = SD_CMD_APP_SET_BUS_WIDTH; 1333 cmd.resp_type = MMC_RSP_R1; 1334 cmd.cmdarg = 2; 1335 err = mmc_send_cmd(mmc, &cmd, NULL); 1336 if (err) 1337 return err; 1338 1339 mmc_set_bus_width(mmc, 4); 1340 } 1341 1342 if (mmc->card_caps & MMC_MODE_HS) 1343 mmc->tran_speed = 50000000; 1344 else 1345 mmc->tran_speed = 25000000; 1346 } else if (mmc->version >= MMC_VERSION_4) { 1347 /* Only version 4 of MMC supports wider bus widths */ 1348 int idx; 1349 1350 /* An array of possible bus widths in order of preference */ 1351 static unsigned ext_csd_bits[] = { 1352 EXT_CSD_DDR_BUS_WIDTH_8, 1353 EXT_CSD_DDR_BUS_WIDTH_4, 1354 EXT_CSD_BUS_WIDTH_8, 1355 EXT_CSD_BUS_WIDTH_4, 1356 EXT_CSD_BUS_WIDTH_1, 1357 }; 1358 1359 /* An array to map CSD bus widths to host cap bits */ 1360 static unsigned ext_to_hostcaps[] = { 1361 [EXT_CSD_DDR_BUS_WIDTH_4] = 1362 MMC_MODE_DDR_52MHz | MMC_MODE_4BIT, 1363 [EXT_CSD_DDR_BUS_WIDTH_8] = 1364 MMC_MODE_DDR_52MHz | MMC_MODE_8BIT, 1365 [EXT_CSD_BUS_WIDTH_4] = MMC_MODE_4BIT, 1366 [EXT_CSD_BUS_WIDTH_8] = MMC_MODE_8BIT, 1367 }; 1368 1369 /* An array to map chosen bus width to an integer */ 1370 static unsigned widths[] = { 1371 8, 4, 8, 4, 1, 1372 }; 1373 1374 for (idx=0; idx < ARRAY_SIZE(ext_csd_bits); idx++) { 1375 unsigned int extw = ext_csd_bits[idx]; 1376 unsigned int caps = ext_to_hostcaps[extw]; 1377 1378 /* 1379 * If the bus width is still not changed, 1380 * don't try to set the default again. 1381 * Otherwise, recover from switch attempts 1382 * by switching to 1-bit bus width. 1383 */ 1384 if (extw == EXT_CSD_BUS_WIDTH_1 && 1385 mmc->bus_width == 1) { 1386 err = 0; 1387 break; 1388 } 1389 1390 /* 1391 * Check to make sure the card and controller support 1392 * these capabilities 1393 */ 1394 if ((mmc->card_caps & caps) != caps) 1395 continue; 1396 1397 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, 1398 EXT_CSD_BUS_WIDTH, extw); 1399 1400 if (err) 1401 continue; 1402 1403 mmc->ddr_mode = (caps & MMC_MODE_DDR_52MHz) ? 1 : 0; 1404 mmc_set_bus_width(mmc, widths[idx]); 1405 1406 err = mmc_send_ext_csd(mmc, test_csd); 1407 1408 if (err) 1409 continue; 1410 1411 /* Only compare read only fields */ 1412 if (ext_csd[EXT_CSD_PARTITIONING_SUPPORT] 1413 == test_csd[EXT_CSD_PARTITIONING_SUPPORT] && 1414 ext_csd[EXT_CSD_HC_WP_GRP_SIZE] 1415 == test_csd[EXT_CSD_HC_WP_GRP_SIZE] && 1416 ext_csd[EXT_CSD_REV] 1417 == test_csd[EXT_CSD_REV] && 1418 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] 1419 == test_csd[EXT_CSD_HC_ERASE_GRP_SIZE] && 1420 memcmp(&ext_csd[EXT_CSD_SEC_CNT], 1421 &test_csd[EXT_CSD_SEC_CNT], 4) == 0) 1422 break; 1423 else 1424 err = SWITCH_ERR; 1425 } 1426 1427 if (err) 1428 return err; 1429 1430 if (mmc->card_caps & MMC_MODE_HS) { 1431 if (mmc->card_caps & MMC_MODE_HS_52MHz) 1432 mmc->tran_speed = 52000000; 1433 else 1434 mmc->tran_speed = 26000000; 1435 } 1436 } 1437 1438 mmc_set_clock(mmc, mmc->tran_speed); 1439 1440 /* Fix the block length for DDR mode */ 1441 if (mmc->ddr_mode) { 1442 mmc->read_bl_len = MMC_MAX_BLOCK_LEN; 1443 mmc->write_bl_len = MMC_MAX_BLOCK_LEN; 1444 } 1445 1446 /* fill in device description */ 1447 bdesc = mmc_get_blk_desc(mmc); 1448 bdesc->lun = 0; 1449 bdesc->hwpart = 0; 1450 bdesc->type = 0; 1451 bdesc->blksz = mmc->read_bl_len; 1452 bdesc->log2blksz = LOG2(bdesc->blksz); 1453 bdesc->lba = lldiv(mmc->capacity, mmc->read_bl_len); 1454 #if !defined(CONFIG_SPL_BUILD) || \ 1455 (defined(CONFIG_SPL_LIBCOMMON_SUPPORT) && \ 1456 !defined(CONFIG_USE_TINY_PRINTF)) 1457 sprintf(bdesc->vendor, "Man %06x Snr %04x%04x", 1458 mmc->cid[0] >> 24, (mmc->cid[2] & 0xffff), 1459 (mmc->cid[3] >> 16) & 0xffff); 1460 sprintf(bdesc->product, "%c%c%c%c%c%c", mmc->cid[0] & 0xff, 1461 (mmc->cid[1] >> 24), (mmc->cid[1] >> 16) & 0xff, 1462 (mmc->cid[1] >> 8) & 0xff, mmc->cid[1] & 0xff, 1463 (mmc->cid[2] >> 24) & 0xff); 1464 sprintf(bdesc->revision, "%d.%d", (mmc->cid[2] >> 20) & 0xf, 1465 (mmc->cid[2] >> 16) & 0xf); 1466 #else 1467 bdesc->vendor[0] = 0; 1468 bdesc->product[0] = 0; 1469 bdesc->revision[0] = 0; 1470 #endif 1471 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBDISK_SUPPORT) 1472 part_init(bdesc); 1473 #endif 1474 1475 return 0; 1476 } 1477 1478 static int mmc_send_if_cond(struct mmc *mmc) 1479 { 1480 struct mmc_cmd cmd; 1481 int err; 1482 1483 cmd.cmdidx = SD_CMD_SEND_IF_COND; 1484 /* We set the bit if the host supports voltages between 2.7 and 3.6 V */ 1485 cmd.cmdarg = ((mmc->cfg->voltages & 0xff8000) != 0) << 8 | 0xaa; 1486 cmd.resp_type = MMC_RSP_R7; 1487 1488 err = mmc_send_cmd(mmc, &cmd, NULL); 1489 1490 if (err) 1491 return err; 1492 1493 if ((cmd.response[0] & 0xff) != 0xaa) 1494 return UNUSABLE_ERR; 1495 else 1496 mmc->version = SD_VERSION_2; 1497 1498 return 0; 1499 } 1500 1501 /* board-specific MMC power initializations. */ 1502 __weak void board_mmc_power_init(void) 1503 { 1504 } 1505 1506 int mmc_start_init(struct mmc *mmc) 1507 { 1508 int err; 1509 1510 /* we pretend there's no card when init is NULL */ 1511 if (mmc_getcd(mmc) == 0 || mmc->cfg->ops->init == NULL) { 1512 mmc->has_init = 0; 1513 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) 1514 printf("MMC: no card present\n"); 1515 #endif 1516 return NO_CARD_ERR; 1517 } 1518 1519 if (mmc->has_init) 1520 return 0; 1521 1522 #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT 1523 mmc_adapter_card_type_ident(); 1524 #endif 1525 board_mmc_power_init(); 1526 1527 /* made sure it's not NULL earlier */ 1528 err = mmc->cfg->ops->init(mmc); 1529 1530 if (err) 1531 return err; 1532 1533 mmc->ddr_mode = 0; 1534 mmc_set_bus_width(mmc, 1); 1535 mmc_set_clock(mmc, 1); 1536 1537 /* Reset the Card */ 1538 err = mmc_go_idle(mmc); 1539 1540 if (err) 1541 return err; 1542 1543 /* The internal partition reset to user partition(0) at every CMD0*/ 1544 mmc_get_blk_desc(mmc)->hwpart = 0; 1545 1546 /* Test for SD version 2 */ 1547 err = mmc_send_if_cond(mmc); 1548 1549 /* Now try to get the SD card's operating condition */ 1550 err = sd_send_op_cond(mmc); 1551 1552 /* If the command timed out, we check for an MMC card */ 1553 if (err == TIMEOUT) { 1554 err = mmc_send_op_cond(mmc); 1555 1556 if (err) { 1557 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) 1558 printf("Card did not respond to voltage select!\n"); 1559 #endif 1560 return UNUSABLE_ERR; 1561 } 1562 } 1563 1564 if (!err) 1565 mmc->init_in_progress = 1; 1566 1567 return err; 1568 } 1569 1570 static int mmc_complete_init(struct mmc *mmc) 1571 { 1572 int err = 0; 1573 1574 mmc->init_in_progress = 0; 1575 if (mmc->op_cond_pending) 1576 err = mmc_complete_op_cond(mmc); 1577 1578 if (!err) 1579 err = mmc_startup(mmc); 1580 if (err) 1581 mmc->has_init = 0; 1582 else 1583 mmc->has_init = 1; 1584 return err; 1585 } 1586 1587 int mmc_init(struct mmc *mmc) 1588 { 1589 int err = 0; 1590 unsigned start; 1591 #ifdef CONFIG_DM_MMC 1592 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(mmc->dev); 1593 1594 upriv->mmc = mmc; 1595 #endif 1596 if (mmc->has_init) 1597 return 0; 1598 1599 start = get_timer(0); 1600 1601 if (!mmc->init_in_progress) 1602 err = mmc_start_init(mmc); 1603 1604 if (!err) 1605 err = mmc_complete_init(mmc); 1606 debug("%s: %d, time %lu\n", __func__, err, get_timer(start)); 1607 return err; 1608 } 1609 1610 int mmc_set_dsr(struct mmc *mmc, u16 val) 1611 { 1612 mmc->dsr = val; 1613 return 0; 1614 } 1615 1616 /* CPU-specific MMC initializations */ 1617 __weak int cpu_mmc_init(bd_t *bis) 1618 { 1619 return -1; 1620 } 1621 1622 /* board-specific MMC initializations. */ 1623 __weak int board_mmc_init(bd_t *bis) 1624 { 1625 return -1; 1626 } 1627 1628 void mmc_set_preinit(struct mmc *mmc, int preinit) 1629 { 1630 mmc->preinit = preinit; 1631 } 1632 1633 #if defined(CONFIG_DM_MMC) && defined(CONFIG_SPL_BUILD) 1634 static int mmc_probe(bd_t *bis) 1635 { 1636 return 0; 1637 } 1638 #elif defined(CONFIG_DM_MMC) 1639 static int mmc_probe(bd_t *bis) 1640 { 1641 int ret, i; 1642 struct uclass *uc; 1643 struct udevice *dev; 1644 1645 ret = uclass_get(UCLASS_MMC, &uc); 1646 if (ret) 1647 return ret; 1648 1649 /* 1650 * Try to add them in sequence order. Really with driver model we 1651 * should allow holes, but the current MMC list does not allow that. 1652 * So if we request 0, 1, 3 we will get 0, 1, 2. 1653 */ 1654 for (i = 0; ; i++) { 1655 ret = uclass_get_device_by_seq(UCLASS_MMC, i, &dev); 1656 if (ret == -ENODEV) 1657 break; 1658 } 1659 uclass_foreach_dev(dev, uc) { 1660 ret = device_probe(dev); 1661 if (ret) 1662 printf("%s - probe failed: %d\n", dev->name, ret); 1663 } 1664 1665 return 0; 1666 } 1667 #else 1668 static int mmc_probe(bd_t *bis) 1669 { 1670 if (board_mmc_init(bis) < 0) 1671 cpu_mmc_init(bis); 1672 1673 return 0; 1674 } 1675 #endif 1676 1677 int mmc_initialize(bd_t *bis) 1678 { 1679 static int initialized = 0; 1680 int ret; 1681 if (initialized) /* Avoid initializing mmc multiple times */ 1682 return 0; 1683 initialized = 1; 1684 1685 #ifndef CONFIG_BLK 1686 mmc_list_init(); 1687 #endif 1688 ret = mmc_probe(bis); 1689 if (ret) 1690 return ret; 1691 1692 #ifndef CONFIG_SPL_BUILD 1693 print_mmc_devices(','); 1694 #endif 1695 1696 mmc_do_preinit(); 1697 return 0; 1698 } 1699