1 /* 2 * Copyright 2008, Freescale Semiconductor, Inc 3 * Andy Fleming 4 * 5 * Based vaguely on the Linux code 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #include <config.h> 11 #include <common.h> 12 #include <command.h> 13 #include <errno.h> 14 #include <mmc.h> 15 #include <part.h> 16 #include <malloc.h> 17 #include <linux/list.h> 18 #include <div64.h> 19 #include "mmc_private.h" 20 21 static struct list_head mmc_devices; 22 static int cur_dev_num = -1; 23 24 __weak int board_mmc_getwp(struct mmc *mmc) 25 { 26 return -1; 27 } 28 29 int mmc_getwp(struct mmc *mmc) 30 { 31 int wp; 32 33 wp = board_mmc_getwp(mmc); 34 35 if (wp < 0) { 36 if (mmc->cfg->ops->getwp) 37 wp = mmc->cfg->ops->getwp(mmc); 38 else 39 wp = 0; 40 } 41 42 return wp; 43 } 44 45 __weak int board_mmc_getcd(struct mmc *mmc) 46 { 47 return -1; 48 } 49 50 int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) 51 { 52 int ret; 53 54 #ifdef CONFIG_MMC_TRACE 55 int i; 56 u8 *ptr; 57 58 printf("CMD_SEND:%d\n", cmd->cmdidx); 59 printf("\t\tARG\t\t\t 0x%08X\n", cmd->cmdarg); 60 ret = mmc->cfg->ops->send_cmd(mmc, cmd, data); 61 switch (cmd->resp_type) { 62 case MMC_RSP_NONE: 63 printf("\t\tMMC_RSP_NONE\n"); 64 break; 65 case MMC_RSP_R1: 66 printf("\t\tMMC_RSP_R1,5,6,7 \t 0x%08X \n", 67 cmd->response[0]); 68 break; 69 case MMC_RSP_R1b: 70 printf("\t\tMMC_RSP_R1b\t\t 0x%08X \n", 71 cmd->response[0]); 72 break; 73 case MMC_RSP_R2: 74 printf("\t\tMMC_RSP_R2\t\t 0x%08X \n", 75 cmd->response[0]); 76 printf("\t\t \t\t 0x%08X \n", 77 cmd->response[1]); 78 printf("\t\t \t\t 0x%08X \n", 79 cmd->response[2]); 80 printf("\t\t \t\t 0x%08X \n", 81 cmd->response[3]); 82 printf("\n"); 83 printf("\t\t\t\t\tDUMPING DATA\n"); 84 for (i = 0; i < 4; i++) { 85 int j; 86 printf("\t\t\t\t\t%03d - ", i*4); 87 ptr = (u8 *)&cmd->response[i]; 88 ptr += 3; 89 for (j = 0; j < 4; j++) 90 printf("%02X ", *ptr--); 91 printf("\n"); 92 } 93 break; 94 case MMC_RSP_R3: 95 printf("\t\tMMC_RSP_R3,4\t\t 0x%08X \n", 96 cmd->response[0]); 97 break; 98 default: 99 printf("\t\tERROR MMC rsp not supported\n"); 100 break; 101 } 102 #else 103 ret = mmc->cfg->ops->send_cmd(mmc, cmd, data); 104 #endif 105 return ret; 106 } 107 108 int mmc_send_status(struct mmc *mmc, int timeout) 109 { 110 struct mmc_cmd cmd; 111 int err, retries = 5; 112 #ifdef CONFIG_MMC_TRACE 113 int status; 114 #endif 115 116 cmd.cmdidx = MMC_CMD_SEND_STATUS; 117 cmd.resp_type = MMC_RSP_R1; 118 if (!mmc_host_is_spi(mmc)) 119 cmd.cmdarg = mmc->rca << 16; 120 121 do { 122 err = mmc_send_cmd(mmc, &cmd, NULL); 123 if (!err) { 124 if ((cmd.response[0] & MMC_STATUS_RDY_FOR_DATA) && 125 (cmd.response[0] & MMC_STATUS_CURR_STATE) != 126 MMC_STATE_PRG) 127 break; 128 else if (cmd.response[0] & MMC_STATUS_MASK) { 129 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) 130 printf("Status Error: 0x%08X\n", 131 cmd.response[0]); 132 #endif 133 return COMM_ERR; 134 } 135 } else if (--retries < 0) 136 return err; 137 138 udelay(1000); 139 140 } while (timeout--); 141 142 #ifdef CONFIG_MMC_TRACE 143 status = (cmd.response[0] & MMC_STATUS_CURR_STATE) >> 9; 144 printf("CURR STATE:%d\n", status); 145 #endif 146 if (timeout <= 0) { 147 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) 148 printf("Timeout waiting card ready\n"); 149 #endif 150 return TIMEOUT; 151 } 152 if (cmd.response[0] & MMC_STATUS_SWITCH_ERROR) 153 return SWITCH_ERR; 154 155 return 0; 156 } 157 158 int mmc_set_blocklen(struct mmc *mmc, int len) 159 { 160 struct mmc_cmd cmd; 161 162 if (mmc->ddr_mode) 163 return 0; 164 165 cmd.cmdidx = MMC_CMD_SET_BLOCKLEN; 166 cmd.resp_type = MMC_RSP_R1; 167 cmd.cmdarg = len; 168 169 return mmc_send_cmd(mmc, &cmd, NULL); 170 } 171 172 struct mmc *find_mmc_device(int dev_num) 173 { 174 struct mmc *m; 175 struct list_head *entry; 176 177 list_for_each(entry, &mmc_devices) { 178 m = list_entry(entry, struct mmc, link); 179 180 if (m->block_dev.dev == dev_num) 181 return m; 182 } 183 184 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) 185 printf("MMC Device %d not found\n", dev_num); 186 #endif 187 188 return NULL; 189 } 190 191 static int mmc_read_blocks(struct mmc *mmc, void *dst, lbaint_t start, 192 lbaint_t blkcnt) 193 { 194 struct mmc_cmd cmd; 195 struct mmc_data data; 196 197 if (blkcnt > 1) 198 cmd.cmdidx = MMC_CMD_READ_MULTIPLE_BLOCK; 199 else 200 cmd.cmdidx = MMC_CMD_READ_SINGLE_BLOCK; 201 202 if (mmc->high_capacity) 203 cmd.cmdarg = start; 204 else 205 cmd.cmdarg = start * mmc->read_bl_len; 206 207 cmd.resp_type = MMC_RSP_R1; 208 209 data.dest = dst; 210 data.blocks = blkcnt; 211 data.blocksize = mmc->read_bl_len; 212 data.flags = MMC_DATA_READ; 213 214 if (mmc_send_cmd(mmc, &cmd, &data)) 215 return 0; 216 217 if (blkcnt > 1) { 218 cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION; 219 cmd.cmdarg = 0; 220 cmd.resp_type = MMC_RSP_R1b; 221 if (mmc_send_cmd(mmc, &cmd, NULL)) { 222 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) 223 printf("mmc fail to send stop cmd\n"); 224 #endif 225 return 0; 226 } 227 } 228 229 return blkcnt; 230 } 231 232 static ulong mmc_bread(int dev_num, lbaint_t start, lbaint_t blkcnt, void *dst) 233 { 234 lbaint_t cur, blocks_todo = blkcnt; 235 236 if (blkcnt == 0) 237 return 0; 238 239 struct mmc *mmc = find_mmc_device(dev_num); 240 if (!mmc) 241 return 0; 242 243 if ((start + blkcnt) > mmc->block_dev.lba) { 244 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) 245 printf("MMC: block number 0x" LBAF " exceeds max(0x" LBAF ")\n", 246 start + blkcnt, mmc->block_dev.lba); 247 #endif 248 return 0; 249 } 250 251 if (mmc_set_blocklen(mmc, mmc->read_bl_len)) 252 return 0; 253 254 do { 255 cur = (blocks_todo > mmc->cfg->b_max) ? 256 mmc->cfg->b_max : blocks_todo; 257 if(mmc_read_blocks(mmc, dst, start, cur) != cur) 258 return 0; 259 blocks_todo -= cur; 260 start += cur; 261 dst += cur * mmc->read_bl_len; 262 } while (blocks_todo > 0); 263 264 return blkcnt; 265 } 266 267 static int mmc_go_idle(struct mmc *mmc) 268 { 269 struct mmc_cmd cmd; 270 int err; 271 272 udelay(1000); 273 274 cmd.cmdidx = MMC_CMD_GO_IDLE_STATE; 275 cmd.cmdarg = 0; 276 cmd.resp_type = MMC_RSP_NONE; 277 278 err = mmc_send_cmd(mmc, &cmd, NULL); 279 280 if (err) 281 return err; 282 283 udelay(2000); 284 285 return 0; 286 } 287 288 static int sd_send_op_cond(struct mmc *mmc) 289 { 290 int timeout = 1000; 291 int err; 292 struct mmc_cmd cmd; 293 294 do { 295 cmd.cmdidx = MMC_CMD_APP_CMD; 296 cmd.resp_type = MMC_RSP_R1; 297 cmd.cmdarg = 0; 298 299 err = mmc_send_cmd(mmc, &cmd, NULL); 300 301 if (err) 302 return err; 303 304 cmd.cmdidx = SD_CMD_APP_SEND_OP_COND; 305 cmd.resp_type = MMC_RSP_R3; 306 307 /* 308 * Most cards do not answer if some reserved bits 309 * in the ocr are set. However, Some controller 310 * can set bit 7 (reserved for low voltages), but 311 * how to manage low voltages SD card is not yet 312 * specified. 313 */ 314 cmd.cmdarg = mmc_host_is_spi(mmc) ? 0 : 315 (mmc->cfg->voltages & 0xff8000); 316 317 if (mmc->version == SD_VERSION_2) 318 cmd.cmdarg |= OCR_HCS; 319 320 err = mmc_send_cmd(mmc, &cmd, NULL); 321 322 if (err) 323 return err; 324 325 udelay(1000); 326 } while ((!(cmd.response[0] & OCR_BUSY)) && timeout--); 327 328 if (timeout <= 0) 329 return UNUSABLE_ERR; 330 331 if (mmc->version != SD_VERSION_2) 332 mmc->version = SD_VERSION_1_0; 333 334 if (mmc_host_is_spi(mmc)) { /* read OCR for spi */ 335 cmd.cmdidx = MMC_CMD_SPI_READ_OCR; 336 cmd.resp_type = MMC_RSP_R3; 337 cmd.cmdarg = 0; 338 339 err = mmc_send_cmd(mmc, &cmd, NULL); 340 341 if (err) 342 return err; 343 } 344 345 mmc->ocr = cmd.response[0]; 346 347 mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS); 348 mmc->rca = 0; 349 350 return 0; 351 } 352 353 /* We pass in the cmd since otherwise the init seems to fail */ 354 static int mmc_send_op_cond_iter(struct mmc *mmc, struct mmc_cmd *cmd, 355 int use_arg) 356 { 357 int err; 358 359 cmd->cmdidx = MMC_CMD_SEND_OP_COND; 360 cmd->resp_type = MMC_RSP_R3; 361 cmd->cmdarg = 0; 362 if (use_arg && !mmc_host_is_spi(mmc)) { 363 cmd->cmdarg = 364 (mmc->cfg->voltages & 365 (mmc->op_cond_response & OCR_VOLTAGE_MASK)) | 366 (mmc->op_cond_response & OCR_ACCESS_MODE); 367 368 if (mmc->cfg->host_caps & MMC_MODE_HC) 369 cmd->cmdarg |= OCR_HCS; 370 } 371 err = mmc_send_cmd(mmc, cmd, NULL); 372 if (err) 373 return err; 374 mmc->op_cond_response = cmd->response[0]; 375 return 0; 376 } 377 378 static int mmc_send_op_cond(struct mmc *mmc) 379 { 380 struct mmc_cmd cmd; 381 int err, i; 382 383 /* Some cards seem to need this */ 384 mmc_go_idle(mmc); 385 386 /* Asking to the card its capabilities */ 387 mmc->op_cond_pending = 1; 388 for (i = 0; i < 2; i++) { 389 err = mmc_send_op_cond_iter(mmc, &cmd, i != 0); 390 if (err) 391 return err; 392 393 /* exit if not busy (flag seems to be inverted) */ 394 if (mmc->op_cond_response & OCR_BUSY) 395 return 0; 396 } 397 return IN_PROGRESS; 398 } 399 400 static int mmc_complete_op_cond(struct mmc *mmc) 401 { 402 struct mmc_cmd cmd; 403 int timeout = 1000; 404 uint start; 405 int err; 406 407 mmc->op_cond_pending = 0; 408 start = get_timer(0); 409 do { 410 err = mmc_send_op_cond_iter(mmc, &cmd, 1); 411 if (err) 412 return err; 413 if (get_timer(start) > timeout) 414 return UNUSABLE_ERR; 415 udelay(100); 416 } while (!(mmc->op_cond_response & OCR_BUSY)); 417 418 if (mmc_host_is_spi(mmc)) { /* read OCR for spi */ 419 cmd.cmdidx = MMC_CMD_SPI_READ_OCR; 420 cmd.resp_type = MMC_RSP_R3; 421 cmd.cmdarg = 0; 422 423 err = mmc_send_cmd(mmc, &cmd, NULL); 424 425 if (err) 426 return err; 427 } 428 429 mmc->version = MMC_VERSION_UNKNOWN; 430 mmc->ocr = cmd.response[0]; 431 432 mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS); 433 mmc->rca = 1; 434 435 return 0; 436 } 437 438 439 static int mmc_send_ext_csd(struct mmc *mmc, u8 *ext_csd) 440 { 441 struct mmc_cmd cmd; 442 struct mmc_data data; 443 int err; 444 445 /* Get the Card Status Register */ 446 cmd.cmdidx = MMC_CMD_SEND_EXT_CSD; 447 cmd.resp_type = MMC_RSP_R1; 448 cmd.cmdarg = 0; 449 450 data.dest = (char *)ext_csd; 451 data.blocks = 1; 452 data.blocksize = MMC_MAX_BLOCK_LEN; 453 data.flags = MMC_DATA_READ; 454 455 err = mmc_send_cmd(mmc, &cmd, &data); 456 457 return err; 458 } 459 460 461 static int mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value) 462 { 463 struct mmc_cmd cmd; 464 int timeout = 1000; 465 int ret; 466 467 cmd.cmdidx = MMC_CMD_SWITCH; 468 cmd.resp_type = MMC_RSP_R1b; 469 cmd.cmdarg = (MMC_SWITCH_MODE_WRITE_BYTE << 24) | 470 (index << 16) | 471 (value << 8); 472 473 ret = mmc_send_cmd(mmc, &cmd, NULL); 474 475 /* Waiting for the ready status */ 476 if (!ret) 477 ret = mmc_send_status(mmc, timeout); 478 479 return ret; 480 481 } 482 483 static int mmc_change_freq(struct mmc *mmc) 484 { 485 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN); 486 char cardtype; 487 int err; 488 489 mmc->card_caps = MMC_MODE_4BIT | MMC_MODE_8BIT; 490 491 if (mmc_host_is_spi(mmc)) 492 return 0; 493 494 /* Only version 4 supports high-speed */ 495 if (mmc->version < MMC_VERSION_4) 496 return 0; 497 498 err = mmc_send_ext_csd(mmc, ext_csd); 499 500 if (err) 501 return err; 502 503 cardtype = ext_csd[EXT_CSD_CARD_TYPE] & 0xf; 504 505 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_HS_TIMING, 1); 506 507 if (err) 508 return err == SWITCH_ERR ? 0 : err; 509 510 /* Now check to see that it worked */ 511 err = mmc_send_ext_csd(mmc, ext_csd); 512 513 if (err) 514 return err; 515 516 /* No high-speed support */ 517 if (!ext_csd[EXT_CSD_HS_TIMING]) 518 return 0; 519 520 /* High Speed is set, there are two types: 52MHz and 26MHz */ 521 if (cardtype & EXT_CSD_CARD_TYPE_52) { 522 if (cardtype & EXT_CSD_CARD_TYPE_DDR_1_8V) 523 mmc->card_caps |= MMC_MODE_DDR_52MHz; 524 mmc->card_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS; 525 } else { 526 mmc->card_caps |= MMC_MODE_HS; 527 } 528 529 return 0; 530 } 531 532 static int mmc_set_capacity(struct mmc *mmc, int part_num) 533 { 534 switch (part_num) { 535 case 0: 536 mmc->capacity = mmc->capacity_user; 537 break; 538 case 1: 539 case 2: 540 mmc->capacity = mmc->capacity_boot; 541 break; 542 case 3: 543 mmc->capacity = mmc->capacity_rpmb; 544 break; 545 case 4: 546 case 5: 547 case 6: 548 case 7: 549 mmc->capacity = mmc->capacity_gp[part_num - 4]; 550 break; 551 default: 552 return -1; 553 } 554 555 mmc->block_dev.lba = lldiv(mmc->capacity, mmc->read_bl_len); 556 557 return 0; 558 } 559 560 int mmc_select_hwpart(int dev_num, int hwpart) 561 { 562 struct mmc *mmc = find_mmc_device(dev_num); 563 int ret; 564 565 if (!mmc) 566 return -ENODEV; 567 568 if (mmc->part_num == hwpart) 569 return 0; 570 571 if (mmc->part_config == MMCPART_NOAVAILABLE) { 572 printf("Card doesn't support part_switch\n"); 573 return -EMEDIUMTYPE; 574 } 575 576 ret = mmc_switch_part(dev_num, hwpart); 577 if (ret) 578 return ret; 579 580 mmc->part_num = hwpart; 581 582 return 0; 583 } 584 585 586 int mmc_switch_part(int dev_num, unsigned int part_num) 587 { 588 struct mmc *mmc = find_mmc_device(dev_num); 589 int ret; 590 591 if (!mmc) 592 return -1; 593 594 ret = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_PART_CONF, 595 (mmc->part_config & ~PART_ACCESS_MASK) 596 | (part_num & PART_ACCESS_MASK)); 597 598 /* 599 * Set the capacity if the switch succeeded or was intended 600 * to return to representing the raw device. 601 */ 602 if ((ret == 0) || ((ret == -ENODEV) && (part_num == 0))) 603 ret = mmc_set_capacity(mmc, part_num); 604 605 return ret; 606 } 607 608 int mmc_hwpart_config(struct mmc *mmc, 609 const struct mmc_hwpart_conf *conf, 610 enum mmc_hwpart_conf_mode mode) 611 { 612 u8 part_attrs = 0; 613 u32 enh_size_mult; 614 u32 enh_start_addr; 615 u32 gp_size_mult[4]; 616 u32 max_enh_size_mult; 617 u32 tot_enh_size_mult = 0; 618 u8 wr_rel_set; 619 int i, pidx, err; 620 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN); 621 622 if (mode < MMC_HWPART_CONF_CHECK || mode > MMC_HWPART_CONF_COMPLETE) 623 return -EINVAL; 624 625 if (IS_SD(mmc) || (mmc->version < MMC_VERSION_4_41)) { 626 printf("eMMC >= 4.4 required for enhanced user data area\n"); 627 return -EMEDIUMTYPE; 628 } 629 630 if (!(mmc->part_support & PART_SUPPORT)) { 631 printf("Card does not support partitioning\n"); 632 return -EMEDIUMTYPE; 633 } 634 635 if (!mmc->hc_wp_grp_size) { 636 printf("Card does not define HC WP group size\n"); 637 return -EMEDIUMTYPE; 638 } 639 640 /* check partition alignment and total enhanced size */ 641 if (conf->user.enh_size) { 642 if (conf->user.enh_size % mmc->hc_wp_grp_size || 643 conf->user.enh_start % mmc->hc_wp_grp_size) { 644 printf("User data enhanced area not HC WP group " 645 "size aligned\n"); 646 return -EINVAL; 647 } 648 part_attrs |= EXT_CSD_ENH_USR; 649 enh_size_mult = conf->user.enh_size / mmc->hc_wp_grp_size; 650 if (mmc->high_capacity) { 651 enh_start_addr = conf->user.enh_start; 652 } else { 653 enh_start_addr = (conf->user.enh_start << 9); 654 } 655 } else { 656 enh_size_mult = 0; 657 enh_start_addr = 0; 658 } 659 tot_enh_size_mult += enh_size_mult; 660 661 for (pidx = 0; pidx < 4; pidx++) { 662 if (conf->gp_part[pidx].size % mmc->hc_wp_grp_size) { 663 printf("GP%i partition not HC WP group size " 664 "aligned\n", pidx+1); 665 return -EINVAL; 666 } 667 gp_size_mult[pidx] = conf->gp_part[pidx].size / mmc->hc_wp_grp_size; 668 if (conf->gp_part[pidx].size && conf->gp_part[pidx].enhanced) { 669 part_attrs |= EXT_CSD_ENH_GP(pidx); 670 tot_enh_size_mult += gp_size_mult[pidx]; 671 } 672 } 673 674 if (part_attrs && ! (mmc->part_support & ENHNCD_SUPPORT)) { 675 printf("Card does not support enhanced attribute\n"); 676 return -EMEDIUMTYPE; 677 } 678 679 err = mmc_send_ext_csd(mmc, ext_csd); 680 if (err) 681 return err; 682 683 max_enh_size_mult = 684 (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+2] << 16) + 685 (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+1] << 8) + 686 ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT]; 687 if (tot_enh_size_mult > max_enh_size_mult) { 688 printf("Total enhanced size exceeds maximum (%u > %u)\n", 689 tot_enh_size_mult, max_enh_size_mult); 690 return -EMEDIUMTYPE; 691 } 692 693 /* The default value of EXT_CSD_WR_REL_SET is device 694 * dependent, the values can only be changed if the 695 * EXT_CSD_HS_CTRL_REL bit is set. The values can be 696 * changed only once and before partitioning is completed. */ 697 wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET]; 698 if (conf->user.wr_rel_change) { 699 if (conf->user.wr_rel_set) 700 wr_rel_set |= EXT_CSD_WR_DATA_REL_USR; 701 else 702 wr_rel_set &= ~EXT_CSD_WR_DATA_REL_USR; 703 } 704 for (pidx = 0; pidx < 4; pidx++) { 705 if (conf->gp_part[pidx].wr_rel_change) { 706 if (conf->gp_part[pidx].wr_rel_set) 707 wr_rel_set |= EXT_CSD_WR_DATA_REL_GP(pidx); 708 else 709 wr_rel_set &= ~EXT_CSD_WR_DATA_REL_GP(pidx); 710 } 711 } 712 713 if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET] && 714 !(ext_csd[EXT_CSD_WR_REL_PARAM] & EXT_CSD_HS_CTRL_REL)) { 715 puts("Card does not support host controlled partition write " 716 "reliability settings\n"); 717 return -EMEDIUMTYPE; 718 } 719 720 if (ext_csd[EXT_CSD_PARTITION_SETTING] & 721 EXT_CSD_PARTITION_SETTING_COMPLETED) { 722 printf("Card already partitioned\n"); 723 return -EPERM; 724 } 725 726 if (mode == MMC_HWPART_CONF_CHECK) 727 return 0; 728 729 /* Partitioning requires high-capacity size definitions */ 730 if (!(ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01)) { 731 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, 732 EXT_CSD_ERASE_GROUP_DEF, 1); 733 734 if (err) 735 return err; 736 737 ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1; 738 739 /* update erase group size to be high-capacity */ 740 mmc->erase_grp_size = 741 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024; 742 743 } 744 745 /* all OK, write the configuration */ 746 for (i = 0; i < 4; i++) { 747 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, 748 EXT_CSD_ENH_START_ADDR+i, 749 (enh_start_addr >> (i*8)) & 0xFF); 750 if (err) 751 return err; 752 } 753 for (i = 0; i < 3; i++) { 754 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, 755 EXT_CSD_ENH_SIZE_MULT+i, 756 (enh_size_mult >> (i*8)) & 0xFF); 757 if (err) 758 return err; 759 } 760 for (pidx = 0; pidx < 4; pidx++) { 761 for (i = 0; i < 3; i++) { 762 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, 763 EXT_CSD_GP_SIZE_MULT+pidx*3+i, 764 (gp_size_mult[pidx] >> (i*8)) & 0xFF); 765 if (err) 766 return err; 767 } 768 } 769 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, 770 EXT_CSD_PARTITIONS_ATTRIBUTE, part_attrs); 771 if (err) 772 return err; 773 774 if (mode == MMC_HWPART_CONF_SET) 775 return 0; 776 777 /* The WR_REL_SET is a write-once register but shall be 778 * written before setting PART_SETTING_COMPLETED. As it is 779 * write-once we can only write it when completing the 780 * partitioning. */ 781 if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET]) { 782 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, 783 EXT_CSD_WR_REL_SET, wr_rel_set); 784 if (err) 785 return err; 786 } 787 788 /* Setting PART_SETTING_COMPLETED confirms the partition 789 * configuration but it only becomes effective after power 790 * cycle, so we do not adjust the partition related settings 791 * in the mmc struct. */ 792 793 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, 794 EXT_CSD_PARTITION_SETTING, 795 EXT_CSD_PARTITION_SETTING_COMPLETED); 796 if (err) 797 return err; 798 799 return 0; 800 } 801 802 int mmc_getcd(struct mmc *mmc) 803 { 804 int cd; 805 806 cd = board_mmc_getcd(mmc); 807 808 if (cd < 0) { 809 if (mmc->cfg->ops->getcd) 810 cd = mmc->cfg->ops->getcd(mmc); 811 else 812 cd = 1; 813 } 814 815 return cd; 816 } 817 818 static int sd_switch(struct mmc *mmc, int mode, int group, u8 value, u8 *resp) 819 { 820 struct mmc_cmd cmd; 821 struct mmc_data data; 822 823 /* Switch the frequency */ 824 cmd.cmdidx = SD_CMD_SWITCH_FUNC; 825 cmd.resp_type = MMC_RSP_R1; 826 cmd.cmdarg = (mode << 31) | 0xffffff; 827 cmd.cmdarg &= ~(0xf << (group * 4)); 828 cmd.cmdarg |= value << (group * 4); 829 830 data.dest = (char *)resp; 831 data.blocksize = 64; 832 data.blocks = 1; 833 data.flags = MMC_DATA_READ; 834 835 return mmc_send_cmd(mmc, &cmd, &data); 836 } 837 838 839 static int sd_change_freq(struct mmc *mmc) 840 { 841 int err; 842 struct mmc_cmd cmd; 843 ALLOC_CACHE_ALIGN_BUFFER(uint, scr, 2); 844 ALLOC_CACHE_ALIGN_BUFFER(uint, switch_status, 16); 845 struct mmc_data data; 846 int timeout; 847 848 mmc->card_caps = 0; 849 850 if (mmc_host_is_spi(mmc)) 851 return 0; 852 853 /* Read the SCR to find out if this card supports higher speeds */ 854 cmd.cmdidx = MMC_CMD_APP_CMD; 855 cmd.resp_type = MMC_RSP_R1; 856 cmd.cmdarg = mmc->rca << 16; 857 858 err = mmc_send_cmd(mmc, &cmd, NULL); 859 860 if (err) 861 return err; 862 863 cmd.cmdidx = SD_CMD_APP_SEND_SCR; 864 cmd.resp_type = MMC_RSP_R1; 865 cmd.cmdarg = 0; 866 867 timeout = 3; 868 869 retry_scr: 870 data.dest = (char *)scr; 871 data.blocksize = 8; 872 data.blocks = 1; 873 data.flags = MMC_DATA_READ; 874 875 err = mmc_send_cmd(mmc, &cmd, &data); 876 877 if (err) { 878 if (timeout--) 879 goto retry_scr; 880 881 return err; 882 } 883 884 mmc->scr[0] = __be32_to_cpu(scr[0]); 885 mmc->scr[1] = __be32_to_cpu(scr[1]); 886 887 switch ((mmc->scr[0] >> 24) & 0xf) { 888 case 0: 889 mmc->version = SD_VERSION_1_0; 890 break; 891 case 1: 892 mmc->version = SD_VERSION_1_10; 893 break; 894 case 2: 895 mmc->version = SD_VERSION_2; 896 if ((mmc->scr[0] >> 15) & 0x1) 897 mmc->version = SD_VERSION_3; 898 break; 899 default: 900 mmc->version = SD_VERSION_1_0; 901 break; 902 } 903 904 if (mmc->scr[0] & SD_DATA_4BIT) 905 mmc->card_caps |= MMC_MODE_4BIT; 906 907 /* Version 1.0 doesn't support switching */ 908 if (mmc->version == SD_VERSION_1_0) 909 return 0; 910 911 timeout = 4; 912 while (timeout--) { 913 err = sd_switch(mmc, SD_SWITCH_CHECK, 0, 1, 914 (u8 *)switch_status); 915 916 if (err) 917 return err; 918 919 /* The high-speed function is busy. Try again */ 920 if (!(__be32_to_cpu(switch_status[7]) & SD_HIGHSPEED_BUSY)) 921 break; 922 } 923 924 /* If high-speed isn't supported, we return */ 925 if (!(__be32_to_cpu(switch_status[3]) & SD_HIGHSPEED_SUPPORTED)) 926 return 0; 927 928 /* 929 * If the host doesn't support SD_HIGHSPEED, do not switch card to 930 * HIGHSPEED mode even if the card support SD_HIGHSPPED. 931 * This can avoid furthur problem when the card runs in different 932 * mode between the host. 933 */ 934 if (!((mmc->cfg->host_caps & MMC_MODE_HS_52MHz) && 935 (mmc->cfg->host_caps & MMC_MODE_HS))) 936 return 0; 937 938 err = sd_switch(mmc, SD_SWITCH_SWITCH, 0, 1, (u8 *)switch_status); 939 940 if (err) 941 return err; 942 943 if ((__be32_to_cpu(switch_status[4]) & 0x0f000000) == 0x01000000) 944 mmc->card_caps |= MMC_MODE_HS; 945 946 return 0; 947 } 948 949 /* frequency bases */ 950 /* divided by 10 to be nice to platforms without floating point */ 951 static const int fbase[] = { 952 10000, 953 100000, 954 1000000, 955 10000000, 956 }; 957 958 /* Multiplier values for TRAN_SPEED. Multiplied by 10 to be nice 959 * to platforms without floating point. 960 */ 961 static const int multipliers[] = { 962 0, /* reserved */ 963 10, 964 12, 965 13, 966 15, 967 20, 968 25, 969 30, 970 35, 971 40, 972 45, 973 50, 974 55, 975 60, 976 70, 977 80, 978 }; 979 980 static void mmc_set_ios(struct mmc *mmc) 981 { 982 if (mmc->cfg->ops->set_ios) 983 mmc->cfg->ops->set_ios(mmc); 984 } 985 986 void mmc_set_clock(struct mmc *mmc, uint clock) 987 { 988 if (clock > mmc->cfg->f_max) 989 clock = mmc->cfg->f_max; 990 991 if (clock < mmc->cfg->f_min) 992 clock = mmc->cfg->f_min; 993 994 mmc->clock = clock; 995 996 mmc_set_ios(mmc); 997 } 998 999 static void mmc_set_bus_width(struct mmc *mmc, uint width) 1000 { 1001 mmc->bus_width = width; 1002 1003 mmc_set_ios(mmc); 1004 } 1005 1006 static int mmc_startup(struct mmc *mmc) 1007 { 1008 int err, i; 1009 uint mult, freq; 1010 u64 cmult, csize, capacity; 1011 struct mmc_cmd cmd; 1012 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN); 1013 ALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, MMC_MAX_BLOCK_LEN); 1014 int timeout = 1000; 1015 bool has_parts = false; 1016 bool part_completed; 1017 1018 #ifdef CONFIG_MMC_SPI_CRC_ON 1019 if (mmc_host_is_spi(mmc)) { /* enable CRC check for spi */ 1020 cmd.cmdidx = MMC_CMD_SPI_CRC_ON_OFF; 1021 cmd.resp_type = MMC_RSP_R1; 1022 cmd.cmdarg = 1; 1023 err = mmc_send_cmd(mmc, &cmd, NULL); 1024 1025 if (err) 1026 return err; 1027 } 1028 #endif 1029 1030 /* Put the Card in Identify Mode */ 1031 cmd.cmdidx = mmc_host_is_spi(mmc) ? MMC_CMD_SEND_CID : 1032 MMC_CMD_ALL_SEND_CID; /* cmd not supported in spi */ 1033 cmd.resp_type = MMC_RSP_R2; 1034 cmd.cmdarg = 0; 1035 1036 err = mmc_send_cmd(mmc, &cmd, NULL); 1037 1038 if (err) 1039 return err; 1040 1041 memcpy(mmc->cid, cmd.response, 16); 1042 1043 /* 1044 * For MMC cards, set the Relative Address. 1045 * For SD cards, get the Relatvie Address. 1046 * This also puts the cards into Standby State 1047 */ 1048 if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */ 1049 cmd.cmdidx = SD_CMD_SEND_RELATIVE_ADDR; 1050 cmd.cmdarg = mmc->rca << 16; 1051 cmd.resp_type = MMC_RSP_R6; 1052 1053 err = mmc_send_cmd(mmc, &cmd, NULL); 1054 1055 if (err) 1056 return err; 1057 1058 if (IS_SD(mmc)) 1059 mmc->rca = (cmd.response[0] >> 16) & 0xffff; 1060 } 1061 1062 /* Get the Card-Specific Data */ 1063 cmd.cmdidx = MMC_CMD_SEND_CSD; 1064 cmd.resp_type = MMC_RSP_R2; 1065 cmd.cmdarg = mmc->rca << 16; 1066 1067 err = mmc_send_cmd(mmc, &cmd, NULL); 1068 1069 /* Waiting for the ready status */ 1070 mmc_send_status(mmc, timeout); 1071 1072 if (err) 1073 return err; 1074 1075 mmc->csd[0] = cmd.response[0]; 1076 mmc->csd[1] = cmd.response[1]; 1077 mmc->csd[2] = cmd.response[2]; 1078 mmc->csd[3] = cmd.response[3]; 1079 1080 if (mmc->version == MMC_VERSION_UNKNOWN) { 1081 int version = (cmd.response[0] >> 26) & 0xf; 1082 1083 switch (version) { 1084 case 0: 1085 mmc->version = MMC_VERSION_1_2; 1086 break; 1087 case 1: 1088 mmc->version = MMC_VERSION_1_4; 1089 break; 1090 case 2: 1091 mmc->version = MMC_VERSION_2_2; 1092 break; 1093 case 3: 1094 mmc->version = MMC_VERSION_3; 1095 break; 1096 case 4: 1097 mmc->version = MMC_VERSION_4; 1098 break; 1099 default: 1100 mmc->version = MMC_VERSION_1_2; 1101 break; 1102 } 1103 } 1104 1105 /* divide frequency by 10, since the mults are 10x bigger */ 1106 freq = fbase[(cmd.response[0] & 0x7)]; 1107 mult = multipliers[((cmd.response[0] >> 3) & 0xf)]; 1108 1109 mmc->tran_speed = freq * mult; 1110 1111 mmc->dsr_imp = ((cmd.response[1] >> 12) & 0x1); 1112 mmc->read_bl_len = 1 << ((cmd.response[1] >> 16) & 0xf); 1113 1114 if (IS_SD(mmc)) 1115 mmc->write_bl_len = mmc->read_bl_len; 1116 else 1117 mmc->write_bl_len = 1 << ((cmd.response[3] >> 22) & 0xf); 1118 1119 if (mmc->high_capacity) { 1120 csize = (mmc->csd[1] & 0x3f) << 16 1121 | (mmc->csd[2] & 0xffff0000) >> 16; 1122 cmult = 8; 1123 } else { 1124 csize = (mmc->csd[1] & 0x3ff) << 2 1125 | (mmc->csd[2] & 0xc0000000) >> 30; 1126 cmult = (mmc->csd[2] & 0x00038000) >> 15; 1127 } 1128 1129 mmc->capacity_user = (csize + 1) << (cmult + 2); 1130 mmc->capacity_user *= mmc->read_bl_len; 1131 mmc->capacity_boot = 0; 1132 mmc->capacity_rpmb = 0; 1133 for (i = 0; i < 4; i++) 1134 mmc->capacity_gp[i] = 0; 1135 1136 if (mmc->read_bl_len > MMC_MAX_BLOCK_LEN) 1137 mmc->read_bl_len = MMC_MAX_BLOCK_LEN; 1138 1139 if (mmc->write_bl_len > MMC_MAX_BLOCK_LEN) 1140 mmc->write_bl_len = MMC_MAX_BLOCK_LEN; 1141 1142 if ((mmc->dsr_imp) && (0xffffffff != mmc->dsr)) { 1143 cmd.cmdidx = MMC_CMD_SET_DSR; 1144 cmd.cmdarg = (mmc->dsr & 0xffff) << 16; 1145 cmd.resp_type = MMC_RSP_NONE; 1146 if (mmc_send_cmd(mmc, &cmd, NULL)) 1147 printf("MMC: SET_DSR failed\n"); 1148 } 1149 1150 /* Select the card, and put it into Transfer Mode */ 1151 if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */ 1152 cmd.cmdidx = MMC_CMD_SELECT_CARD; 1153 cmd.resp_type = MMC_RSP_R1; 1154 cmd.cmdarg = mmc->rca << 16; 1155 err = mmc_send_cmd(mmc, &cmd, NULL); 1156 1157 if (err) 1158 return err; 1159 } 1160 1161 /* 1162 * For SD, its erase group is always one sector 1163 */ 1164 mmc->erase_grp_size = 1; 1165 mmc->part_config = MMCPART_NOAVAILABLE; 1166 if (!IS_SD(mmc) && (mmc->version >= MMC_VERSION_4)) { 1167 /* check ext_csd version and capacity */ 1168 err = mmc_send_ext_csd(mmc, ext_csd); 1169 if (err) 1170 return err; 1171 if (ext_csd[EXT_CSD_REV] >= 2) { 1172 /* 1173 * According to the JEDEC Standard, the value of 1174 * ext_csd's capacity is valid if the value is more 1175 * than 2GB 1176 */ 1177 capacity = ext_csd[EXT_CSD_SEC_CNT] << 0 1178 | ext_csd[EXT_CSD_SEC_CNT + 1] << 8 1179 | ext_csd[EXT_CSD_SEC_CNT + 2] << 16 1180 | ext_csd[EXT_CSD_SEC_CNT + 3] << 24; 1181 capacity *= MMC_MAX_BLOCK_LEN; 1182 if ((capacity >> 20) > 2 * 1024) 1183 mmc->capacity_user = capacity; 1184 } 1185 1186 switch (ext_csd[EXT_CSD_REV]) { 1187 case 1: 1188 mmc->version = MMC_VERSION_4_1; 1189 break; 1190 case 2: 1191 mmc->version = MMC_VERSION_4_2; 1192 break; 1193 case 3: 1194 mmc->version = MMC_VERSION_4_3; 1195 break; 1196 case 5: 1197 mmc->version = MMC_VERSION_4_41; 1198 break; 1199 case 6: 1200 mmc->version = MMC_VERSION_4_5; 1201 break; 1202 case 7: 1203 mmc->version = MMC_VERSION_5_0; 1204 break; 1205 } 1206 1207 /* The partition data may be non-zero but it is only 1208 * effective if PARTITION_SETTING_COMPLETED is set in 1209 * EXT_CSD, so ignore any data if this bit is not set, 1210 * except for enabling the high-capacity group size 1211 * definition (see below). */ 1212 part_completed = !!(ext_csd[EXT_CSD_PARTITION_SETTING] & 1213 EXT_CSD_PARTITION_SETTING_COMPLETED); 1214 1215 /* store the partition info of emmc */ 1216 mmc->part_support = ext_csd[EXT_CSD_PARTITIONING_SUPPORT]; 1217 if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) || 1218 ext_csd[EXT_CSD_BOOT_MULT]) 1219 mmc->part_config = ext_csd[EXT_CSD_PART_CONF]; 1220 if (part_completed && 1221 (ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & ENHNCD_SUPPORT)) 1222 mmc->part_attr = ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE]; 1223 1224 mmc->capacity_boot = ext_csd[EXT_CSD_BOOT_MULT] << 17; 1225 1226 mmc->capacity_rpmb = ext_csd[EXT_CSD_RPMB_MULT] << 17; 1227 1228 for (i = 0; i < 4; i++) { 1229 int idx = EXT_CSD_GP_SIZE_MULT + i * 3; 1230 uint mult = (ext_csd[idx + 2] << 16) + 1231 (ext_csd[idx + 1] << 8) + ext_csd[idx]; 1232 if (mult) 1233 has_parts = true; 1234 if (!part_completed) 1235 continue; 1236 mmc->capacity_gp[i] = mult; 1237 mmc->capacity_gp[i] *= 1238 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]; 1239 mmc->capacity_gp[i] *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE]; 1240 mmc->capacity_gp[i] <<= 19; 1241 } 1242 1243 if (part_completed) { 1244 mmc->enh_user_size = 1245 (ext_csd[EXT_CSD_ENH_SIZE_MULT+2] << 16) + 1246 (ext_csd[EXT_CSD_ENH_SIZE_MULT+1] << 8) + 1247 ext_csd[EXT_CSD_ENH_SIZE_MULT]; 1248 mmc->enh_user_size *= ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]; 1249 mmc->enh_user_size *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE]; 1250 mmc->enh_user_size <<= 19; 1251 mmc->enh_user_start = 1252 (ext_csd[EXT_CSD_ENH_START_ADDR+3] << 24) + 1253 (ext_csd[EXT_CSD_ENH_START_ADDR+2] << 16) + 1254 (ext_csd[EXT_CSD_ENH_START_ADDR+1] << 8) + 1255 ext_csd[EXT_CSD_ENH_START_ADDR]; 1256 if (mmc->high_capacity) 1257 mmc->enh_user_start <<= 9; 1258 } 1259 1260 /* 1261 * Host needs to enable ERASE_GRP_DEF bit if device is 1262 * partitioned. This bit will be lost every time after a reset 1263 * or power off. This will affect erase size. 1264 */ 1265 if (part_completed) 1266 has_parts = true; 1267 if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) && 1268 (ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE] & PART_ENH_ATTRIB)) 1269 has_parts = true; 1270 if (has_parts) { 1271 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, 1272 EXT_CSD_ERASE_GROUP_DEF, 1); 1273 1274 if (err) 1275 return err; 1276 else 1277 ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1; 1278 } 1279 1280 if (ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01) { 1281 /* Read out group size from ext_csd */ 1282 mmc->erase_grp_size = 1283 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024; 1284 /* 1285 * if high capacity and partition setting completed 1286 * SEC_COUNT is valid even if it is smaller than 2 GiB 1287 * JEDEC Standard JESD84-B45, 6.2.4 1288 */ 1289 if (mmc->high_capacity && part_completed) { 1290 capacity = (ext_csd[EXT_CSD_SEC_CNT]) | 1291 (ext_csd[EXT_CSD_SEC_CNT + 1] << 8) | 1292 (ext_csd[EXT_CSD_SEC_CNT + 2] << 16) | 1293 (ext_csd[EXT_CSD_SEC_CNT + 3] << 24); 1294 capacity *= MMC_MAX_BLOCK_LEN; 1295 mmc->capacity_user = capacity; 1296 } 1297 } else { 1298 /* Calculate the group size from the csd value. */ 1299 int erase_gsz, erase_gmul; 1300 erase_gsz = (mmc->csd[2] & 0x00007c00) >> 10; 1301 erase_gmul = (mmc->csd[2] & 0x000003e0) >> 5; 1302 mmc->erase_grp_size = (erase_gsz + 1) 1303 * (erase_gmul + 1); 1304 } 1305 1306 mmc->hc_wp_grp_size = 1024 1307 * ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] 1308 * ext_csd[EXT_CSD_HC_WP_GRP_SIZE]; 1309 1310 mmc->wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET]; 1311 } 1312 1313 err = mmc_set_capacity(mmc, mmc->part_num); 1314 if (err) 1315 return err; 1316 1317 if (IS_SD(mmc)) 1318 err = sd_change_freq(mmc); 1319 else 1320 err = mmc_change_freq(mmc); 1321 1322 if (err) 1323 return err; 1324 1325 /* Restrict card's capabilities by what the host can do */ 1326 mmc->card_caps &= mmc->cfg->host_caps; 1327 1328 if (IS_SD(mmc)) { 1329 if (mmc->card_caps & MMC_MODE_4BIT) { 1330 cmd.cmdidx = MMC_CMD_APP_CMD; 1331 cmd.resp_type = MMC_RSP_R1; 1332 cmd.cmdarg = mmc->rca << 16; 1333 1334 err = mmc_send_cmd(mmc, &cmd, NULL); 1335 if (err) 1336 return err; 1337 1338 cmd.cmdidx = SD_CMD_APP_SET_BUS_WIDTH; 1339 cmd.resp_type = MMC_RSP_R1; 1340 cmd.cmdarg = 2; 1341 err = mmc_send_cmd(mmc, &cmd, NULL); 1342 if (err) 1343 return err; 1344 1345 mmc_set_bus_width(mmc, 4); 1346 } 1347 1348 if (mmc->card_caps & MMC_MODE_HS) 1349 mmc->tran_speed = 50000000; 1350 else 1351 mmc->tran_speed = 25000000; 1352 } else { 1353 int idx; 1354 1355 /* An array of possible bus widths in order of preference */ 1356 static unsigned ext_csd_bits[] = { 1357 EXT_CSD_DDR_BUS_WIDTH_8, 1358 EXT_CSD_DDR_BUS_WIDTH_4, 1359 EXT_CSD_BUS_WIDTH_8, 1360 EXT_CSD_BUS_WIDTH_4, 1361 EXT_CSD_BUS_WIDTH_1, 1362 }; 1363 1364 /* An array to map CSD bus widths to host cap bits */ 1365 static unsigned ext_to_hostcaps[] = { 1366 [EXT_CSD_DDR_BUS_WIDTH_4] = 1367 MMC_MODE_DDR_52MHz | MMC_MODE_4BIT, 1368 [EXT_CSD_DDR_BUS_WIDTH_8] = 1369 MMC_MODE_DDR_52MHz | MMC_MODE_8BIT, 1370 [EXT_CSD_BUS_WIDTH_4] = MMC_MODE_4BIT, 1371 [EXT_CSD_BUS_WIDTH_8] = MMC_MODE_8BIT, 1372 }; 1373 1374 /* An array to map chosen bus width to an integer */ 1375 static unsigned widths[] = { 1376 8, 4, 8, 4, 1, 1377 }; 1378 1379 for (idx=0; idx < ARRAY_SIZE(ext_csd_bits); idx++) { 1380 unsigned int extw = ext_csd_bits[idx]; 1381 unsigned int caps = ext_to_hostcaps[extw]; 1382 1383 /* 1384 * Check to make sure the card and controller support 1385 * these capabilities 1386 */ 1387 if ((mmc->card_caps & caps) != caps) 1388 continue; 1389 1390 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, 1391 EXT_CSD_BUS_WIDTH, extw); 1392 1393 if (err) 1394 continue; 1395 1396 mmc->ddr_mode = (caps & MMC_MODE_DDR_52MHz) ? 1 : 0; 1397 mmc_set_bus_width(mmc, widths[idx]); 1398 1399 err = mmc_send_ext_csd(mmc, test_csd); 1400 1401 if (err) 1402 continue; 1403 1404 /* Only compare read only fields */ 1405 if (ext_csd[EXT_CSD_PARTITIONING_SUPPORT] 1406 == test_csd[EXT_CSD_PARTITIONING_SUPPORT] && 1407 ext_csd[EXT_CSD_HC_WP_GRP_SIZE] 1408 == test_csd[EXT_CSD_HC_WP_GRP_SIZE] && 1409 ext_csd[EXT_CSD_REV] 1410 == test_csd[EXT_CSD_REV] && 1411 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] 1412 == test_csd[EXT_CSD_HC_ERASE_GRP_SIZE] && 1413 memcmp(&ext_csd[EXT_CSD_SEC_CNT], 1414 &test_csd[EXT_CSD_SEC_CNT], 4) == 0) 1415 break; 1416 else 1417 err = SWITCH_ERR; 1418 } 1419 1420 if (err) 1421 return err; 1422 1423 if (mmc->card_caps & MMC_MODE_HS) { 1424 if (mmc->card_caps & MMC_MODE_HS_52MHz) 1425 mmc->tran_speed = 52000000; 1426 else 1427 mmc->tran_speed = 26000000; 1428 } 1429 } 1430 1431 mmc_set_clock(mmc, mmc->tran_speed); 1432 1433 /* Fix the block length for DDR mode */ 1434 if (mmc->ddr_mode) { 1435 mmc->read_bl_len = MMC_MAX_BLOCK_LEN; 1436 mmc->write_bl_len = MMC_MAX_BLOCK_LEN; 1437 } 1438 1439 /* fill in device description */ 1440 mmc->block_dev.lun = 0; 1441 mmc->block_dev.type = 0; 1442 mmc->block_dev.blksz = mmc->read_bl_len; 1443 mmc->block_dev.log2blksz = LOG2(mmc->block_dev.blksz); 1444 mmc->block_dev.lba = lldiv(mmc->capacity, mmc->read_bl_len); 1445 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) 1446 sprintf(mmc->block_dev.vendor, "Man %06x Snr %04x%04x", 1447 mmc->cid[0] >> 24, (mmc->cid[2] & 0xffff), 1448 (mmc->cid[3] >> 16) & 0xffff); 1449 sprintf(mmc->block_dev.product, "%c%c%c%c%c%c", mmc->cid[0] & 0xff, 1450 (mmc->cid[1] >> 24), (mmc->cid[1] >> 16) & 0xff, 1451 (mmc->cid[1] >> 8) & 0xff, mmc->cid[1] & 0xff, 1452 (mmc->cid[2] >> 24) & 0xff); 1453 sprintf(mmc->block_dev.revision, "%d.%d", (mmc->cid[2] >> 20) & 0xf, 1454 (mmc->cid[2] >> 16) & 0xf); 1455 #else 1456 mmc->block_dev.vendor[0] = 0; 1457 mmc->block_dev.product[0] = 0; 1458 mmc->block_dev.revision[0] = 0; 1459 #endif 1460 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBDISK_SUPPORT) 1461 init_part(&mmc->block_dev); 1462 #endif 1463 1464 return 0; 1465 } 1466 1467 static int mmc_send_if_cond(struct mmc *mmc) 1468 { 1469 struct mmc_cmd cmd; 1470 int err; 1471 1472 cmd.cmdidx = SD_CMD_SEND_IF_COND; 1473 /* We set the bit if the host supports voltages between 2.7 and 3.6 V */ 1474 cmd.cmdarg = ((mmc->cfg->voltages & 0xff8000) != 0) << 8 | 0xaa; 1475 cmd.resp_type = MMC_RSP_R7; 1476 1477 err = mmc_send_cmd(mmc, &cmd, NULL); 1478 1479 if (err) 1480 return err; 1481 1482 if ((cmd.response[0] & 0xff) != 0xaa) 1483 return UNUSABLE_ERR; 1484 else 1485 mmc->version = SD_VERSION_2; 1486 1487 return 0; 1488 } 1489 1490 /* not used any more */ 1491 int __deprecated mmc_register(struct mmc *mmc) 1492 { 1493 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) 1494 printf("%s is deprecated! use mmc_create() instead.\n", __func__); 1495 #endif 1496 return -1; 1497 } 1498 1499 struct mmc *mmc_create(const struct mmc_config *cfg, void *priv) 1500 { 1501 struct mmc *mmc; 1502 1503 /* quick validation */ 1504 if (cfg == NULL || cfg->ops == NULL || cfg->ops->send_cmd == NULL || 1505 cfg->f_min == 0 || cfg->f_max == 0 || cfg->b_max == 0) 1506 return NULL; 1507 1508 mmc = calloc(1, sizeof(*mmc)); 1509 if (mmc == NULL) 1510 return NULL; 1511 1512 mmc->cfg = cfg; 1513 mmc->priv = priv; 1514 1515 /* the following chunk was mmc_register() */ 1516 1517 /* Setup dsr related values */ 1518 mmc->dsr_imp = 0; 1519 mmc->dsr = 0xffffffff; 1520 /* Setup the universal parts of the block interface just once */ 1521 mmc->block_dev.if_type = IF_TYPE_MMC; 1522 mmc->block_dev.dev = cur_dev_num++; 1523 mmc->block_dev.removable = 1; 1524 mmc->block_dev.block_read = mmc_bread; 1525 mmc->block_dev.block_write = mmc_bwrite; 1526 mmc->block_dev.block_erase = mmc_berase; 1527 1528 /* setup initial part type */ 1529 mmc->block_dev.part_type = mmc->cfg->part_type; 1530 1531 INIT_LIST_HEAD(&mmc->link); 1532 1533 list_add_tail(&mmc->link, &mmc_devices); 1534 1535 return mmc; 1536 } 1537 1538 void mmc_destroy(struct mmc *mmc) 1539 { 1540 /* only freeing memory for now */ 1541 free(mmc); 1542 } 1543 1544 #ifdef CONFIG_PARTITIONS 1545 block_dev_desc_t *mmc_get_dev(int dev) 1546 { 1547 struct mmc *mmc = find_mmc_device(dev); 1548 if (!mmc || mmc_init(mmc)) 1549 return NULL; 1550 1551 return &mmc->block_dev; 1552 } 1553 #endif 1554 1555 /* board-specific MMC power initializations. */ 1556 __weak void board_mmc_power_init(void) 1557 { 1558 } 1559 1560 int mmc_start_init(struct mmc *mmc) 1561 { 1562 int err; 1563 1564 /* we pretend there's no card when init is NULL */ 1565 if (mmc_getcd(mmc) == 0 || mmc->cfg->ops->init == NULL) { 1566 mmc->has_init = 0; 1567 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) 1568 printf("MMC: no card present\n"); 1569 #endif 1570 return NO_CARD_ERR; 1571 } 1572 1573 if (mmc->has_init) 1574 return 0; 1575 1576 board_mmc_power_init(); 1577 1578 /* made sure it's not NULL earlier */ 1579 err = mmc->cfg->ops->init(mmc); 1580 1581 if (err) 1582 return err; 1583 1584 mmc->ddr_mode = 0; 1585 mmc_set_bus_width(mmc, 1); 1586 mmc_set_clock(mmc, 1); 1587 1588 /* Reset the Card */ 1589 err = mmc_go_idle(mmc); 1590 1591 if (err) 1592 return err; 1593 1594 /* The internal partition reset to user partition(0) at every CMD0*/ 1595 mmc->part_num = 0; 1596 1597 /* Test for SD version 2 */ 1598 err = mmc_send_if_cond(mmc); 1599 1600 /* Now try to get the SD card's operating condition */ 1601 err = sd_send_op_cond(mmc); 1602 1603 /* If the command timed out, we check for an MMC card */ 1604 if (err == TIMEOUT) { 1605 err = mmc_send_op_cond(mmc); 1606 1607 if (err && err != IN_PROGRESS) { 1608 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) 1609 printf("Card did not respond to voltage select!\n"); 1610 #endif 1611 return UNUSABLE_ERR; 1612 } 1613 } 1614 1615 if (err == IN_PROGRESS) 1616 mmc->init_in_progress = 1; 1617 1618 return err; 1619 } 1620 1621 static int mmc_complete_init(struct mmc *mmc) 1622 { 1623 int err = 0; 1624 1625 if (mmc->op_cond_pending) 1626 err = mmc_complete_op_cond(mmc); 1627 1628 if (!err) 1629 err = mmc_startup(mmc); 1630 if (err) 1631 mmc->has_init = 0; 1632 else 1633 mmc->has_init = 1; 1634 mmc->init_in_progress = 0; 1635 return err; 1636 } 1637 1638 int mmc_init(struct mmc *mmc) 1639 { 1640 int err = IN_PROGRESS; 1641 unsigned start; 1642 1643 if (mmc->has_init) 1644 return 0; 1645 1646 start = get_timer(0); 1647 1648 if (!mmc->init_in_progress) 1649 err = mmc_start_init(mmc); 1650 1651 if (!err || err == IN_PROGRESS) 1652 err = mmc_complete_init(mmc); 1653 debug("%s: %d, time %lu\n", __func__, err, get_timer(start)); 1654 return err; 1655 } 1656 1657 int mmc_set_dsr(struct mmc *mmc, u16 val) 1658 { 1659 mmc->dsr = val; 1660 return 0; 1661 } 1662 1663 /* CPU-specific MMC initializations */ 1664 __weak int cpu_mmc_init(bd_t *bis) 1665 { 1666 return -1; 1667 } 1668 1669 /* board-specific MMC initializations. */ 1670 __weak int board_mmc_init(bd_t *bis) 1671 { 1672 return -1; 1673 } 1674 1675 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) 1676 1677 void print_mmc_devices(char separator) 1678 { 1679 struct mmc *m; 1680 struct list_head *entry; 1681 1682 list_for_each(entry, &mmc_devices) { 1683 m = list_entry(entry, struct mmc, link); 1684 1685 printf("%s: %d", m->cfg->name, m->block_dev.dev); 1686 1687 if (entry->next != &mmc_devices) { 1688 printf("%c", separator); 1689 if (separator != '\n') 1690 puts (" "); 1691 } 1692 } 1693 1694 printf("\n"); 1695 } 1696 1697 #else 1698 void print_mmc_devices(char separator) { } 1699 #endif 1700 1701 int get_mmc_num(void) 1702 { 1703 return cur_dev_num; 1704 } 1705 1706 void mmc_set_preinit(struct mmc *mmc, int preinit) 1707 { 1708 mmc->preinit = preinit; 1709 } 1710 1711 static void do_preinit(void) 1712 { 1713 struct mmc *m; 1714 struct list_head *entry; 1715 1716 list_for_each(entry, &mmc_devices) { 1717 m = list_entry(entry, struct mmc, link); 1718 1719 if (m->preinit) 1720 mmc_start_init(m); 1721 } 1722 } 1723 1724 1725 int mmc_initialize(bd_t *bis) 1726 { 1727 INIT_LIST_HEAD (&mmc_devices); 1728 cur_dev_num = 0; 1729 1730 if (board_mmc_init(bis) < 0) 1731 cpu_mmc_init(bis); 1732 1733 #ifndef CONFIG_SPL_BUILD 1734 print_mmc_devices(','); 1735 #endif 1736 1737 do_preinit(); 1738 return 0; 1739 } 1740 1741 #ifdef CONFIG_SUPPORT_EMMC_BOOT 1742 /* 1743 * This function changes the size of boot partition and the size of rpmb 1744 * partition present on EMMC devices. 1745 * 1746 * Input Parameters: 1747 * struct *mmc: pointer for the mmc device strcuture 1748 * bootsize: size of boot partition 1749 * rpmbsize: size of rpmb partition 1750 * 1751 * Returns 0 on success. 1752 */ 1753 1754 int mmc_boot_partition_size_change(struct mmc *mmc, unsigned long bootsize, 1755 unsigned long rpmbsize) 1756 { 1757 int err; 1758 struct mmc_cmd cmd; 1759 1760 /* Only use this command for raw EMMC moviNAND. Enter backdoor mode */ 1761 cmd.cmdidx = MMC_CMD_RES_MAN; 1762 cmd.resp_type = MMC_RSP_R1b; 1763 cmd.cmdarg = MMC_CMD62_ARG1; 1764 1765 err = mmc_send_cmd(mmc, &cmd, NULL); 1766 if (err) { 1767 debug("mmc_boot_partition_size_change: Error1 = %d\n", err); 1768 return err; 1769 } 1770 1771 /* Boot partition changing mode */ 1772 cmd.cmdidx = MMC_CMD_RES_MAN; 1773 cmd.resp_type = MMC_RSP_R1b; 1774 cmd.cmdarg = MMC_CMD62_ARG2; 1775 1776 err = mmc_send_cmd(mmc, &cmd, NULL); 1777 if (err) { 1778 debug("mmc_boot_partition_size_change: Error2 = %d\n", err); 1779 return err; 1780 } 1781 /* boot partition size is multiple of 128KB */ 1782 bootsize = (bootsize * 1024) / 128; 1783 1784 /* Arg: boot partition size */ 1785 cmd.cmdidx = MMC_CMD_RES_MAN; 1786 cmd.resp_type = MMC_RSP_R1b; 1787 cmd.cmdarg = bootsize; 1788 1789 err = mmc_send_cmd(mmc, &cmd, NULL); 1790 if (err) { 1791 debug("mmc_boot_partition_size_change: Error3 = %d\n", err); 1792 return err; 1793 } 1794 /* RPMB partition size is multiple of 128KB */ 1795 rpmbsize = (rpmbsize * 1024) / 128; 1796 /* Arg: RPMB partition size */ 1797 cmd.cmdidx = MMC_CMD_RES_MAN; 1798 cmd.resp_type = MMC_RSP_R1b; 1799 cmd.cmdarg = rpmbsize; 1800 1801 err = mmc_send_cmd(mmc, &cmd, NULL); 1802 if (err) { 1803 debug("mmc_boot_partition_size_change: Error4 = %d\n", err); 1804 return err; 1805 } 1806 return 0; 1807 } 1808 1809 /* 1810 * Modify EXT_CSD[177] which is BOOT_BUS_WIDTH 1811 * based on the passed in values for BOOT_BUS_WIDTH, RESET_BOOT_BUS_WIDTH 1812 * and BOOT_MODE. 1813 * 1814 * Returns 0 on success. 1815 */ 1816 int mmc_set_boot_bus_width(struct mmc *mmc, u8 width, u8 reset, u8 mode) 1817 { 1818 int err; 1819 1820 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BOOT_BUS_WIDTH, 1821 EXT_CSD_BOOT_BUS_WIDTH_MODE(mode) | 1822 EXT_CSD_BOOT_BUS_WIDTH_RESET(reset) | 1823 EXT_CSD_BOOT_BUS_WIDTH_WIDTH(width)); 1824 1825 if (err) 1826 return err; 1827 return 0; 1828 } 1829 1830 /* 1831 * Modify EXT_CSD[179] which is PARTITION_CONFIG (formerly BOOT_CONFIG) 1832 * based on the passed in values for BOOT_ACK, BOOT_PARTITION_ENABLE and 1833 * PARTITION_ACCESS. 1834 * 1835 * Returns 0 on success. 1836 */ 1837 int mmc_set_part_conf(struct mmc *mmc, u8 ack, u8 part_num, u8 access) 1838 { 1839 int err; 1840 1841 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_PART_CONF, 1842 EXT_CSD_BOOT_ACK(ack) | 1843 EXT_CSD_BOOT_PART_NUM(part_num) | 1844 EXT_CSD_PARTITION_ACCESS(access)); 1845 1846 if (err) 1847 return err; 1848 return 0; 1849 } 1850 1851 /* 1852 * Modify EXT_CSD[162] which is RST_n_FUNCTION based on the given value 1853 * for enable. Note that this is a write-once field for non-zero values. 1854 * 1855 * Returns 0 on success. 1856 */ 1857 int mmc_set_rst_n_function(struct mmc *mmc, u8 enable) 1858 { 1859 return mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_RST_N_FUNCTION, 1860 enable); 1861 } 1862 #endif 1863