1 /* 2 * Copyright 2008, Freescale Semiconductor, Inc 3 * Andy Fleming 4 * 5 * Based vaguely on the Linux code 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #include <config.h> 11 #include <common.h> 12 #include <command.h> 13 #include <dm.h> 14 #include <dm/device-internal.h> 15 #include <errno.h> 16 #include <mmc.h> 17 #include <part.h> 18 #include <power/regulator.h> 19 #include <malloc.h> 20 #include <memalign.h> 21 #include <linux/list.h> 22 #include <div64.h> 23 #include "mmc_private.h" 24 25 static const unsigned int sd_au_size[] = { 26 0, SZ_16K / 512, SZ_32K / 512, 27 SZ_64K / 512, SZ_128K / 512, SZ_256K / 512, 28 SZ_512K / 512, SZ_1M / 512, SZ_2M / 512, 29 SZ_4M / 512, SZ_8M / 512, (SZ_8M + SZ_4M) / 512, 30 SZ_16M / 512, (SZ_16M + SZ_8M) / 512, SZ_32M / 512, SZ_64M / 512, 31 }; 32 33 #if CONFIG_IS_ENABLED(MMC_TINY) 34 static struct mmc mmc_static; 35 struct mmc *find_mmc_device(int dev_num) 36 { 37 return &mmc_static; 38 } 39 40 void mmc_do_preinit(void) 41 { 42 struct mmc *m = &mmc_static; 43 #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT 44 mmc_set_preinit(m, 1); 45 #endif 46 if (m->preinit) 47 mmc_start_init(m); 48 } 49 50 struct blk_desc *mmc_get_blk_desc(struct mmc *mmc) 51 { 52 return &mmc->block_dev; 53 } 54 #endif 55 56 #if !CONFIG_IS_ENABLED(DM_MMC) 57 __weak int board_mmc_getwp(struct mmc *mmc) 58 { 59 return -1; 60 } 61 62 int mmc_getwp(struct mmc *mmc) 63 { 64 int wp; 65 66 wp = board_mmc_getwp(mmc); 67 68 if (wp < 0) { 69 if (mmc->cfg->ops->getwp) 70 wp = mmc->cfg->ops->getwp(mmc); 71 else 72 wp = 0; 73 } 74 75 return wp; 76 } 77 78 __weak int board_mmc_getcd(struct mmc *mmc) 79 { 80 return -1; 81 } 82 #endif 83 84 #ifdef CONFIG_MMC_TRACE 85 void mmmc_trace_before_send(struct mmc *mmc, struct mmc_cmd *cmd) 86 { 87 printf("CMD_SEND:%d\n", cmd->cmdidx); 88 printf("\t\tARG\t\t\t 0x%08X\n", cmd->cmdarg); 89 } 90 91 void mmmc_trace_after_send(struct mmc *mmc, struct mmc_cmd *cmd, int ret) 92 { 93 int i; 94 u8 *ptr; 95 96 if (ret) { 97 printf("\t\tRET\t\t\t %d\n", ret); 98 } else { 99 switch (cmd->resp_type) { 100 case MMC_RSP_NONE: 101 printf("\t\tMMC_RSP_NONE\n"); 102 break; 103 case MMC_RSP_R1: 104 printf("\t\tMMC_RSP_R1,5,6,7 \t 0x%08X \n", 105 cmd->response[0]); 106 break; 107 case MMC_RSP_R1b: 108 printf("\t\tMMC_RSP_R1b\t\t 0x%08X \n", 109 cmd->response[0]); 110 break; 111 case MMC_RSP_R2: 112 printf("\t\tMMC_RSP_R2\t\t 0x%08X \n", 113 cmd->response[0]); 114 printf("\t\t \t\t 0x%08X \n", 115 cmd->response[1]); 116 printf("\t\t \t\t 0x%08X \n", 117 cmd->response[2]); 118 printf("\t\t \t\t 0x%08X \n", 119 cmd->response[3]); 120 printf("\n"); 121 printf("\t\t\t\t\tDUMPING DATA\n"); 122 for (i = 0; i < 4; i++) { 123 int j; 124 printf("\t\t\t\t\t%03d - ", i*4); 125 ptr = (u8 *)&cmd->response[i]; 126 ptr += 3; 127 for (j = 0; j < 4; j++) 128 printf("%02X ", *ptr--); 129 printf("\n"); 130 } 131 break; 132 case MMC_RSP_R3: 133 printf("\t\tMMC_RSP_R3,4\t\t 0x%08X \n", 134 cmd->response[0]); 135 break; 136 default: 137 printf("\t\tERROR MMC rsp not supported\n"); 138 break; 139 } 140 } 141 } 142 143 void mmc_trace_state(struct mmc *mmc, struct mmc_cmd *cmd) 144 { 145 int status; 146 147 status = (cmd->response[0] & MMC_STATUS_CURR_STATE) >> 9; 148 printf("CURR STATE:%d\n", status); 149 } 150 #endif 151 152 #if !CONFIG_IS_ENABLED(DM_MMC) 153 int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) 154 { 155 int ret; 156 157 mmmc_trace_before_send(mmc, cmd); 158 ret = mmc->cfg->ops->send_cmd(mmc, cmd, data); 159 mmmc_trace_after_send(mmc, cmd, ret); 160 161 return ret; 162 } 163 #endif 164 165 int mmc_send_status(struct mmc *mmc, int timeout) 166 { 167 struct mmc_cmd cmd; 168 int err, retries = 5; 169 170 cmd.cmdidx = MMC_CMD_SEND_STATUS; 171 cmd.resp_type = MMC_RSP_R1; 172 if (!mmc_host_is_spi(mmc)) 173 cmd.cmdarg = mmc->rca << 16; 174 175 while (1) { 176 err = mmc_send_cmd(mmc, &cmd, NULL); 177 if (!err) { 178 if ((cmd.response[0] & MMC_STATUS_RDY_FOR_DATA) && 179 (cmd.response[0] & MMC_STATUS_CURR_STATE) != 180 MMC_STATE_PRG) 181 break; 182 else if (cmd.response[0] & MMC_STATUS_MASK) { 183 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) 184 printf("Status Error: 0x%08X\n", 185 cmd.response[0]); 186 #endif 187 return -ECOMM; 188 } 189 } else if (--retries < 0) 190 return err; 191 192 if (timeout-- <= 0) 193 break; 194 195 udelay(1000); 196 } 197 198 mmc_trace_state(mmc, &cmd); 199 if (timeout <= 0) { 200 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) 201 printf("Timeout waiting card ready\n"); 202 #endif 203 return -ETIMEDOUT; 204 } 205 206 return 0; 207 } 208 209 int mmc_set_blocklen(struct mmc *mmc, int len) 210 { 211 struct mmc_cmd cmd; 212 213 if (mmc->ddr_mode) 214 return 0; 215 216 cmd.cmdidx = MMC_CMD_SET_BLOCKLEN; 217 cmd.resp_type = MMC_RSP_R1; 218 cmd.cmdarg = len; 219 220 return mmc_send_cmd(mmc, &cmd, NULL); 221 } 222 223 static int mmc_read_blocks(struct mmc *mmc, void *dst, lbaint_t start, 224 lbaint_t blkcnt) 225 { 226 struct mmc_cmd cmd; 227 struct mmc_data data; 228 229 if (blkcnt > 1) 230 cmd.cmdidx = MMC_CMD_READ_MULTIPLE_BLOCK; 231 else 232 cmd.cmdidx = MMC_CMD_READ_SINGLE_BLOCK; 233 234 if (mmc->high_capacity) 235 cmd.cmdarg = start; 236 else 237 cmd.cmdarg = start * mmc->read_bl_len; 238 239 cmd.resp_type = MMC_RSP_R1; 240 241 data.dest = dst; 242 data.blocks = blkcnt; 243 data.blocksize = mmc->read_bl_len; 244 data.flags = MMC_DATA_READ; 245 246 if (mmc_send_cmd(mmc, &cmd, &data)) 247 return 0; 248 249 if (blkcnt > 1) { 250 cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION; 251 cmd.cmdarg = 0; 252 cmd.resp_type = MMC_RSP_R1b; 253 if (mmc_send_cmd(mmc, &cmd, NULL)) { 254 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) 255 printf("mmc fail to send stop cmd\n"); 256 #endif 257 return 0; 258 } 259 } 260 261 return blkcnt; 262 } 263 264 #if CONFIG_IS_ENABLED(BLK) 265 ulong mmc_bread(struct udevice *dev, lbaint_t start, lbaint_t blkcnt, void *dst) 266 #else 267 ulong mmc_bread(struct blk_desc *block_dev, lbaint_t start, lbaint_t blkcnt, 268 void *dst) 269 #endif 270 { 271 #if CONFIG_IS_ENABLED(BLK) 272 struct blk_desc *block_dev = dev_get_uclass_platdata(dev); 273 #endif 274 int dev_num = block_dev->devnum; 275 int err; 276 lbaint_t cur, blocks_todo = blkcnt; 277 278 if (blkcnt == 0) 279 return 0; 280 281 struct mmc *mmc = find_mmc_device(dev_num); 282 if (!mmc) 283 return 0; 284 285 if (CONFIG_IS_ENABLED(MMC_TINY)) 286 err = mmc_switch_part(mmc, block_dev->hwpart); 287 else 288 err = blk_dselect_hwpart(block_dev, block_dev->hwpart); 289 290 if (err < 0) 291 return 0; 292 293 if ((start + blkcnt) > block_dev->lba) { 294 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) 295 printf("MMC: block number 0x" LBAF " exceeds max(0x" LBAF ")\n", 296 start + blkcnt, block_dev->lba); 297 #endif 298 return 0; 299 } 300 301 if (mmc_set_blocklen(mmc, mmc->read_bl_len)) { 302 debug("%s: Failed to set blocklen\n", __func__); 303 return 0; 304 } 305 306 do { 307 cur = (blocks_todo > mmc->cfg->b_max) ? 308 mmc->cfg->b_max : blocks_todo; 309 if (mmc_read_blocks(mmc, dst, start, cur) != cur) { 310 debug("%s: Failed to read blocks\n", __func__); 311 return 0; 312 } 313 blocks_todo -= cur; 314 start += cur; 315 dst += cur * mmc->read_bl_len; 316 } while (blocks_todo > 0); 317 318 return blkcnt; 319 } 320 321 static void mmc_set_timing(struct mmc *mmc, uint timing) 322 { 323 mmc->timing = timing; 324 mmc_set_ios(mmc); 325 } 326 327 static int mmc_go_idle(struct mmc *mmc) 328 { 329 struct mmc_cmd cmd; 330 int err; 331 332 udelay(1000); 333 334 cmd.cmdidx = MMC_CMD_GO_IDLE_STATE; 335 cmd.cmdarg = 0; 336 cmd.resp_type = MMC_RSP_NONE; 337 338 err = mmc_send_cmd(mmc, &cmd, NULL); 339 340 if (err) 341 return err; 342 343 udelay(2000); 344 345 return 0; 346 } 347 348 static int sd_send_op_cond(struct mmc *mmc) 349 { 350 int timeout = 1000; 351 int err; 352 struct mmc_cmd cmd; 353 354 while (1) { 355 cmd.cmdidx = MMC_CMD_APP_CMD; 356 cmd.resp_type = MMC_RSP_R1; 357 cmd.cmdarg = 0; 358 359 err = mmc_send_cmd(mmc, &cmd, NULL); 360 361 if (err) 362 return err; 363 364 cmd.cmdidx = SD_CMD_APP_SEND_OP_COND; 365 cmd.resp_type = MMC_RSP_R3; 366 367 /* 368 * Most cards do not answer if some reserved bits 369 * in the ocr are set. However, Some controller 370 * can set bit 7 (reserved for low voltages), but 371 * how to manage low voltages SD card is not yet 372 * specified. 373 */ 374 cmd.cmdarg = mmc_host_is_spi(mmc) ? 0 : 375 (mmc->cfg->voltages & 0xff8000); 376 377 if (mmc->version == SD_VERSION_2) 378 cmd.cmdarg |= OCR_HCS; 379 380 err = mmc_send_cmd(mmc, &cmd, NULL); 381 382 if (err) 383 return err; 384 385 if (cmd.response[0] & OCR_BUSY) 386 break; 387 388 if (timeout-- <= 0) 389 return -EOPNOTSUPP; 390 391 udelay(1000); 392 } 393 394 if (mmc->version != SD_VERSION_2) 395 mmc->version = SD_VERSION_1_0; 396 397 if (mmc_host_is_spi(mmc)) { /* read OCR for spi */ 398 cmd.cmdidx = MMC_CMD_SPI_READ_OCR; 399 cmd.resp_type = MMC_RSP_R3; 400 cmd.cmdarg = 0; 401 402 err = mmc_send_cmd(mmc, &cmd, NULL); 403 404 if (err) 405 return err; 406 } 407 408 mmc->ocr = cmd.response[0]; 409 410 mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS); 411 mmc->rca = 0; 412 413 return 0; 414 } 415 416 static int mmc_send_op_cond_iter(struct mmc *mmc, int use_arg) 417 { 418 struct mmc_cmd cmd; 419 int err; 420 421 cmd.cmdidx = MMC_CMD_SEND_OP_COND; 422 cmd.resp_type = MMC_RSP_R3; 423 cmd.cmdarg = 0; 424 if (use_arg && !mmc_host_is_spi(mmc)) 425 cmd.cmdarg = OCR_HCS | 426 (mmc->cfg->voltages & 427 (mmc->ocr & OCR_VOLTAGE_MASK)) | 428 (mmc->ocr & OCR_ACCESS_MODE); 429 430 err = mmc_send_cmd(mmc, &cmd, NULL); 431 if (err) 432 return err; 433 mmc->ocr = cmd.response[0]; 434 return 0; 435 } 436 437 static int mmc_send_op_cond(struct mmc *mmc) 438 { 439 int err, i; 440 441 /* Some cards seem to need this */ 442 mmc_go_idle(mmc); 443 444 /* Asking to the card its capabilities */ 445 for (i = 0; i < 2; i++) { 446 err = mmc_send_op_cond_iter(mmc, i != 0); 447 if (err) 448 return err; 449 450 /* exit if not busy (flag seems to be inverted) */ 451 if (mmc->ocr & OCR_BUSY) 452 break; 453 } 454 mmc->op_cond_pending = 1; 455 return 0; 456 } 457 458 static int mmc_complete_op_cond(struct mmc *mmc) 459 { 460 struct mmc_cmd cmd; 461 int timeout = 1000; 462 uint start; 463 int err; 464 465 mmc->op_cond_pending = 0; 466 if (!(mmc->ocr & OCR_BUSY)) { 467 /* Some cards seem to need this */ 468 mmc_go_idle(mmc); 469 470 start = get_timer(0); 471 while (1) { 472 err = mmc_send_op_cond_iter(mmc, 1); 473 if (err) 474 return err; 475 if (mmc->ocr & OCR_BUSY) 476 break; 477 if (get_timer(start) > timeout) 478 return -EOPNOTSUPP; 479 udelay(100); 480 } 481 } 482 483 if (mmc_host_is_spi(mmc)) { /* read OCR for spi */ 484 cmd.cmdidx = MMC_CMD_SPI_READ_OCR; 485 cmd.resp_type = MMC_RSP_R3; 486 cmd.cmdarg = 0; 487 488 err = mmc_send_cmd(mmc, &cmd, NULL); 489 490 if (err) 491 return err; 492 493 mmc->ocr = cmd.response[0]; 494 } 495 496 mmc->version = MMC_VERSION_UNKNOWN; 497 498 mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS); 499 mmc->rca = 1; 500 501 return 0; 502 } 503 504 505 static int mmc_send_ext_csd(struct mmc *mmc, u8 *ext_csd) 506 { 507 struct mmc_cmd cmd; 508 struct mmc_data data; 509 int err; 510 511 /* Get the Card Status Register */ 512 cmd.cmdidx = MMC_CMD_SEND_EXT_CSD; 513 cmd.resp_type = MMC_RSP_R1; 514 cmd.cmdarg = 0; 515 516 data.dest = (char *)ext_csd; 517 data.blocks = 1; 518 data.blocksize = MMC_MAX_BLOCK_LEN; 519 data.flags = MMC_DATA_READ; 520 521 err = mmc_send_cmd(mmc, &cmd, &data); 522 523 return err; 524 } 525 526 int mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value) 527 { 528 struct mmc_cmd cmd; 529 int timeout = 1000; 530 int retries = 3; 531 int ret; 532 533 cmd.cmdidx = MMC_CMD_SWITCH; 534 cmd.resp_type = MMC_RSP_R1b; 535 cmd.cmdarg = (MMC_SWITCH_MODE_WRITE_BYTE << 24) | 536 (index << 16) | 537 (value << 8); 538 539 while (retries > 0) { 540 ret = mmc_send_cmd(mmc, &cmd, NULL); 541 542 /* Waiting for the ready status */ 543 if (!ret) { 544 ret = mmc_send_status(mmc, timeout); 545 return ret; 546 } 547 548 retries--; 549 } 550 551 return ret; 552 553 } 554 555 static u32 mmc_select_card_type(struct mmc *mmc, u8 *ext_csd) 556 { 557 u8 card_type; 558 u32 host_caps, avail_type = 0; 559 560 card_type = ext_csd[EXT_CSD_CARD_TYPE]; 561 host_caps = mmc->cfg->host_caps; 562 563 if ((host_caps & MMC_MODE_HS) && 564 (card_type & EXT_CSD_CARD_TYPE_26)) 565 avail_type |= EXT_CSD_CARD_TYPE_26; 566 567 if ((host_caps & MMC_MODE_HS) && 568 (card_type & EXT_CSD_CARD_TYPE_52)) 569 avail_type |= EXT_CSD_CARD_TYPE_52; 570 571 /* 572 * For the moment, u-boot doesn't support signal voltage 573 * switch, therefor we assume that host support ddr52 574 * at 1.8v or 3.3v I/O(1.2v I/O not supported, hs200 and 575 * hs400 are the same). 576 */ 577 if ((host_caps & MMC_MODE_DDR_52MHz) && 578 (card_type & EXT_CSD_CARD_TYPE_DDR_1_8V)) 579 avail_type |= EXT_CSD_CARD_TYPE_DDR_1_8V; 580 581 if ((host_caps & MMC_MODE_HS200) && 582 (card_type & EXT_CSD_CARD_TYPE_HS200_1_8V)) 583 avail_type |= EXT_CSD_CARD_TYPE_HS200_1_8V; 584 585 /* 586 * If host can support HS400, it means that host can also 587 * support HS200. 588 */ 589 if ((host_caps & MMC_MODE_HS400) && 590 (host_caps & MMC_MODE_8BIT) && 591 (card_type & EXT_CSD_CARD_TYPE_HS400_1_8V)) 592 avail_type |= EXT_CSD_CARD_TYPE_HS200_1_8V | 593 EXT_CSD_CARD_TYPE_HS400_1_8V; 594 595 if ((host_caps & MMC_MODE_HS400ES) && 596 (host_caps & MMC_MODE_8BIT) && 597 ext_csd[EXT_CSD_STROBE_SUPPORT] && 598 (avail_type & EXT_CSD_CARD_TYPE_HS400_1_8V)) 599 avail_type |= EXT_CSD_CARD_TYPE_HS200_1_8V | 600 EXT_CSD_CARD_TYPE_HS400_1_8V | 601 EXT_CSD_CARD_TYPE_HS400ES; 602 603 return avail_type; 604 } 605 606 static int mmc_change_freq(struct mmc *mmc) 607 { 608 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN); 609 char cardtype; 610 u32 avail_type; 611 int err; 612 613 mmc->card_caps = 0; 614 615 if (mmc_host_is_spi(mmc)) 616 return 0; 617 618 /* Only version 4 supports high-speed */ 619 if (mmc->version < MMC_VERSION_4) 620 return 0; 621 622 mmc->card_caps |= MMC_MODE_4BIT | MMC_MODE_8BIT; 623 624 err = mmc_send_ext_csd(mmc, ext_csd); 625 626 if (err) 627 return err; 628 629 cardtype = ext_csd[EXT_CSD_CARD_TYPE] & 0xf; 630 avail_type = mmc_select_card_type(mmc, ext_csd); 631 632 if (avail_type & EXT_CSD_CARD_TYPE_HS) 633 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, 634 EXT_CSD_HS_TIMING, 1); 635 else 636 err = -EINVAL; 637 638 if (err) 639 return err; 640 641 /* Now check to see that it worked */ 642 err = mmc_send_ext_csd(mmc, ext_csd); 643 644 if (err) 645 return err; 646 647 /* No high-speed support */ 648 if (!ext_csd[EXT_CSD_HS_TIMING]) 649 return 0; 650 651 /* High Speed is set, there are two types: 52MHz and 26MHz */ 652 if (cardtype & EXT_CSD_CARD_TYPE_52) { 653 if (cardtype & EXT_CSD_CARD_TYPE_DDR_1_8V) 654 mmc->card_caps |= MMC_MODE_DDR_52MHz; 655 mmc->card_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS; 656 } else { 657 mmc->card_caps |= MMC_MODE_HS; 658 } 659 660 return 0; 661 } 662 663 static int mmc_set_capacity(struct mmc *mmc, int part_num) 664 { 665 switch (part_num) { 666 case 0: 667 mmc->capacity = mmc->capacity_user; 668 break; 669 case 1: 670 case 2: 671 mmc->capacity = mmc->capacity_boot; 672 break; 673 case 3: 674 mmc->capacity = mmc->capacity_rpmb; 675 break; 676 case 4: 677 case 5: 678 case 6: 679 case 7: 680 mmc->capacity = mmc->capacity_gp[part_num - 4]; 681 break; 682 default: 683 return -1; 684 } 685 686 mmc_get_blk_desc(mmc)->lba = lldiv(mmc->capacity, mmc->read_bl_len); 687 688 return 0; 689 } 690 691 int mmc_switch_part(struct mmc *mmc, unsigned int part_num) 692 { 693 int ret; 694 695 ret = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_PART_CONF, 696 (mmc->part_config & ~PART_ACCESS_MASK) 697 | (part_num & PART_ACCESS_MASK)); 698 699 /* 700 * Set the capacity if the switch succeeded or was intended 701 * to return to representing the raw device. 702 */ 703 if ((ret == 0) || ((ret == -ENODEV) && (part_num == 0))) { 704 ret = mmc_set_capacity(mmc, part_num); 705 mmc_get_blk_desc(mmc)->hwpart = part_num; 706 } 707 708 return ret; 709 } 710 711 int mmc_hwpart_config(struct mmc *mmc, 712 const struct mmc_hwpart_conf *conf, 713 enum mmc_hwpart_conf_mode mode) 714 { 715 u8 part_attrs = 0; 716 u32 enh_size_mult; 717 u32 enh_start_addr; 718 u32 gp_size_mult[4]; 719 u32 max_enh_size_mult; 720 u32 tot_enh_size_mult = 0; 721 u8 wr_rel_set; 722 int i, pidx, err; 723 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN); 724 725 if (mode < MMC_HWPART_CONF_CHECK || mode > MMC_HWPART_CONF_COMPLETE) 726 return -EINVAL; 727 728 if (IS_SD(mmc) || (mmc->version < MMC_VERSION_4_41)) { 729 printf("eMMC >= 4.4 required for enhanced user data area\n"); 730 return -EMEDIUMTYPE; 731 } 732 733 if (!(mmc->part_support & PART_SUPPORT)) { 734 printf("Card does not support partitioning\n"); 735 return -EMEDIUMTYPE; 736 } 737 738 if (!mmc->hc_wp_grp_size) { 739 printf("Card does not define HC WP group size\n"); 740 return -EMEDIUMTYPE; 741 } 742 743 /* check partition alignment and total enhanced size */ 744 if (conf->user.enh_size) { 745 if (conf->user.enh_size % mmc->hc_wp_grp_size || 746 conf->user.enh_start % mmc->hc_wp_grp_size) { 747 printf("User data enhanced area not HC WP group " 748 "size aligned\n"); 749 return -EINVAL; 750 } 751 part_attrs |= EXT_CSD_ENH_USR; 752 enh_size_mult = conf->user.enh_size / mmc->hc_wp_grp_size; 753 if (mmc->high_capacity) { 754 enh_start_addr = conf->user.enh_start; 755 } else { 756 enh_start_addr = (conf->user.enh_start << 9); 757 } 758 } else { 759 enh_size_mult = 0; 760 enh_start_addr = 0; 761 } 762 tot_enh_size_mult += enh_size_mult; 763 764 for (pidx = 0; pidx < 4; pidx++) { 765 if (conf->gp_part[pidx].size % mmc->hc_wp_grp_size) { 766 printf("GP%i partition not HC WP group size " 767 "aligned\n", pidx+1); 768 return -EINVAL; 769 } 770 gp_size_mult[pidx] = conf->gp_part[pidx].size / mmc->hc_wp_grp_size; 771 if (conf->gp_part[pidx].size && conf->gp_part[pidx].enhanced) { 772 part_attrs |= EXT_CSD_ENH_GP(pidx); 773 tot_enh_size_mult += gp_size_mult[pidx]; 774 } 775 } 776 777 if (part_attrs && ! (mmc->part_support & ENHNCD_SUPPORT)) { 778 printf("Card does not support enhanced attribute\n"); 779 return -EMEDIUMTYPE; 780 } 781 782 err = mmc_send_ext_csd(mmc, ext_csd); 783 if (err) 784 return err; 785 786 max_enh_size_mult = 787 (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+2] << 16) + 788 (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+1] << 8) + 789 ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT]; 790 if (tot_enh_size_mult > max_enh_size_mult) { 791 printf("Total enhanced size exceeds maximum (%u > %u)\n", 792 tot_enh_size_mult, max_enh_size_mult); 793 return -EMEDIUMTYPE; 794 } 795 796 /* The default value of EXT_CSD_WR_REL_SET is device 797 * dependent, the values can only be changed if the 798 * EXT_CSD_HS_CTRL_REL bit is set. The values can be 799 * changed only once and before partitioning is completed. */ 800 wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET]; 801 if (conf->user.wr_rel_change) { 802 if (conf->user.wr_rel_set) 803 wr_rel_set |= EXT_CSD_WR_DATA_REL_USR; 804 else 805 wr_rel_set &= ~EXT_CSD_WR_DATA_REL_USR; 806 } 807 for (pidx = 0; pidx < 4; pidx++) { 808 if (conf->gp_part[pidx].wr_rel_change) { 809 if (conf->gp_part[pidx].wr_rel_set) 810 wr_rel_set |= EXT_CSD_WR_DATA_REL_GP(pidx); 811 else 812 wr_rel_set &= ~EXT_CSD_WR_DATA_REL_GP(pidx); 813 } 814 } 815 816 if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET] && 817 !(ext_csd[EXT_CSD_WR_REL_PARAM] & EXT_CSD_HS_CTRL_REL)) { 818 puts("Card does not support host controlled partition write " 819 "reliability settings\n"); 820 return -EMEDIUMTYPE; 821 } 822 823 if (ext_csd[EXT_CSD_PARTITION_SETTING] & 824 EXT_CSD_PARTITION_SETTING_COMPLETED) { 825 printf("Card already partitioned\n"); 826 return -EPERM; 827 } 828 829 if (mode == MMC_HWPART_CONF_CHECK) 830 return 0; 831 832 /* Partitioning requires high-capacity size definitions */ 833 if (!(ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01)) { 834 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, 835 EXT_CSD_ERASE_GROUP_DEF, 1); 836 837 if (err) 838 return err; 839 840 ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1; 841 842 /* update erase group size to be high-capacity */ 843 mmc->erase_grp_size = 844 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024; 845 846 } 847 848 /* all OK, write the configuration */ 849 for (i = 0; i < 4; i++) { 850 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, 851 EXT_CSD_ENH_START_ADDR+i, 852 (enh_start_addr >> (i*8)) & 0xFF); 853 if (err) 854 return err; 855 } 856 for (i = 0; i < 3; i++) { 857 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, 858 EXT_CSD_ENH_SIZE_MULT+i, 859 (enh_size_mult >> (i*8)) & 0xFF); 860 if (err) 861 return err; 862 } 863 for (pidx = 0; pidx < 4; pidx++) { 864 for (i = 0; i < 3; i++) { 865 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, 866 EXT_CSD_GP_SIZE_MULT+pidx*3+i, 867 (gp_size_mult[pidx] >> (i*8)) & 0xFF); 868 if (err) 869 return err; 870 } 871 } 872 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, 873 EXT_CSD_PARTITIONS_ATTRIBUTE, part_attrs); 874 if (err) 875 return err; 876 877 if (mode == MMC_HWPART_CONF_SET) 878 return 0; 879 880 /* The WR_REL_SET is a write-once register but shall be 881 * written before setting PART_SETTING_COMPLETED. As it is 882 * write-once we can only write it when completing the 883 * partitioning. */ 884 if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET]) { 885 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, 886 EXT_CSD_WR_REL_SET, wr_rel_set); 887 if (err) 888 return err; 889 } 890 891 /* Setting PART_SETTING_COMPLETED confirms the partition 892 * configuration but it only becomes effective after power 893 * cycle, so we do not adjust the partition related settings 894 * in the mmc struct. */ 895 896 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, 897 EXT_CSD_PARTITION_SETTING, 898 EXT_CSD_PARTITION_SETTING_COMPLETED); 899 if (err) 900 return err; 901 902 return 0; 903 } 904 905 #if !CONFIG_IS_ENABLED(DM_MMC) 906 int mmc_getcd(struct mmc *mmc) 907 { 908 int cd; 909 910 cd = board_mmc_getcd(mmc); 911 912 if (cd < 0) { 913 if (mmc->cfg->ops->getcd) 914 cd = mmc->cfg->ops->getcd(mmc); 915 else 916 cd = 1; 917 } 918 919 return cd; 920 } 921 #endif 922 923 static int sd_switch(struct mmc *mmc, int mode, int group, u8 value, u8 *resp) 924 { 925 struct mmc_cmd cmd; 926 struct mmc_data data; 927 928 /* Switch the frequency */ 929 cmd.cmdidx = SD_CMD_SWITCH_FUNC; 930 cmd.resp_type = MMC_RSP_R1; 931 cmd.cmdarg = (mode << 31) | 0xffffff; 932 cmd.cmdarg &= ~(0xf << (group * 4)); 933 cmd.cmdarg |= value << (group * 4); 934 935 data.dest = (char *)resp; 936 data.blocksize = 64; 937 data.blocks = 1; 938 data.flags = MMC_DATA_READ; 939 940 return mmc_send_cmd(mmc, &cmd, &data); 941 } 942 943 944 static int sd_change_freq(struct mmc *mmc) 945 { 946 int err; 947 struct mmc_cmd cmd; 948 ALLOC_CACHE_ALIGN_BUFFER(uint, scr, 2); 949 ALLOC_CACHE_ALIGN_BUFFER(uint, switch_status, 16); 950 struct mmc_data data; 951 int timeout; 952 953 mmc->card_caps = 0; 954 955 if (mmc_host_is_spi(mmc)) 956 return 0; 957 958 /* Read the SCR to find out if this card supports higher speeds */ 959 cmd.cmdidx = MMC_CMD_APP_CMD; 960 cmd.resp_type = MMC_RSP_R1; 961 cmd.cmdarg = mmc->rca << 16; 962 963 err = mmc_send_cmd(mmc, &cmd, NULL); 964 965 if (err) 966 return err; 967 968 cmd.cmdidx = SD_CMD_APP_SEND_SCR; 969 cmd.resp_type = MMC_RSP_R1; 970 cmd.cmdarg = 0; 971 972 timeout = 3; 973 974 retry_scr: 975 data.dest = (char *)scr; 976 data.blocksize = 8; 977 data.blocks = 1; 978 data.flags = MMC_DATA_READ; 979 980 err = mmc_send_cmd(mmc, &cmd, &data); 981 982 if (err) { 983 if (timeout--) 984 goto retry_scr; 985 986 return err; 987 } 988 989 mmc->scr[0] = __be32_to_cpu(scr[0]); 990 mmc->scr[1] = __be32_to_cpu(scr[1]); 991 992 switch ((mmc->scr[0] >> 24) & 0xf) { 993 case 0: 994 mmc->version = SD_VERSION_1_0; 995 break; 996 case 1: 997 mmc->version = SD_VERSION_1_10; 998 break; 999 case 2: 1000 mmc->version = SD_VERSION_2; 1001 if ((mmc->scr[0] >> 15) & 0x1) 1002 mmc->version = SD_VERSION_3; 1003 break; 1004 default: 1005 mmc->version = SD_VERSION_1_0; 1006 break; 1007 } 1008 1009 if (mmc->scr[0] & SD_DATA_4BIT) 1010 mmc->card_caps |= MMC_MODE_4BIT; 1011 1012 /* Version 1.0 doesn't support switching */ 1013 if (mmc->version == SD_VERSION_1_0) 1014 return 0; 1015 1016 timeout = 4; 1017 while (timeout--) { 1018 err = sd_switch(mmc, SD_SWITCH_CHECK, 0, 1, 1019 (u8 *)switch_status); 1020 1021 if (err) 1022 return err; 1023 1024 /* The high-speed function is busy. Try again */ 1025 if (!(__be32_to_cpu(switch_status[7]) & SD_HIGHSPEED_BUSY)) 1026 break; 1027 } 1028 1029 /* If high-speed isn't supported, we return */ 1030 if (!(__be32_to_cpu(switch_status[3]) & SD_HIGHSPEED_SUPPORTED)) 1031 return 0; 1032 1033 /* 1034 * If the host doesn't support SD_HIGHSPEED, do not switch card to 1035 * HIGHSPEED mode even if the card support SD_HIGHSPPED. 1036 * This can avoid furthur problem when the card runs in different 1037 * mode between the host. 1038 */ 1039 if (!((mmc->cfg->host_caps & MMC_MODE_HS_52MHz) && 1040 (mmc->cfg->host_caps & MMC_MODE_HS))) 1041 return 0; 1042 1043 err = sd_switch(mmc, SD_SWITCH_SWITCH, 0, 1, (u8 *)switch_status); 1044 1045 if (err) 1046 return err; 1047 1048 if ((__be32_to_cpu(switch_status[4]) & 0x0f000000) == 0x01000000) 1049 mmc->card_caps |= MMC_MODE_HS; 1050 1051 return 0; 1052 } 1053 1054 static int sd_read_ssr(struct mmc *mmc) 1055 { 1056 int err, i; 1057 struct mmc_cmd cmd; 1058 ALLOC_CACHE_ALIGN_BUFFER(uint, ssr, 16); 1059 struct mmc_data data; 1060 int timeout = 3; 1061 unsigned int au, eo, et, es; 1062 1063 cmd.cmdidx = MMC_CMD_APP_CMD; 1064 cmd.resp_type = MMC_RSP_R1; 1065 cmd.cmdarg = mmc->rca << 16; 1066 1067 err = mmc_send_cmd(mmc, &cmd, NULL); 1068 if (err) 1069 return err; 1070 1071 cmd.cmdidx = SD_CMD_APP_SD_STATUS; 1072 cmd.resp_type = MMC_RSP_R1; 1073 cmd.cmdarg = 0; 1074 1075 retry_ssr: 1076 data.dest = (char *)ssr; 1077 data.blocksize = 64; 1078 data.blocks = 1; 1079 data.flags = MMC_DATA_READ; 1080 1081 err = mmc_send_cmd(mmc, &cmd, &data); 1082 if (err) { 1083 if (timeout--) 1084 goto retry_ssr; 1085 1086 return err; 1087 } 1088 1089 for (i = 0; i < 16; i++) 1090 ssr[i] = be32_to_cpu(ssr[i]); 1091 1092 au = (ssr[2] >> 12) & 0xF; 1093 if ((au <= 9) || (mmc->version == SD_VERSION_3)) { 1094 mmc->ssr.au = sd_au_size[au]; 1095 es = (ssr[3] >> 24) & 0xFF; 1096 es |= (ssr[2] & 0xFF) << 8; 1097 et = (ssr[3] >> 18) & 0x3F; 1098 if (es && et) { 1099 eo = (ssr[3] >> 16) & 0x3; 1100 mmc->ssr.erase_timeout = (et * 1000) / es; 1101 mmc->ssr.erase_offset = eo * 1000; 1102 } 1103 } else { 1104 debug("Invalid Allocation Unit Size.\n"); 1105 } 1106 1107 return 0; 1108 } 1109 1110 /* frequency bases */ 1111 /* divided by 10 to be nice to platforms without floating point */ 1112 static const int fbase[] = { 1113 10000, 1114 100000, 1115 1000000, 1116 10000000, 1117 }; 1118 1119 /* Multiplier values for TRAN_SPEED. Multiplied by 10 to be nice 1120 * to platforms without floating point. 1121 */ 1122 static const u8 multipliers[] = { 1123 0, /* reserved */ 1124 10, 1125 12, 1126 13, 1127 15, 1128 20, 1129 25, 1130 30, 1131 35, 1132 40, 1133 45, 1134 50, 1135 55, 1136 60, 1137 70, 1138 80, 1139 }; 1140 1141 #if !CONFIG_IS_ENABLED(DM_MMC) 1142 static void mmc_set_ios(struct mmc *mmc) 1143 { 1144 if (mmc->cfg->ops->set_ios) 1145 mmc->cfg->ops->set_ios(mmc); 1146 } 1147 #endif 1148 1149 void mmc_set_clock(struct mmc *mmc, uint clock) 1150 { 1151 if (clock > mmc->cfg->f_max) 1152 clock = mmc->cfg->f_max; 1153 1154 if (clock < mmc->cfg->f_min) 1155 clock = mmc->cfg->f_min; 1156 1157 mmc->clock = clock; 1158 1159 mmc_set_ios(mmc); 1160 } 1161 1162 static void mmc_set_bus_width(struct mmc *mmc, uint width) 1163 { 1164 mmc->bus_width = width; 1165 1166 mmc_set_ios(mmc); 1167 } 1168 1169 static int mmc_startup(struct mmc *mmc) 1170 { 1171 int err, i; 1172 uint mult, freq; 1173 u64 cmult, csize, capacity; 1174 struct mmc_cmd cmd; 1175 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN); 1176 ALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, MMC_MAX_BLOCK_LEN); 1177 bool has_parts = false; 1178 bool part_completed; 1179 struct blk_desc *bdesc; 1180 1181 #ifdef CONFIG_MMC_SPI_CRC_ON 1182 if (mmc_host_is_spi(mmc)) { /* enable CRC check for spi */ 1183 cmd.cmdidx = MMC_CMD_SPI_CRC_ON_OFF; 1184 cmd.resp_type = MMC_RSP_R1; 1185 cmd.cmdarg = 1; 1186 err = mmc_send_cmd(mmc, &cmd, NULL); 1187 1188 if (err) 1189 return err; 1190 } 1191 #endif 1192 1193 /* Put the Card in Identify Mode */ 1194 cmd.cmdidx = mmc_host_is_spi(mmc) ? MMC_CMD_SEND_CID : 1195 MMC_CMD_ALL_SEND_CID; /* cmd not supported in spi */ 1196 cmd.resp_type = MMC_RSP_R2; 1197 cmd.cmdarg = 0; 1198 1199 err = mmc_send_cmd(mmc, &cmd, NULL); 1200 1201 if (err) 1202 return err; 1203 1204 memcpy(mmc->cid, cmd.response, 16); 1205 1206 /* 1207 * For MMC cards, set the Relative Address. 1208 * For SD cards, get the Relatvie Address. 1209 * This also puts the cards into Standby State 1210 */ 1211 if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */ 1212 cmd.cmdidx = SD_CMD_SEND_RELATIVE_ADDR; 1213 cmd.cmdarg = mmc->rca << 16; 1214 cmd.resp_type = MMC_RSP_R6; 1215 1216 err = mmc_send_cmd(mmc, &cmd, NULL); 1217 1218 if (err) 1219 return err; 1220 1221 if (IS_SD(mmc)) 1222 mmc->rca = (cmd.response[0] >> 16) & 0xffff; 1223 } 1224 1225 /* Get the Card-Specific Data */ 1226 cmd.cmdidx = MMC_CMD_SEND_CSD; 1227 cmd.resp_type = MMC_RSP_R2; 1228 cmd.cmdarg = mmc->rca << 16; 1229 1230 err = mmc_send_cmd(mmc, &cmd, NULL); 1231 1232 if (err) 1233 return err; 1234 1235 mmc->csd[0] = cmd.response[0]; 1236 mmc->csd[1] = cmd.response[1]; 1237 mmc->csd[2] = cmd.response[2]; 1238 mmc->csd[3] = cmd.response[3]; 1239 1240 if (mmc->version == MMC_VERSION_UNKNOWN) { 1241 int version = (cmd.response[0] >> 26) & 0xf; 1242 1243 switch (version) { 1244 case 0: 1245 mmc->version = MMC_VERSION_1_2; 1246 break; 1247 case 1: 1248 mmc->version = MMC_VERSION_1_4; 1249 break; 1250 case 2: 1251 mmc->version = MMC_VERSION_2_2; 1252 break; 1253 case 3: 1254 mmc->version = MMC_VERSION_3; 1255 break; 1256 case 4: 1257 mmc->version = MMC_VERSION_4; 1258 break; 1259 default: 1260 mmc->version = MMC_VERSION_1_2; 1261 break; 1262 } 1263 } 1264 1265 /* divide frequency by 10, since the mults are 10x bigger */ 1266 freq = fbase[(cmd.response[0] & 0x7)]; 1267 mult = multipliers[((cmd.response[0] >> 3) & 0xf)]; 1268 1269 mmc->tran_speed = freq * mult; 1270 1271 mmc->dsr_imp = ((cmd.response[1] >> 12) & 0x1); 1272 mmc->read_bl_len = 1 << ((cmd.response[1] >> 16) & 0xf); 1273 1274 if (IS_SD(mmc)) 1275 mmc->write_bl_len = mmc->read_bl_len; 1276 else 1277 mmc->write_bl_len = 1 << ((cmd.response[3] >> 22) & 0xf); 1278 1279 if (mmc->high_capacity) { 1280 csize = (mmc->csd[1] & 0x3f) << 16 1281 | (mmc->csd[2] & 0xffff0000) >> 16; 1282 cmult = 8; 1283 } else { 1284 csize = (mmc->csd[1] & 0x3ff) << 2 1285 | (mmc->csd[2] & 0xc0000000) >> 30; 1286 cmult = (mmc->csd[2] & 0x00038000) >> 15; 1287 } 1288 1289 mmc->capacity_user = (csize + 1) << (cmult + 2); 1290 mmc->capacity_user *= mmc->read_bl_len; 1291 mmc->capacity_boot = 0; 1292 mmc->capacity_rpmb = 0; 1293 for (i = 0; i < 4; i++) 1294 mmc->capacity_gp[i] = 0; 1295 1296 if (mmc->read_bl_len > MMC_MAX_BLOCK_LEN) 1297 mmc->read_bl_len = MMC_MAX_BLOCK_LEN; 1298 1299 if (mmc->write_bl_len > MMC_MAX_BLOCK_LEN) 1300 mmc->write_bl_len = MMC_MAX_BLOCK_LEN; 1301 1302 if ((mmc->dsr_imp) && (0xffffffff != mmc->dsr)) { 1303 cmd.cmdidx = MMC_CMD_SET_DSR; 1304 cmd.cmdarg = (mmc->dsr & 0xffff) << 16; 1305 cmd.resp_type = MMC_RSP_NONE; 1306 if (mmc_send_cmd(mmc, &cmd, NULL)) 1307 printf("MMC: SET_DSR failed\n"); 1308 } 1309 1310 /* Select the card, and put it into Transfer Mode */ 1311 if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */ 1312 cmd.cmdidx = MMC_CMD_SELECT_CARD; 1313 cmd.resp_type = MMC_RSP_R1; 1314 cmd.cmdarg = mmc->rca << 16; 1315 err = mmc_send_cmd(mmc, &cmd, NULL); 1316 1317 if (err) 1318 return err; 1319 } 1320 1321 /* 1322 * For SD, its erase group is always one sector 1323 */ 1324 mmc->erase_grp_size = 1; 1325 mmc->part_config = MMCPART_NOAVAILABLE; 1326 if (!IS_SD(mmc) && (mmc->version >= MMC_VERSION_4)) { 1327 /* check ext_csd version and capacity */ 1328 err = mmc_send_ext_csd(mmc, ext_csd); 1329 if (err) 1330 return err; 1331 if (ext_csd[EXT_CSD_REV] >= 2) { 1332 /* 1333 * According to the JEDEC Standard, the value of 1334 * ext_csd's capacity is valid if the value is more 1335 * than 2GB 1336 */ 1337 capacity = ext_csd[EXT_CSD_SEC_CNT] << 0 1338 | ext_csd[EXT_CSD_SEC_CNT + 1] << 8 1339 | ext_csd[EXT_CSD_SEC_CNT + 2] << 16 1340 | ext_csd[EXT_CSD_SEC_CNT + 3] << 24; 1341 capacity *= MMC_MAX_BLOCK_LEN; 1342 if ((capacity >> 20) > 2 * 1024) 1343 mmc->capacity_user = capacity; 1344 } 1345 1346 switch (ext_csd[EXT_CSD_REV]) { 1347 case 1: 1348 mmc->version = MMC_VERSION_4_1; 1349 break; 1350 case 2: 1351 mmc->version = MMC_VERSION_4_2; 1352 break; 1353 case 3: 1354 mmc->version = MMC_VERSION_4_3; 1355 break; 1356 case 5: 1357 mmc->version = MMC_VERSION_4_41; 1358 break; 1359 case 6: 1360 mmc->version = MMC_VERSION_4_5; 1361 break; 1362 case 7: 1363 mmc->version = MMC_VERSION_5_0; 1364 break; 1365 case 8: 1366 mmc->version = MMC_VERSION_5_1; 1367 break; 1368 } 1369 1370 /* The partition data may be non-zero but it is only 1371 * effective if PARTITION_SETTING_COMPLETED is set in 1372 * EXT_CSD, so ignore any data if this bit is not set, 1373 * except for enabling the high-capacity group size 1374 * definition (see below). */ 1375 part_completed = !!(ext_csd[EXT_CSD_PARTITION_SETTING] & 1376 EXT_CSD_PARTITION_SETTING_COMPLETED); 1377 1378 /* store the partition info of emmc */ 1379 mmc->part_support = ext_csd[EXT_CSD_PARTITIONING_SUPPORT]; 1380 if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) || 1381 ext_csd[EXT_CSD_BOOT_MULT]) 1382 mmc->part_config = ext_csd[EXT_CSD_PART_CONF]; 1383 if (part_completed && 1384 (ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & ENHNCD_SUPPORT)) 1385 mmc->part_attr = ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE]; 1386 1387 mmc->capacity_boot = ext_csd[EXT_CSD_BOOT_MULT] << 17; 1388 1389 mmc->capacity_rpmb = ext_csd[EXT_CSD_RPMB_MULT] << 17; 1390 1391 for (i = 0; i < 4; i++) { 1392 int idx = EXT_CSD_GP_SIZE_MULT + i * 3; 1393 uint mult = (ext_csd[idx + 2] << 16) + 1394 (ext_csd[idx + 1] << 8) + ext_csd[idx]; 1395 if (mult) 1396 has_parts = true; 1397 if (!part_completed) 1398 continue; 1399 mmc->capacity_gp[i] = mult; 1400 mmc->capacity_gp[i] *= 1401 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]; 1402 mmc->capacity_gp[i] *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE]; 1403 mmc->capacity_gp[i] <<= 19; 1404 } 1405 1406 if (part_completed) { 1407 mmc->enh_user_size = 1408 (ext_csd[EXT_CSD_ENH_SIZE_MULT+2] << 16) + 1409 (ext_csd[EXT_CSD_ENH_SIZE_MULT+1] << 8) + 1410 ext_csd[EXT_CSD_ENH_SIZE_MULT]; 1411 mmc->enh_user_size *= ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]; 1412 mmc->enh_user_size *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE]; 1413 mmc->enh_user_size <<= 19; 1414 mmc->enh_user_start = 1415 (ext_csd[EXT_CSD_ENH_START_ADDR+3] << 24) + 1416 (ext_csd[EXT_CSD_ENH_START_ADDR+2] << 16) + 1417 (ext_csd[EXT_CSD_ENH_START_ADDR+1] << 8) + 1418 ext_csd[EXT_CSD_ENH_START_ADDR]; 1419 if (mmc->high_capacity) 1420 mmc->enh_user_start <<= 9; 1421 } 1422 1423 /* 1424 * Host needs to enable ERASE_GRP_DEF bit if device is 1425 * partitioned. This bit will be lost every time after a reset 1426 * or power off. This will affect erase size. 1427 */ 1428 if (part_completed) 1429 has_parts = true; 1430 if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) && 1431 (ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE] & PART_ENH_ATTRIB)) 1432 has_parts = true; 1433 if (has_parts) { 1434 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, 1435 EXT_CSD_ERASE_GROUP_DEF, 1); 1436 1437 if (err) 1438 return err; 1439 else 1440 ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1; 1441 } 1442 1443 if (ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01) { 1444 /* Read out group size from ext_csd */ 1445 mmc->erase_grp_size = 1446 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024; 1447 /* 1448 * if high capacity and partition setting completed 1449 * SEC_COUNT is valid even if it is smaller than 2 GiB 1450 * JEDEC Standard JESD84-B45, 6.2.4 1451 */ 1452 if (mmc->high_capacity && part_completed) { 1453 capacity = (ext_csd[EXT_CSD_SEC_CNT]) | 1454 (ext_csd[EXT_CSD_SEC_CNT + 1] << 8) | 1455 (ext_csd[EXT_CSD_SEC_CNT + 2] << 16) | 1456 (ext_csd[EXT_CSD_SEC_CNT + 3] << 24); 1457 capacity *= MMC_MAX_BLOCK_LEN; 1458 mmc->capacity_user = capacity; 1459 } 1460 } else { 1461 /* Calculate the group size from the csd value. */ 1462 int erase_gsz, erase_gmul; 1463 erase_gsz = (mmc->csd[2] & 0x00007c00) >> 10; 1464 erase_gmul = (mmc->csd[2] & 0x000003e0) >> 5; 1465 mmc->erase_grp_size = (erase_gsz + 1) 1466 * (erase_gmul + 1); 1467 } 1468 1469 mmc->hc_wp_grp_size = 1024 1470 * ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] 1471 * ext_csd[EXT_CSD_HC_WP_GRP_SIZE]; 1472 1473 mmc->wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET]; 1474 } 1475 1476 err = mmc_set_capacity(mmc, mmc_get_blk_desc(mmc)->hwpart); 1477 if (err) 1478 return err; 1479 1480 if (IS_SD(mmc)) 1481 err = sd_change_freq(mmc); 1482 else 1483 err = mmc_change_freq(mmc); 1484 1485 if (err) 1486 return err; 1487 1488 /* Restrict card's capabilities by what the host can do */ 1489 mmc->card_caps &= mmc->cfg->host_caps; 1490 1491 if (IS_SD(mmc)) { 1492 if (mmc->card_caps & MMC_MODE_4BIT) { 1493 cmd.cmdidx = MMC_CMD_APP_CMD; 1494 cmd.resp_type = MMC_RSP_R1; 1495 cmd.cmdarg = mmc->rca << 16; 1496 1497 err = mmc_send_cmd(mmc, &cmd, NULL); 1498 if (err) 1499 return err; 1500 1501 cmd.cmdidx = SD_CMD_APP_SET_BUS_WIDTH; 1502 cmd.resp_type = MMC_RSP_R1; 1503 cmd.cmdarg = 2; 1504 err = mmc_send_cmd(mmc, &cmd, NULL); 1505 if (err) 1506 return err; 1507 1508 mmc_set_bus_width(mmc, 4); 1509 } 1510 1511 err = sd_read_ssr(mmc); 1512 if (err) 1513 return err; 1514 1515 if (mmc->card_caps & MMC_MODE_HS) 1516 mmc->tran_speed = 50000000; 1517 else 1518 mmc->tran_speed = 25000000; 1519 } else if (mmc->version >= MMC_VERSION_4) { 1520 /* Only version 4 of MMC supports wider bus widths */ 1521 int idx; 1522 1523 /* An array of possible bus widths in order of preference */ 1524 static unsigned ext_csd_bits[] = { 1525 EXT_CSD_DDR_BUS_WIDTH_8, 1526 EXT_CSD_DDR_BUS_WIDTH_4, 1527 EXT_CSD_BUS_WIDTH_8, 1528 EXT_CSD_BUS_WIDTH_4, 1529 EXT_CSD_BUS_WIDTH_1, 1530 }; 1531 1532 /* An array to map CSD bus widths to host cap bits */ 1533 static unsigned ext_to_hostcaps[] = { 1534 [EXT_CSD_DDR_BUS_WIDTH_4] = 1535 MMC_MODE_DDR_52MHz | MMC_MODE_4BIT, 1536 [EXT_CSD_DDR_BUS_WIDTH_8] = 1537 MMC_MODE_DDR_52MHz | MMC_MODE_8BIT, 1538 [EXT_CSD_BUS_WIDTH_4] = MMC_MODE_4BIT, 1539 [EXT_CSD_BUS_WIDTH_8] = MMC_MODE_8BIT, 1540 }; 1541 1542 /* An array to map chosen bus width to an integer */ 1543 static unsigned widths[] = { 1544 8, 4, 8, 4, 1, 1545 }; 1546 1547 for (idx=0; idx < ARRAY_SIZE(ext_csd_bits); idx++) { 1548 unsigned int extw = ext_csd_bits[idx]; 1549 unsigned int caps = ext_to_hostcaps[extw]; 1550 1551 /* 1552 * If the bus width is still not changed, 1553 * don't try to set the default again. 1554 * Otherwise, recover from switch attempts 1555 * by switching to 1-bit bus width. 1556 */ 1557 if (extw == EXT_CSD_BUS_WIDTH_1 && 1558 mmc->bus_width == 1) { 1559 err = 0; 1560 break; 1561 } 1562 1563 /* 1564 * Check to make sure the card and controller support 1565 * these capabilities 1566 */ 1567 if ((mmc->card_caps & caps) != caps) 1568 continue; 1569 1570 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, 1571 EXT_CSD_BUS_WIDTH, extw); 1572 1573 if (err) 1574 continue; 1575 1576 mmc->ddr_mode = (caps & MMC_MODE_DDR_52MHz) ? 1 : 0; 1577 mmc_set_bus_width(mmc, widths[idx]); 1578 1579 err = mmc_send_ext_csd(mmc, test_csd); 1580 1581 if (err) 1582 continue; 1583 1584 /* Only compare read only fields */ 1585 if (ext_csd[EXT_CSD_PARTITIONING_SUPPORT] 1586 == test_csd[EXT_CSD_PARTITIONING_SUPPORT] && 1587 ext_csd[EXT_CSD_HC_WP_GRP_SIZE] 1588 == test_csd[EXT_CSD_HC_WP_GRP_SIZE] && 1589 ext_csd[EXT_CSD_REV] 1590 == test_csd[EXT_CSD_REV] && 1591 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] 1592 == test_csd[EXT_CSD_HC_ERASE_GRP_SIZE] && 1593 memcmp(&ext_csd[EXT_CSD_SEC_CNT], 1594 &test_csd[EXT_CSD_SEC_CNT], 4) == 0) 1595 break; 1596 else 1597 err = -EBADMSG; 1598 } 1599 1600 if (err) 1601 return err; 1602 1603 if (mmc->card_caps & MMC_MODE_HS) { 1604 if (mmc->card_caps & MMC_MODE_HS_52MHz) 1605 mmc->tran_speed = 52000000; 1606 else 1607 mmc->tran_speed = 26000000; 1608 } 1609 } 1610 1611 mmc_set_clock(mmc, mmc->tran_speed); 1612 1613 /* Fix the block length for DDR mode */ 1614 if (mmc->ddr_mode) { 1615 mmc->read_bl_len = MMC_MAX_BLOCK_LEN; 1616 mmc->write_bl_len = MMC_MAX_BLOCK_LEN; 1617 } 1618 1619 /* fill in device description */ 1620 bdesc = mmc_get_blk_desc(mmc); 1621 bdesc->lun = 0; 1622 bdesc->hwpart = 0; 1623 bdesc->type = 0; 1624 bdesc->blksz = mmc->read_bl_len; 1625 bdesc->log2blksz = LOG2(bdesc->blksz); 1626 bdesc->lba = lldiv(mmc->capacity, mmc->read_bl_len); 1627 #if !defined(CONFIG_SPL_BUILD) || \ 1628 (defined(CONFIG_SPL_LIBCOMMON_SUPPORT) && \ 1629 !defined(CONFIG_USE_TINY_PRINTF)) 1630 sprintf(bdesc->vendor, "Man %06x Snr %04x%04x", 1631 mmc->cid[0] >> 24, (mmc->cid[2] & 0xffff), 1632 (mmc->cid[3] >> 16) & 0xffff); 1633 sprintf(bdesc->product, "%c%c%c%c%c%c", mmc->cid[0] & 0xff, 1634 (mmc->cid[1] >> 24), (mmc->cid[1] >> 16) & 0xff, 1635 (mmc->cid[1] >> 8) & 0xff, mmc->cid[1] & 0xff, 1636 (mmc->cid[2] >> 24) & 0xff); 1637 sprintf(bdesc->revision, "%d.%d", (mmc->cid[2] >> 20) & 0xf, 1638 (mmc->cid[2] >> 16) & 0xf); 1639 #else 1640 bdesc->vendor[0] = 0; 1641 bdesc->product[0] = 0; 1642 bdesc->revision[0] = 0; 1643 #endif 1644 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBDISK_SUPPORT) 1645 part_init(bdesc); 1646 #endif 1647 1648 return 0; 1649 } 1650 1651 static int mmc_send_if_cond(struct mmc *mmc) 1652 { 1653 struct mmc_cmd cmd; 1654 int err; 1655 1656 cmd.cmdidx = SD_CMD_SEND_IF_COND; 1657 /* We set the bit if the host supports voltages between 2.7 and 3.6 V */ 1658 cmd.cmdarg = ((mmc->cfg->voltages & 0xff8000) != 0) << 8 | 0xaa; 1659 cmd.resp_type = MMC_RSP_R7; 1660 1661 err = mmc_send_cmd(mmc, &cmd, NULL); 1662 1663 if (err) 1664 return err; 1665 1666 if ((cmd.response[0] & 0xff) != 0xaa) 1667 return -EOPNOTSUPP; 1668 else 1669 mmc->version = SD_VERSION_2; 1670 1671 return 0; 1672 } 1673 1674 #if !CONFIG_IS_ENABLED(DM_MMC) 1675 /* board-specific MMC power initializations. */ 1676 __weak void board_mmc_power_init(void) 1677 { 1678 } 1679 #endif 1680 1681 static int mmc_power_init(struct mmc *mmc) 1682 { 1683 #if CONFIG_IS_ENABLED(DM_MMC) 1684 #if defined(CONFIG_DM_REGULATOR) && !defined(CONFIG_SPL_BUILD) 1685 struct udevice *vmmc_supply; 1686 int ret; 1687 1688 ret = device_get_supply_regulator(mmc->dev, "vmmc-supply", 1689 &vmmc_supply); 1690 if (ret) { 1691 debug("%s: No vmmc supply\n", mmc->dev->name); 1692 return 0; 1693 } 1694 1695 ret = regulator_set_enable(vmmc_supply, true); 1696 if (ret) { 1697 puts("Error enabling VMMC supply\n"); 1698 return ret; 1699 } 1700 #endif 1701 #else /* !CONFIG_DM_MMC */ 1702 /* 1703 * Driver model should use a regulator, as above, rather than calling 1704 * out to board code. 1705 */ 1706 board_mmc_power_init(); 1707 #endif 1708 return 0; 1709 } 1710 1711 int mmc_start_init(struct mmc *mmc) 1712 { 1713 bool no_card; 1714 int err; 1715 1716 /* we pretend there's no card when init is NULL */ 1717 no_card = mmc_getcd(mmc) == 0; 1718 #if !CONFIG_IS_ENABLED(DM_MMC) 1719 no_card = no_card || (mmc->cfg->ops->init == NULL); 1720 #endif 1721 if (no_card) { 1722 mmc->has_init = 0; 1723 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) 1724 printf("MMC: no card present\n"); 1725 #endif 1726 return -ENOMEDIUM; 1727 } 1728 1729 if (mmc->has_init) 1730 return 0; 1731 1732 #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT 1733 mmc_adapter_card_type_ident(); 1734 #endif 1735 err = mmc_power_init(mmc); 1736 if (err) 1737 return err; 1738 1739 #if CONFIG_IS_ENABLED(DM_MMC) 1740 /* The device has already been probed ready for use */ 1741 #else 1742 /* made sure it's not NULL earlier */ 1743 err = mmc->cfg->ops->init(mmc); 1744 if (err) 1745 return err; 1746 #endif 1747 mmc->ddr_mode = 0; 1748 mmc_set_bus_width(mmc, 1); 1749 mmc_set_clock(mmc, 1); 1750 mmc_set_timing(mmc, MMC_TIMING_LEGACY); 1751 1752 /* Reset the Card */ 1753 err = mmc_go_idle(mmc); 1754 1755 if (err) 1756 return err; 1757 1758 /* The internal partition reset to user partition(0) at every CMD0*/ 1759 mmc_get_blk_desc(mmc)->hwpart = 0; 1760 1761 /* Test for SD version 2 */ 1762 err = mmc_send_if_cond(mmc); 1763 1764 /* Now try to get the SD card's operating condition */ 1765 err = sd_send_op_cond(mmc); 1766 1767 /* If the command timed out, we check for an MMC card */ 1768 if (err == -ETIMEDOUT) { 1769 err = mmc_send_op_cond(mmc); 1770 1771 if (err) { 1772 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) 1773 printf("Card did not respond to voltage select!\n"); 1774 #endif 1775 return -EOPNOTSUPP; 1776 } 1777 } 1778 1779 if (!err) 1780 mmc->init_in_progress = 1; 1781 1782 return err; 1783 } 1784 1785 static int mmc_complete_init(struct mmc *mmc) 1786 { 1787 int err = 0; 1788 1789 mmc->init_in_progress = 0; 1790 if (mmc->op_cond_pending) 1791 err = mmc_complete_op_cond(mmc); 1792 1793 if (!err) 1794 err = mmc_startup(mmc); 1795 if (err) 1796 mmc->has_init = 0; 1797 else 1798 mmc->has_init = 1; 1799 return err; 1800 } 1801 1802 int mmc_init(struct mmc *mmc) 1803 { 1804 int err = 0; 1805 __maybe_unused unsigned start; 1806 #if CONFIG_IS_ENABLED(DM_MMC) 1807 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(mmc->dev); 1808 1809 upriv->mmc = mmc; 1810 #endif 1811 if (mmc->has_init) 1812 return 0; 1813 1814 start = get_timer(0); 1815 1816 if (!mmc->init_in_progress) 1817 err = mmc_start_init(mmc); 1818 1819 if (!err) 1820 err = mmc_complete_init(mmc); 1821 if (err) 1822 printf("%s: %d, time %lu\n", __func__, err, get_timer(start)); 1823 1824 return err; 1825 } 1826 1827 int mmc_set_dsr(struct mmc *mmc, u16 val) 1828 { 1829 mmc->dsr = val; 1830 return 0; 1831 } 1832 1833 /* CPU-specific MMC initializations */ 1834 __weak int cpu_mmc_init(bd_t *bis) 1835 { 1836 return -1; 1837 } 1838 1839 /* board-specific MMC initializations. */ 1840 __weak int board_mmc_init(bd_t *bis) 1841 { 1842 return -1; 1843 } 1844 1845 void mmc_set_preinit(struct mmc *mmc, int preinit) 1846 { 1847 mmc->preinit = preinit; 1848 } 1849 1850 #if CONFIG_IS_ENABLED(DM_MMC) && defined(CONFIG_SPL_BUILD) 1851 static int mmc_probe(bd_t *bis) 1852 { 1853 return 0; 1854 } 1855 #elif CONFIG_IS_ENABLED(DM_MMC) 1856 static int mmc_probe(bd_t *bis) 1857 { 1858 int ret, i; 1859 struct uclass *uc; 1860 struct udevice *dev; 1861 1862 ret = uclass_get(UCLASS_MMC, &uc); 1863 if (ret) 1864 return ret; 1865 1866 /* 1867 * Try to add them in sequence order. Really with driver model we 1868 * should allow holes, but the current MMC list does not allow that. 1869 * So if we request 0, 1, 3 we will get 0, 1, 2. 1870 */ 1871 for (i = 0; ; i++) { 1872 ret = uclass_get_device_by_seq(UCLASS_MMC, i, &dev); 1873 if (ret == -ENODEV) 1874 break; 1875 } 1876 uclass_foreach_dev(dev, uc) { 1877 ret = device_probe(dev); 1878 if (ret) 1879 printf("%s - probe failed: %d\n", dev->name, ret); 1880 } 1881 1882 return 0; 1883 } 1884 #else 1885 static int mmc_probe(bd_t *bis) 1886 { 1887 if (board_mmc_init(bis) < 0) 1888 cpu_mmc_init(bis); 1889 1890 return 0; 1891 } 1892 #endif 1893 1894 int mmc_initialize(bd_t *bis) 1895 { 1896 static int initialized = 0; 1897 int ret; 1898 if (initialized) /* Avoid initializing mmc multiple times */ 1899 return 0; 1900 initialized = 1; 1901 1902 #if !CONFIG_IS_ENABLED(BLK) 1903 #if !CONFIG_IS_ENABLED(MMC_TINY) 1904 mmc_list_init(); 1905 #endif 1906 #endif 1907 ret = mmc_probe(bis); 1908 if (ret) 1909 return ret; 1910 1911 #ifndef CONFIG_SPL_BUILD 1912 print_mmc_devices(','); 1913 #endif 1914 1915 mmc_do_preinit(); 1916 return 0; 1917 } 1918 1919 #ifdef CONFIG_CMD_BKOPS_ENABLE 1920 int mmc_set_bkops_enable(struct mmc *mmc) 1921 { 1922 int err; 1923 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN); 1924 1925 err = mmc_send_ext_csd(mmc, ext_csd); 1926 if (err) { 1927 puts("Could not get ext_csd register values\n"); 1928 return err; 1929 } 1930 1931 if (!(ext_csd[EXT_CSD_BKOPS_SUPPORT] & 0x1)) { 1932 puts("Background operations not supported on device\n"); 1933 return -EMEDIUMTYPE; 1934 } 1935 1936 if (ext_csd[EXT_CSD_BKOPS_EN] & 0x1) { 1937 puts("Background operations already enabled\n"); 1938 return 0; 1939 } 1940 1941 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BKOPS_EN, 1); 1942 if (err) { 1943 puts("Failed to enable manual background operations\n"); 1944 return err; 1945 } 1946 1947 puts("Enabled manual background operations\n"); 1948 1949 return 0; 1950 } 1951 #endif 1952