1 /* 2 * Copyright 2008, Freescale Semiconductor, Inc 3 * Andy Fleming 4 * 5 * Based vaguely on the Linux code 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #include <config.h> 11 #include <common.h> 12 #include <command.h> 13 #include <dm.h> 14 #include <dm/device-internal.h> 15 #include <errno.h> 16 #include <mmc.h> 17 #include <part.h> 18 #include <malloc.h> 19 #include <memalign.h> 20 #include <linux/list.h> 21 #include <div64.h> 22 #include "mmc_private.h" 23 24 __weak int board_mmc_getwp(struct mmc *mmc) 25 { 26 return -1; 27 } 28 29 int mmc_getwp(struct mmc *mmc) 30 { 31 int wp; 32 33 wp = board_mmc_getwp(mmc); 34 35 if (wp < 0) { 36 if (mmc->cfg->ops->getwp) 37 wp = mmc->cfg->ops->getwp(mmc); 38 else 39 wp = 0; 40 } 41 42 return wp; 43 } 44 45 __weak int board_mmc_getcd(struct mmc *mmc) 46 { 47 return -1; 48 } 49 50 int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) 51 { 52 int ret; 53 54 #ifdef CONFIG_MMC_TRACE 55 int i; 56 u8 *ptr; 57 58 printf("CMD_SEND:%d\n", cmd->cmdidx); 59 printf("\t\tARG\t\t\t 0x%08X\n", cmd->cmdarg); 60 ret = mmc->cfg->ops->send_cmd(mmc, cmd, data); 61 if (ret) { 62 printf("\t\tRET\t\t\t %d\n", ret); 63 } else { 64 switch (cmd->resp_type) { 65 case MMC_RSP_NONE: 66 printf("\t\tMMC_RSP_NONE\n"); 67 break; 68 case MMC_RSP_R1: 69 printf("\t\tMMC_RSP_R1,5,6,7 \t 0x%08X \n", 70 cmd->response[0]); 71 break; 72 case MMC_RSP_R1b: 73 printf("\t\tMMC_RSP_R1b\t\t 0x%08X \n", 74 cmd->response[0]); 75 break; 76 case MMC_RSP_R2: 77 printf("\t\tMMC_RSP_R2\t\t 0x%08X \n", 78 cmd->response[0]); 79 printf("\t\t \t\t 0x%08X \n", 80 cmd->response[1]); 81 printf("\t\t \t\t 0x%08X \n", 82 cmd->response[2]); 83 printf("\t\t \t\t 0x%08X \n", 84 cmd->response[3]); 85 printf("\n"); 86 printf("\t\t\t\t\tDUMPING DATA\n"); 87 for (i = 0; i < 4; i++) { 88 int j; 89 printf("\t\t\t\t\t%03d - ", i*4); 90 ptr = (u8 *)&cmd->response[i]; 91 ptr += 3; 92 for (j = 0; j < 4; j++) 93 printf("%02X ", *ptr--); 94 printf("\n"); 95 } 96 break; 97 case MMC_RSP_R3: 98 printf("\t\tMMC_RSP_R3,4\t\t 0x%08X \n", 99 cmd->response[0]); 100 break; 101 default: 102 printf("\t\tERROR MMC rsp not supported\n"); 103 break; 104 } 105 } 106 #else 107 ret = mmc->cfg->ops->send_cmd(mmc, cmd, data); 108 #endif 109 return ret; 110 } 111 112 int mmc_send_status(struct mmc *mmc, int timeout) 113 { 114 struct mmc_cmd cmd; 115 int err, retries = 5; 116 #ifdef CONFIG_MMC_TRACE 117 int status; 118 #endif 119 120 cmd.cmdidx = MMC_CMD_SEND_STATUS; 121 cmd.resp_type = MMC_RSP_R1; 122 if (!mmc_host_is_spi(mmc)) 123 cmd.cmdarg = mmc->rca << 16; 124 125 while (1) { 126 err = mmc_send_cmd(mmc, &cmd, NULL); 127 if (!err) { 128 if ((cmd.response[0] & MMC_STATUS_RDY_FOR_DATA) && 129 (cmd.response[0] & MMC_STATUS_CURR_STATE) != 130 MMC_STATE_PRG) 131 break; 132 else if (cmd.response[0] & MMC_STATUS_MASK) { 133 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) 134 printf("Status Error: 0x%08X\n", 135 cmd.response[0]); 136 #endif 137 return COMM_ERR; 138 } 139 } else if (--retries < 0) 140 return err; 141 142 if (timeout-- <= 0) 143 break; 144 145 udelay(1000); 146 } 147 148 #ifdef CONFIG_MMC_TRACE 149 status = (cmd.response[0] & MMC_STATUS_CURR_STATE) >> 9; 150 printf("CURR STATE:%d\n", status); 151 #endif 152 if (timeout <= 0) { 153 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) 154 printf("Timeout waiting card ready\n"); 155 #endif 156 return TIMEOUT; 157 } 158 159 return 0; 160 } 161 162 int mmc_set_blocklen(struct mmc *mmc, int len) 163 { 164 struct mmc_cmd cmd; 165 166 if (mmc->ddr_mode) 167 return 0; 168 169 cmd.cmdidx = MMC_CMD_SET_BLOCKLEN; 170 cmd.resp_type = MMC_RSP_R1; 171 cmd.cmdarg = len; 172 173 return mmc_send_cmd(mmc, &cmd, NULL); 174 } 175 176 static int mmc_read_blocks(struct mmc *mmc, void *dst, lbaint_t start, 177 lbaint_t blkcnt) 178 { 179 struct mmc_cmd cmd; 180 struct mmc_data data; 181 182 if (blkcnt > 1) 183 cmd.cmdidx = MMC_CMD_READ_MULTIPLE_BLOCK; 184 else 185 cmd.cmdidx = MMC_CMD_READ_SINGLE_BLOCK; 186 187 if (mmc->high_capacity) 188 cmd.cmdarg = start; 189 else 190 cmd.cmdarg = start * mmc->read_bl_len; 191 192 cmd.resp_type = MMC_RSP_R1; 193 194 data.dest = dst; 195 data.blocks = blkcnt; 196 data.blocksize = mmc->read_bl_len; 197 data.flags = MMC_DATA_READ; 198 199 if (mmc_send_cmd(mmc, &cmd, &data)) 200 return 0; 201 202 if (blkcnt > 1) { 203 cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION; 204 cmd.cmdarg = 0; 205 cmd.resp_type = MMC_RSP_R1b; 206 if (mmc_send_cmd(mmc, &cmd, NULL)) { 207 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) 208 printf("mmc fail to send stop cmd\n"); 209 #endif 210 return 0; 211 } 212 } 213 214 return blkcnt; 215 } 216 217 #ifdef CONFIG_BLK 218 ulong mmc_bread(struct udevice *dev, lbaint_t start, lbaint_t blkcnt, void *dst) 219 #else 220 ulong mmc_bread(struct blk_desc *block_dev, lbaint_t start, lbaint_t blkcnt, 221 void *dst) 222 #endif 223 { 224 #ifdef CONFIG_BLK 225 struct blk_desc *block_dev = dev_get_uclass_platdata(dev); 226 #endif 227 int dev_num = block_dev->devnum; 228 int err; 229 lbaint_t cur, blocks_todo = blkcnt; 230 231 if (blkcnt == 0) 232 return 0; 233 234 struct mmc *mmc = find_mmc_device(dev_num); 235 if (!mmc) 236 return 0; 237 238 err = blk_dselect_hwpart(block_dev, block_dev->hwpart); 239 if (err < 0) 240 return 0; 241 242 if ((start + blkcnt) > block_dev->lba) { 243 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) 244 printf("MMC: block number 0x" LBAF " exceeds max(0x" LBAF ")\n", 245 start + blkcnt, block_dev->lba); 246 #endif 247 return 0; 248 } 249 250 if (mmc_set_blocklen(mmc, mmc->read_bl_len)) { 251 debug("%s: Failed to set blocklen\n", __func__); 252 return 0; 253 } 254 255 do { 256 cur = (blocks_todo > mmc->cfg->b_max) ? 257 mmc->cfg->b_max : blocks_todo; 258 if (mmc_read_blocks(mmc, dst, start, cur) != cur) { 259 debug("%s: Failed to read blocks\n", __func__); 260 return 0; 261 } 262 blocks_todo -= cur; 263 start += cur; 264 dst += cur * mmc->read_bl_len; 265 } while (blocks_todo > 0); 266 267 return blkcnt; 268 } 269 270 static int mmc_go_idle(struct mmc *mmc) 271 { 272 struct mmc_cmd cmd; 273 int err; 274 275 udelay(1000); 276 277 cmd.cmdidx = MMC_CMD_GO_IDLE_STATE; 278 cmd.cmdarg = 0; 279 cmd.resp_type = MMC_RSP_NONE; 280 281 err = mmc_send_cmd(mmc, &cmd, NULL); 282 283 if (err) 284 return err; 285 286 udelay(2000); 287 288 return 0; 289 } 290 291 static int sd_send_op_cond(struct mmc *mmc) 292 { 293 int timeout = 1000; 294 int err; 295 struct mmc_cmd cmd; 296 297 while (1) { 298 cmd.cmdidx = MMC_CMD_APP_CMD; 299 cmd.resp_type = MMC_RSP_R1; 300 cmd.cmdarg = 0; 301 302 err = mmc_send_cmd(mmc, &cmd, NULL); 303 304 if (err) 305 return err; 306 307 cmd.cmdidx = SD_CMD_APP_SEND_OP_COND; 308 cmd.resp_type = MMC_RSP_R3; 309 310 /* 311 * Most cards do not answer if some reserved bits 312 * in the ocr are set. However, Some controller 313 * can set bit 7 (reserved for low voltages), but 314 * how to manage low voltages SD card is not yet 315 * specified. 316 */ 317 cmd.cmdarg = mmc_host_is_spi(mmc) ? 0 : 318 (mmc->cfg->voltages & 0xff8000); 319 320 if (mmc->version == SD_VERSION_2) 321 cmd.cmdarg |= OCR_HCS; 322 323 err = mmc_send_cmd(mmc, &cmd, NULL); 324 325 if (err) 326 return err; 327 328 if (cmd.response[0] & OCR_BUSY) 329 break; 330 331 if (timeout-- <= 0) 332 return UNUSABLE_ERR; 333 334 udelay(1000); 335 } 336 337 if (mmc->version != SD_VERSION_2) 338 mmc->version = SD_VERSION_1_0; 339 340 if (mmc_host_is_spi(mmc)) { /* read OCR for spi */ 341 cmd.cmdidx = MMC_CMD_SPI_READ_OCR; 342 cmd.resp_type = MMC_RSP_R3; 343 cmd.cmdarg = 0; 344 345 err = mmc_send_cmd(mmc, &cmd, NULL); 346 347 if (err) 348 return err; 349 } 350 351 mmc->ocr = cmd.response[0]; 352 353 mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS); 354 mmc->rca = 0; 355 356 return 0; 357 } 358 359 static int mmc_send_op_cond_iter(struct mmc *mmc, int use_arg) 360 { 361 struct mmc_cmd cmd; 362 int err; 363 364 cmd.cmdidx = MMC_CMD_SEND_OP_COND; 365 cmd.resp_type = MMC_RSP_R3; 366 cmd.cmdarg = 0; 367 if (use_arg && !mmc_host_is_spi(mmc)) 368 cmd.cmdarg = OCR_HCS | 369 (mmc->cfg->voltages & 370 (mmc->ocr & OCR_VOLTAGE_MASK)) | 371 (mmc->ocr & OCR_ACCESS_MODE); 372 373 err = mmc_send_cmd(mmc, &cmd, NULL); 374 if (err) 375 return err; 376 mmc->ocr = cmd.response[0]; 377 return 0; 378 } 379 380 static int mmc_send_op_cond(struct mmc *mmc) 381 { 382 int err, i; 383 384 /* Some cards seem to need this */ 385 mmc_go_idle(mmc); 386 387 /* Asking to the card its capabilities */ 388 for (i = 0; i < 2; i++) { 389 err = mmc_send_op_cond_iter(mmc, i != 0); 390 if (err) 391 return err; 392 393 /* exit if not busy (flag seems to be inverted) */ 394 if (mmc->ocr & OCR_BUSY) 395 break; 396 } 397 mmc->op_cond_pending = 1; 398 return 0; 399 } 400 401 static int mmc_complete_op_cond(struct mmc *mmc) 402 { 403 struct mmc_cmd cmd; 404 int timeout = 1000; 405 uint start; 406 int err; 407 408 mmc->op_cond_pending = 0; 409 if (!(mmc->ocr & OCR_BUSY)) { 410 start = get_timer(0); 411 while (1) { 412 err = mmc_send_op_cond_iter(mmc, 1); 413 if (err) 414 return err; 415 if (mmc->ocr & OCR_BUSY) 416 break; 417 if (get_timer(start) > timeout) 418 return UNUSABLE_ERR; 419 udelay(100); 420 } 421 } 422 423 if (mmc_host_is_spi(mmc)) { /* read OCR for spi */ 424 cmd.cmdidx = MMC_CMD_SPI_READ_OCR; 425 cmd.resp_type = MMC_RSP_R3; 426 cmd.cmdarg = 0; 427 428 err = mmc_send_cmd(mmc, &cmd, NULL); 429 430 if (err) 431 return err; 432 433 mmc->ocr = cmd.response[0]; 434 } 435 436 mmc->version = MMC_VERSION_UNKNOWN; 437 438 mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS); 439 mmc->rca = 1; 440 441 return 0; 442 } 443 444 445 static int mmc_send_ext_csd(struct mmc *mmc, u8 *ext_csd) 446 { 447 struct mmc_cmd cmd; 448 struct mmc_data data; 449 int err; 450 451 /* Get the Card Status Register */ 452 cmd.cmdidx = MMC_CMD_SEND_EXT_CSD; 453 cmd.resp_type = MMC_RSP_R1; 454 cmd.cmdarg = 0; 455 456 data.dest = (char *)ext_csd; 457 data.blocks = 1; 458 data.blocksize = MMC_MAX_BLOCK_LEN; 459 data.flags = MMC_DATA_READ; 460 461 err = mmc_send_cmd(mmc, &cmd, &data); 462 463 return err; 464 } 465 466 467 static int mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value) 468 { 469 struct mmc_cmd cmd; 470 int timeout = 1000; 471 int ret; 472 473 cmd.cmdidx = MMC_CMD_SWITCH; 474 cmd.resp_type = MMC_RSP_R1b; 475 cmd.cmdarg = (MMC_SWITCH_MODE_WRITE_BYTE << 24) | 476 (index << 16) | 477 (value << 8); 478 479 ret = mmc_send_cmd(mmc, &cmd, NULL); 480 481 /* Waiting for the ready status */ 482 if (!ret) 483 ret = mmc_send_status(mmc, timeout); 484 485 return ret; 486 487 } 488 489 static int mmc_change_freq(struct mmc *mmc) 490 { 491 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN); 492 char cardtype; 493 int err; 494 495 mmc->card_caps = 0; 496 497 if (mmc_host_is_spi(mmc)) 498 return 0; 499 500 /* Only version 4 supports high-speed */ 501 if (mmc->version < MMC_VERSION_4) 502 return 0; 503 504 mmc->card_caps |= MMC_MODE_4BIT | MMC_MODE_8BIT; 505 506 err = mmc_send_ext_csd(mmc, ext_csd); 507 508 if (err) 509 return err; 510 511 cardtype = ext_csd[EXT_CSD_CARD_TYPE] & 0xf; 512 513 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_HS_TIMING, 1); 514 515 if (err) 516 return err; 517 518 /* Now check to see that it worked */ 519 err = mmc_send_ext_csd(mmc, ext_csd); 520 521 if (err) 522 return err; 523 524 /* No high-speed support */ 525 if (!ext_csd[EXT_CSD_HS_TIMING]) 526 return 0; 527 528 /* High Speed is set, there are two types: 52MHz and 26MHz */ 529 if (cardtype & EXT_CSD_CARD_TYPE_52) { 530 if (cardtype & EXT_CSD_CARD_TYPE_DDR_1_8V) 531 mmc->card_caps |= MMC_MODE_DDR_52MHz; 532 mmc->card_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS; 533 } else { 534 mmc->card_caps |= MMC_MODE_HS; 535 } 536 537 return 0; 538 } 539 540 static int mmc_set_capacity(struct mmc *mmc, int part_num) 541 { 542 switch (part_num) { 543 case 0: 544 mmc->capacity = mmc->capacity_user; 545 break; 546 case 1: 547 case 2: 548 mmc->capacity = mmc->capacity_boot; 549 break; 550 case 3: 551 mmc->capacity = mmc->capacity_rpmb; 552 break; 553 case 4: 554 case 5: 555 case 6: 556 case 7: 557 mmc->capacity = mmc->capacity_gp[part_num - 4]; 558 break; 559 default: 560 return -1; 561 } 562 563 mmc_get_blk_desc(mmc)->lba = lldiv(mmc->capacity, mmc->read_bl_len); 564 565 return 0; 566 } 567 568 int mmc_switch_part(struct mmc *mmc, unsigned int part_num) 569 { 570 int ret; 571 572 ret = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_PART_CONF, 573 (mmc->part_config & ~PART_ACCESS_MASK) 574 | (part_num & PART_ACCESS_MASK)); 575 576 /* 577 * Set the capacity if the switch succeeded or was intended 578 * to return to representing the raw device. 579 */ 580 if ((ret == 0) || ((ret == -ENODEV) && (part_num == 0))) { 581 ret = mmc_set_capacity(mmc, part_num); 582 mmc_get_blk_desc(mmc)->hwpart = part_num; 583 } 584 585 return ret; 586 } 587 588 #ifdef CONFIG_BLK 589 static int mmc_select_hwpart(struct udevice *bdev, int hwpart) 590 { 591 struct udevice *mmc_dev = dev_get_parent(bdev); 592 struct mmc *mmc = mmc_get_mmc_dev(mmc_dev); 593 struct blk_desc *desc = dev_get_uclass_platdata(bdev); 594 int ret; 595 596 if (desc->hwpart == hwpart) 597 return 0; 598 599 if (mmc->part_config == MMCPART_NOAVAILABLE) 600 return -EMEDIUMTYPE; 601 602 ret = mmc_switch_part(mmc, hwpart); 603 if (ret) 604 return ret; 605 606 return 0; 607 } 608 #else 609 static int mmc_select_hwpartp(struct blk_desc *desc, int hwpart) 610 { 611 struct mmc *mmc = find_mmc_device(desc->devnum); 612 int ret; 613 614 if (!mmc) 615 return -ENODEV; 616 617 if (mmc->block_dev.hwpart == hwpart) 618 return 0; 619 620 if (mmc->part_config == MMCPART_NOAVAILABLE) 621 return -EMEDIUMTYPE; 622 623 ret = mmc_switch_part(mmc, hwpart); 624 if (ret) 625 return ret; 626 627 return 0; 628 } 629 #endif 630 631 int mmc_hwpart_config(struct mmc *mmc, 632 const struct mmc_hwpart_conf *conf, 633 enum mmc_hwpart_conf_mode mode) 634 { 635 u8 part_attrs = 0; 636 u32 enh_size_mult; 637 u32 enh_start_addr; 638 u32 gp_size_mult[4]; 639 u32 max_enh_size_mult; 640 u32 tot_enh_size_mult = 0; 641 u8 wr_rel_set; 642 int i, pidx, err; 643 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN); 644 645 if (mode < MMC_HWPART_CONF_CHECK || mode > MMC_HWPART_CONF_COMPLETE) 646 return -EINVAL; 647 648 if (IS_SD(mmc) || (mmc->version < MMC_VERSION_4_41)) { 649 printf("eMMC >= 4.4 required for enhanced user data area\n"); 650 return -EMEDIUMTYPE; 651 } 652 653 if (!(mmc->part_support & PART_SUPPORT)) { 654 printf("Card does not support partitioning\n"); 655 return -EMEDIUMTYPE; 656 } 657 658 if (!mmc->hc_wp_grp_size) { 659 printf("Card does not define HC WP group size\n"); 660 return -EMEDIUMTYPE; 661 } 662 663 /* check partition alignment and total enhanced size */ 664 if (conf->user.enh_size) { 665 if (conf->user.enh_size % mmc->hc_wp_grp_size || 666 conf->user.enh_start % mmc->hc_wp_grp_size) { 667 printf("User data enhanced area not HC WP group " 668 "size aligned\n"); 669 return -EINVAL; 670 } 671 part_attrs |= EXT_CSD_ENH_USR; 672 enh_size_mult = conf->user.enh_size / mmc->hc_wp_grp_size; 673 if (mmc->high_capacity) { 674 enh_start_addr = conf->user.enh_start; 675 } else { 676 enh_start_addr = (conf->user.enh_start << 9); 677 } 678 } else { 679 enh_size_mult = 0; 680 enh_start_addr = 0; 681 } 682 tot_enh_size_mult += enh_size_mult; 683 684 for (pidx = 0; pidx < 4; pidx++) { 685 if (conf->gp_part[pidx].size % mmc->hc_wp_grp_size) { 686 printf("GP%i partition not HC WP group size " 687 "aligned\n", pidx+1); 688 return -EINVAL; 689 } 690 gp_size_mult[pidx] = conf->gp_part[pidx].size / mmc->hc_wp_grp_size; 691 if (conf->gp_part[pidx].size && conf->gp_part[pidx].enhanced) { 692 part_attrs |= EXT_CSD_ENH_GP(pidx); 693 tot_enh_size_mult += gp_size_mult[pidx]; 694 } 695 } 696 697 if (part_attrs && ! (mmc->part_support & ENHNCD_SUPPORT)) { 698 printf("Card does not support enhanced attribute\n"); 699 return -EMEDIUMTYPE; 700 } 701 702 err = mmc_send_ext_csd(mmc, ext_csd); 703 if (err) 704 return err; 705 706 max_enh_size_mult = 707 (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+2] << 16) + 708 (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+1] << 8) + 709 ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT]; 710 if (tot_enh_size_mult > max_enh_size_mult) { 711 printf("Total enhanced size exceeds maximum (%u > %u)\n", 712 tot_enh_size_mult, max_enh_size_mult); 713 return -EMEDIUMTYPE; 714 } 715 716 /* The default value of EXT_CSD_WR_REL_SET is device 717 * dependent, the values can only be changed if the 718 * EXT_CSD_HS_CTRL_REL bit is set. The values can be 719 * changed only once and before partitioning is completed. */ 720 wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET]; 721 if (conf->user.wr_rel_change) { 722 if (conf->user.wr_rel_set) 723 wr_rel_set |= EXT_CSD_WR_DATA_REL_USR; 724 else 725 wr_rel_set &= ~EXT_CSD_WR_DATA_REL_USR; 726 } 727 for (pidx = 0; pidx < 4; pidx++) { 728 if (conf->gp_part[pidx].wr_rel_change) { 729 if (conf->gp_part[pidx].wr_rel_set) 730 wr_rel_set |= EXT_CSD_WR_DATA_REL_GP(pidx); 731 else 732 wr_rel_set &= ~EXT_CSD_WR_DATA_REL_GP(pidx); 733 } 734 } 735 736 if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET] && 737 !(ext_csd[EXT_CSD_WR_REL_PARAM] & EXT_CSD_HS_CTRL_REL)) { 738 puts("Card does not support host controlled partition write " 739 "reliability settings\n"); 740 return -EMEDIUMTYPE; 741 } 742 743 if (ext_csd[EXT_CSD_PARTITION_SETTING] & 744 EXT_CSD_PARTITION_SETTING_COMPLETED) { 745 printf("Card already partitioned\n"); 746 return -EPERM; 747 } 748 749 if (mode == MMC_HWPART_CONF_CHECK) 750 return 0; 751 752 /* Partitioning requires high-capacity size definitions */ 753 if (!(ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01)) { 754 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, 755 EXT_CSD_ERASE_GROUP_DEF, 1); 756 757 if (err) 758 return err; 759 760 ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1; 761 762 /* update erase group size to be high-capacity */ 763 mmc->erase_grp_size = 764 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024; 765 766 } 767 768 /* all OK, write the configuration */ 769 for (i = 0; i < 4; i++) { 770 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, 771 EXT_CSD_ENH_START_ADDR+i, 772 (enh_start_addr >> (i*8)) & 0xFF); 773 if (err) 774 return err; 775 } 776 for (i = 0; i < 3; i++) { 777 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, 778 EXT_CSD_ENH_SIZE_MULT+i, 779 (enh_size_mult >> (i*8)) & 0xFF); 780 if (err) 781 return err; 782 } 783 for (pidx = 0; pidx < 4; pidx++) { 784 for (i = 0; i < 3; i++) { 785 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, 786 EXT_CSD_GP_SIZE_MULT+pidx*3+i, 787 (gp_size_mult[pidx] >> (i*8)) & 0xFF); 788 if (err) 789 return err; 790 } 791 } 792 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, 793 EXT_CSD_PARTITIONS_ATTRIBUTE, part_attrs); 794 if (err) 795 return err; 796 797 if (mode == MMC_HWPART_CONF_SET) 798 return 0; 799 800 /* The WR_REL_SET is a write-once register but shall be 801 * written before setting PART_SETTING_COMPLETED. As it is 802 * write-once we can only write it when completing the 803 * partitioning. */ 804 if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET]) { 805 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, 806 EXT_CSD_WR_REL_SET, wr_rel_set); 807 if (err) 808 return err; 809 } 810 811 /* Setting PART_SETTING_COMPLETED confirms the partition 812 * configuration but it only becomes effective after power 813 * cycle, so we do not adjust the partition related settings 814 * in the mmc struct. */ 815 816 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, 817 EXT_CSD_PARTITION_SETTING, 818 EXT_CSD_PARTITION_SETTING_COMPLETED); 819 if (err) 820 return err; 821 822 return 0; 823 } 824 825 int mmc_getcd(struct mmc *mmc) 826 { 827 int cd; 828 829 cd = board_mmc_getcd(mmc); 830 831 if (cd < 0) { 832 if (mmc->cfg->ops->getcd) 833 cd = mmc->cfg->ops->getcd(mmc); 834 else 835 cd = 1; 836 } 837 838 return cd; 839 } 840 841 static int sd_switch(struct mmc *mmc, int mode, int group, u8 value, u8 *resp) 842 { 843 struct mmc_cmd cmd; 844 struct mmc_data data; 845 846 /* Switch the frequency */ 847 cmd.cmdidx = SD_CMD_SWITCH_FUNC; 848 cmd.resp_type = MMC_RSP_R1; 849 cmd.cmdarg = (mode << 31) | 0xffffff; 850 cmd.cmdarg &= ~(0xf << (group * 4)); 851 cmd.cmdarg |= value << (group * 4); 852 853 data.dest = (char *)resp; 854 data.blocksize = 64; 855 data.blocks = 1; 856 data.flags = MMC_DATA_READ; 857 858 return mmc_send_cmd(mmc, &cmd, &data); 859 } 860 861 862 static int sd_change_freq(struct mmc *mmc) 863 { 864 int err; 865 struct mmc_cmd cmd; 866 ALLOC_CACHE_ALIGN_BUFFER(uint, scr, 2); 867 ALLOC_CACHE_ALIGN_BUFFER(uint, switch_status, 16); 868 struct mmc_data data; 869 int timeout; 870 871 mmc->card_caps = 0; 872 873 if (mmc_host_is_spi(mmc)) 874 return 0; 875 876 /* Read the SCR to find out if this card supports higher speeds */ 877 cmd.cmdidx = MMC_CMD_APP_CMD; 878 cmd.resp_type = MMC_RSP_R1; 879 cmd.cmdarg = mmc->rca << 16; 880 881 err = mmc_send_cmd(mmc, &cmd, NULL); 882 883 if (err) 884 return err; 885 886 cmd.cmdidx = SD_CMD_APP_SEND_SCR; 887 cmd.resp_type = MMC_RSP_R1; 888 cmd.cmdarg = 0; 889 890 timeout = 3; 891 892 retry_scr: 893 data.dest = (char *)scr; 894 data.blocksize = 8; 895 data.blocks = 1; 896 data.flags = MMC_DATA_READ; 897 898 err = mmc_send_cmd(mmc, &cmd, &data); 899 900 if (err) { 901 if (timeout--) 902 goto retry_scr; 903 904 return err; 905 } 906 907 mmc->scr[0] = __be32_to_cpu(scr[0]); 908 mmc->scr[1] = __be32_to_cpu(scr[1]); 909 910 switch ((mmc->scr[0] >> 24) & 0xf) { 911 case 0: 912 mmc->version = SD_VERSION_1_0; 913 break; 914 case 1: 915 mmc->version = SD_VERSION_1_10; 916 break; 917 case 2: 918 mmc->version = SD_VERSION_2; 919 if ((mmc->scr[0] >> 15) & 0x1) 920 mmc->version = SD_VERSION_3; 921 break; 922 default: 923 mmc->version = SD_VERSION_1_0; 924 break; 925 } 926 927 if (mmc->scr[0] & SD_DATA_4BIT) 928 mmc->card_caps |= MMC_MODE_4BIT; 929 930 /* Version 1.0 doesn't support switching */ 931 if (mmc->version == SD_VERSION_1_0) 932 return 0; 933 934 timeout = 4; 935 while (timeout--) { 936 err = sd_switch(mmc, SD_SWITCH_CHECK, 0, 1, 937 (u8 *)switch_status); 938 939 if (err) 940 return err; 941 942 /* The high-speed function is busy. Try again */ 943 if (!(__be32_to_cpu(switch_status[7]) & SD_HIGHSPEED_BUSY)) 944 break; 945 } 946 947 /* If high-speed isn't supported, we return */ 948 if (!(__be32_to_cpu(switch_status[3]) & SD_HIGHSPEED_SUPPORTED)) 949 return 0; 950 951 /* 952 * If the host doesn't support SD_HIGHSPEED, do not switch card to 953 * HIGHSPEED mode even if the card support SD_HIGHSPPED. 954 * This can avoid furthur problem when the card runs in different 955 * mode between the host. 956 */ 957 if (!((mmc->cfg->host_caps & MMC_MODE_HS_52MHz) && 958 (mmc->cfg->host_caps & MMC_MODE_HS))) 959 return 0; 960 961 err = sd_switch(mmc, SD_SWITCH_SWITCH, 0, 1, (u8 *)switch_status); 962 963 if (err) 964 return err; 965 966 if ((__be32_to_cpu(switch_status[4]) & 0x0f000000) == 0x01000000) 967 mmc->card_caps |= MMC_MODE_HS; 968 969 return 0; 970 } 971 972 /* frequency bases */ 973 /* divided by 10 to be nice to platforms without floating point */ 974 static const int fbase[] = { 975 10000, 976 100000, 977 1000000, 978 10000000, 979 }; 980 981 /* Multiplier values for TRAN_SPEED. Multiplied by 10 to be nice 982 * to platforms without floating point. 983 */ 984 static const u8 multipliers[] = { 985 0, /* reserved */ 986 10, 987 12, 988 13, 989 15, 990 20, 991 25, 992 30, 993 35, 994 40, 995 45, 996 50, 997 55, 998 60, 999 70, 1000 80, 1001 }; 1002 1003 static void mmc_set_ios(struct mmc *mmc) 1004 { 1005 if (mmc->cfg->ops->set_ios) 1006 mmc->cfg->ops->set_ios(mmc); 1007 } 1008 1009 void mmc_set_clock(struct mmc *mmc, uint clock) 1010 { 1011 if (clock > mmc->cfg->f_max) 1012 clock = mmc->cfg->f_max; 1013 1014 if (clock < mmc->cfg->f_min) 1015 clock = mmc->cfg->f_min; 1016 1017 mmc->clock = clock; 1018 1019 mmc_set_ios(mmc); 1020 } 1021 1022 static void mmc_set_bus_width(struct mmc *mmc, uint width) 1023 { 1024 mmc->bus_width = width; 1025 1026 mmc_set_ios(mmc); 1027 } 1028 1029 static int mmc_startup(struct mmc *mmc) 1030 { 1031 int err, i; 1032 uint mult, freq; 1033 u64 cmult, csize, capacity; 1034 struct mmc_cmd cmd; 1035 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN); 1036 ALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, MMC_MAX_BLOCK_LEN); 1037 int timeout = 1000; 1038 bool has_parts = false; 1039 bool part_completed; 1040 struct blk_desc *bdesc; 1041 1042 #ifdef CONFIG_MMC_SPI_CRC_ON 1043 if (mmc_host_is_spi(mmc)) { /* enable CRC check for spi */ 1044 cmd.cmdidx = MMC_CMD_SPI_CRC_ON_OFF; 1045 cmd.resp_type = MMC_RSP_R1; 1046 cmd.cmdarg = 1; 1047 err = mmc_send_cmd(mmc, &cmd, NULL); 1048 1049 if (err) 1050 return err; 1051 } 1052 #endif 1053 1054 /* Put the Card in Identify Mode */ 1055 cmd.cmdidx = mmc_host_is_spi(mmc) ? MMC_CMD_SEND_CID : 1056 MMC_CMD_ALL_SEND_CID; /* cmd not supported in spi */ 1057 cmd.resp_type = MMC_RSP_R2; 1058 cmd.cmdarg = 0; 1059 1060 err = mmc_send_cmd(mmc, &cmd, NULL); 1061 1062 if (err) 1063 return err; 1064 1065 memcpy(mmc->cid, cmd.response, 16); 1066 1067 /* 1068 * For MMC cards, set the Relative Address. 1069 * For SD cards, get the Relatvie Address. 1070 * This also puts the cards into Standby State 1071 */ 1072 if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */ 1073 cmd.cmdidx = SD_CMD_SEND_RELATIVE_ADDR; 1074 cmd.cmdarg = mmc->rca << 16; 1075 cmd.resp_type = MMC_RSP_R6; 1076 1077 err = mmc_send_cmd(mmc, &cmd, NULL); 1078 1079 if (err) 1080 return err; 1081 1082 if (IS_SD(mmc)) 1083 mmc->rca = (cmd.response[0] >> 16) & 0xffff; 1084 } 1085 1086 /* Get the Card-Specific Data */ 1087 cmd.cmdidx = MMC_CMD_SEND_CSD; 1088 cmd.resp_type = MMC_RSP_R2; 1089 cmd.cmdarg = mmc->rca << 16; 1090 1091 err = mmc_send_cmd(mmc, &cmd, NULL); 1092 1093 /* Waiting for the ready status */ 1094 mmc_send_status(mmc, timeout); 1095 1096 if (err) 1097 return err; 1098 1099 mmc->csd[0] = cmd.response[0]; 1100 mmc->csd[1] = cmd.response[1]; 1101 mmc->csd[2] = cmd.response[2]; 1102 mmc->csd[3] = cmd.response[3]; 1103 1104 if (mmc->version == MMC_VERSION_UNKNOWN) { 1105 int version = (cmd.response[0] >> 26) & 0xf; 1106 1107 switch (version) { 1108 case 0: 1109 mmc->version = MMC_VERSION_1_2; 1110 break; 1111 case 1: 1112 mmc->version = MMC_VERSION_1_4; 1113 break; 1114 case 2: 1115 mmc->version = MMC_VERSION_2_2; 1116 break; 1117 case 3: 1118 mmc->version = MMC_VERSION_3; 1119 break; 1120 case 4: 1121 mmc->version = MMC_VERSION_4; 1122 break; 1123 default: 1124 mmc->version = MMC_VERSION_1_2; 1125 break; 1126 } 1127 } 1128 1129 /* divide frequency by 10, since the mults are 10x bigger */ 1130 freq = fbase[(cmd.response[0] & 0x7)]; 1131 mult = multipliers[((cmd.response[0] >> 3) & 0xf)]; 1132 1133 mmc->tran_speed = freq * mult; 1134 1135 mmc->dsr_imp = ((cmd.response[1] >> 12) & 0x1); 1136 mmc->read_bl_len = 1 << ((cmd.response[1] >> 16) & 0xf); 1137 1138 if (IS_SD(mmc)) 1139 mmc->write_bl_len = mmc->read_bl_len; 1140 else 1141 mmc->write_bl_len = 1 << ((cmd.response[3] >> 22) & 0xf); 1142 1143 if (mmc->high_capacity) { 1144 csize = (mmc->csd[1] & 0x3f) << 16 1145 | (mmc->csd[2] & 0xffff0000) >> 16; 1146 cmult = 8; 1147 } else { 1148 csize = (mmc->csd[1] & 0x3ff) << 2 1149 | (mmc->csd[2] & 0xc0000000) >> 30; 1150 cmult = (mmc->csd[2] & 0x00038000) >> 15; 1151 } 1152 1153 mmc->capacity_user = (csize + 1) << (cmult + 2); 1154 mmc->capacity_user *= mmc->read_bl_len; 1155 mmc->capacity_boot = 0; 1156 mmc->capacity_rpmb = 0; 1157 for (i = 0; i < 4; i++) 1158 mmc->capacity_gp[i] = 0; 1159 1160 if (mmc->read_bl_len > MMC_MAX_BLOCK_LEN) 1161 mmc->read_bl_len = MMC_MAX_BLOCK_LEN; 1162 1163 if (mmc->write_bl_len > MMC_MAX_BLOCK_LEN) 1164 mmc->write_bl_len = MMC_MAX_BLOCK_LEN; 1165 1166 if ((mmc->dsr_imp) && (0xffffffff != mmc->dsr)) { 1167 cmd.cmdidx = MMC_CMD_SET_DSR; 1168 cmd.cmdarg = (mmc->dsr & 0xffff) << 16; 1169 cmd.resp_type = MMC_RSP_NONE; 1170 if (mmc_send_cmd(mmc, &cmd, NULL)) 1171 printf("MMC: SET_DSR failed\n"); 1172 } 1173 1174 /* Select the card, and put it into Transfer Mode */ 1175 if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */ 1176 cmd.cmdidx = MMC_CMD_SELECT_CARD; 1177 cmd.resp_type = MMC_RSP_R1; 1178 cmd.cmdarg = mmc->rca << 16; 1179 err = mmc_send_cmd(mmc, &cmd, NULL); 1180 1181 if (err) 1182 return err; 1183 } 1184 1185 /* 1186 * For SD, its erase group is always one sector 1187 */ 1188 mmc->erase_grp_size = 1; 1189 mmc->part_config = MMCPART_NOAVAILABLE; 1190 if (!IS_SD(mmc) && (mmc->version >= MMC_VERSION_4)) { 1191 /* check ext_csd version and capacity */ 1192 err = mmc_send_ext_csd(mmc, ext_csd); 1193 if (err) 1194 return err; 1195 if (ext_csd[EXT_CSD_REV] >= 2) { 1196 /* 1197 * According to the JEDEC Standard, the value of 1198 * ext_csd's capacity is valid if the value is more 1199 * than 2GB 1200 */ 1201 capacity = ext_csd[EXT_CSD_SEC_CNT] << 0 1202 | ext_csd[EXT_CSD_SEC_CNT + 1] << 8 1203 | ext_csd[EXT_CSD_SEC_CNT + 2] << 16 1204 | ext_csd[EXT_CSD_SEC_CNT + 3] << 24; 1205 capacity *= MMC_MAX_BLOCK_LEN; 1206 if ((capacity >> 20) > 2 * 1024) 1207 mmc->capacity_user = capacity; 1208 } 1209 1210 switch (ext_csd[EXT_CSD_REV]) { 1211 case 1: 1212 mmc->version = MMC_VERSION_4_1; 1213 break; 1214 case 2: 1215 mmc->version = MMC_VERSION_4_2; 1216 break; 1217 case 3: 1218 mmc->version = MMC_VERSION_4_3; 1219 break; 1220 case 5: 1221 mmc->version = MMC_VERSION_4_41; 1222 break; 1223 case 6: 1224 mmc->version = MMC_VERSION_4_5; 1225 break; 1226 case 7: 1227 mmc->version = MMC_VERSION_5_0; 1228 break; 1229 case 8: 1230 mmc->version = MMC_VERSION_5_1; 1231 break; 1232 } 1233 1234 /* The partition data may be non-zero but it is only 1235 * effective if PARTITION_SETTING_COMPLETED is set in 1236 * EXT_CSD, so ignore any data if this bit is not set, 1237 * except for enabling the high-capacity group size 1238 * definition (see below). */ 1239 part_completed = !!(ext_csd[EXT_CSD_PARTITION_SETTING] & 1240 EXT_CSD_PARTITION_SETTING_COMPLETED); 1241 1242 /* store the partition info of emmc */ 1243 mmc->part_support = ext_csd[EXT_CSD_PARTITIONING_SUPPORT]; 1244 if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) || 1245 ext_csd[EXT_CSD_BOOT_MULT]) 1246 mmc->part_config = ext_csd[EXT_CSD_PART_CONF]; 1247 if (part_completed && 1248 (ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & ENHNCD_SUPPORT)) 1249 mmc->part_attr = ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE]; 1250 1251 mmc->capacity_boot = ext_csd[EXT_CSD_BOOT_MULT] << 17; 1252 1253 mmc->capacity_rpmb = ext_csd[EXT_CSD_RPMB_MULT] << 17; 1254 1255 for (i = 0; i < 4; i++) { 1256 int idx = EXT_CSD_GP_SIZE_MULT + i * 3; 1257 uint mult = (ext_csd[idx + 2] << 16) + 1258 (ext_csd[idx + 1] << 8) + ext_csd[idx]; 1259 if (mult) 1260 has_parts = true; 1261 if (!part_completed) 1262 continue; 1263 mmc->capacity_gp[i] = mult; 1264 mmc->capacity_gp[i] *= 1265 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]; 1266 mmc->capacity_gp[i] *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE]; 1267 mmc->capacity_gp[i] <<= 19; 1268 } 1269 1270 if (part_completed) { 1271 mmc->enh_user_size = 1272 (ext_csd[EXT_CSD_ENH_SIZE_MULT+2] << 16) + 1273 (ext_csd[EXT_CSD_ENH_SIZE_MULT+1] << 8) + 1274 ext_csd[EXT_CSD_ENH_SIZE_MULT]; 1275 mmc->enh_user_size *= ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]; 1276 mmc->enh_user_size *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE]; 1277 mmc->enh_user_size <<= 19; 1278 mmc->enh_user_start = 1279 (ext_csd[EXT_CSD_ENH_START_ADDR+3] << 24) + 1280 (ext_csd[EXT_CSD_ENH_START_ADDR+2] << 16) + 1281 (ext_csd[EXT_CSD_ENH_START_ADDR+1] << 8) + 1282 ext_csd[EXT_CSD_ENH_START_ADDR]; 1283 if (mmc->high_capacity) 1284 mmc->enh_user_start <<= 9; 1285 } 1286 1287 /* 1288 * Host needs to enable ERASE_GRP_DEF bit if device is 1289 * partitioned. This bit will be lost every time after a reset 1290 * or power off. This will affect erase size. 1291 */ 1292 if (part_completed) 1293 has_parts = true; 1294 if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) && 1295 (ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE] & PART_ENH_ATTRIB)) 1296 has_parts = true; 1297 if (has_parts) { 1298 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, 1299 EXT_CSD_ERASE_GROUP_DEF, 1); 1300 1301 if (err) 1302 return err; 1303 else 1304 ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1; 1305 } 1306 1307 if (ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01) { 1308 /* Read out group size from ext_csd */ 1309 mmc->erase_grp_size = 1310 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024; 1311 /* 1312 * if high capacity and partition setting completed 1313 * SEC_COUNT is valid even if it is smaller than 2 GiB 1314 * JEDEC Standard JESD84-B45, 6.2.4 1315 */ 1316 if (mmc->high_capacity && part_completed) { 1317 capacity = (ext_csd[EXT_CSD_SEC_CNT]) | 1318 (ext_csd[EXT_CSD_SEC_CNT + 1] << 8) | 1319 (ext_csd[EXT_CSD_SEC_CNT + 2] << 16) | 1320 (ext_csd[EXT_CSD_SEC_CNT + 3] << 24); 1321 capacity *= MMC_MAX_BLOCK_LEN; 1322 mmc->capacity_user = capacity; 1323 } 1324 } else { 1325 /* Calculate the group size from the csd value. */ 1326 int erase_gsz, erase_gmul; 1327 erase_gsz = (mmc->csd[2] & 0x00007c00) >> 10; 1328 erase_gmul = (mmc->csd[2] & 0x000003e0) >> 5; 1329 mmc->erase_grp_size = (erase_gsz + 1) 1330 * (erase_gmul + 1); 1331 } 1332 1333 mmc->hc_wp_grp_size = 1024 1334 * ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] 1335 * ext_csd[EXT_CSD_HC_WP_GRP_SIZE]; 1336 1337 mmc->wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET]; 1338 } 1339 1340 err = mmc_set_capacity(mmc, mmc_get_blk_desc(mmc)->hwpart); 1341 if (err) 1342 return err; 1343 1344 if (IS_SD(mmc)) 1345 err = sd_change_freq(mmc); 1346 else 1347 err = mmc_change_freq(mmc); 1348 1349 if (err) 1350 return err; 1351 1352 /* Restrict card's capabilities by what the host can do */ 1353 mmc->card_caps &= mmc->cfg->host_caps; 1354 1355 if (IS_SD(mmc)) { 1356 if (mmc->card_caps & MMC_MODE_4BIT) { 1357 cmd.cmdidx = MMC_CMD_APP_CMD; 1358 cmd.resp_type = MMC_RSP_R1; 1359 cmd.cmdarg = mmc->rca << 16; 1360 1361 err = mmc_send_cmd(mmc, &cmd, NULL); 1362 if (err) 1363 return err; 1364 1365 cmd.cmdidx = SD_CMD_APP_SET_BUS_WIDTH; 1366 cmd.resp_type = MMC_RSP_R1; 1367 cmd.cmdarg = 2; 1368 err = mmc_send_cmd(mmc, &cmd, NULL); 1369 if (err) 1370 return err; 1371 1372 mmc_set_bus_width(mmc, 4); 1373 } 1374 1375 if (mmc->card_caps & MMC_MODE_HS) 1376 mmc->tran_speed = 50000000; 1377 else 1378 mmc->tran_speed = 25000000; 1379 } else if (mmc->version >= MMC_VERSION_4) { 1380 /* Only version 4 of MMC supports wider bus widths */ 1381 int idx; 1382 1383 /* An array of possible bus widths in order of preference */ 1384 static unsigned ext_csd_bits[] = { 1385 EXT_CSD_DDR_BUS_WIDTH_8, 1386 EXT_CSD_DDR_BUS_WIDTH_4, 1387 EXT_CSD_BUS_WIDTH_8, 1388 EXT_CSD_BUS_WIDTH_4, 1389 EXT_CSD_BUS_WIDTH_1, 1390 }; 1391 1392 /* An array to map CSD bus widths to host cap bits */ 1393 static unsigned ext_to_hostcaps[] = { 1394 [EXT_CSD_DDR_BUS_WIDTH_4] = 1395 MMC_MODE_DDR_52MHz | MMC_MODE_4BIT, 1396 [EXT_CSD_DDR_BUS_WIDTH_8] = 1397 MMC_MODE_DDR_52MHz | MMC_MODE_8BIT, 1398 [EXT_CSD_BUS_WIDTH_4] = MMC_MODE_4BIT, 1399 [EXT_CSD_BUS_WIDTH_8] = MMC_MODE_8BIT, 1400 }; 1401 1402 /* An array to map chosen bus width to an integer */ 1403 static unsigned widths[] = { 1404 8, 4, 8, 4, 1, 1405 }; 1406 1407 for (idx=0; idx < ARRAY_SIZE(ext_csd_bits); idx++) { 1408 unsigned int extw = ext_csd_bits[idx]; 1409 unsigned int caps = ext_to_hostcaps[extw]; 1410 1411 /* 1412 * If the bus width is still not changed, 1413 * don't try to set the default again. 1414 * Otherwise, recover from switch attempts 1415 * by switching to 1-bit bus width. 1416 */ 1417 if (extw == EXT_CSD_BUS_WIDTH_1 && 1418 mmc->bus_width == 1) { 1419 err = 0; 1420 break; 1421 } 1422 1423 /* 1424 * Check to make sure the card and controller support 1425 * these capabilities 1426 */ 1427 if ((mmc->card_caps & caps) != caps) 1428 continue; 1429 1430 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, 1431 EXT_CSD_BUS_WIDTH, extw); 1432 1433 if (err) 1434 continue; 1435 1436 mmc->ddr_mode = (caps & MMC_MODE_DDR_52MHz) ? 1 : 0; 1437 mmc_set_bus_width(mmc, widths[idx]); 1438 1439 err = mmc_send_ext_csd(mmc, test_csd); 1440 1441 if (err) 1442 continue; 1443 1444 /* Only compare read only fields */ 1445 if (ext_csd[EXT_CSD_PARTITIONING_SUPPORT] 1446 == test_csd[EXT_CSD_PARTITIONING_SUPPORT] && 1447 ext_csd[EXT_CSD_HC_WP_GRP_SIZE] 1448 == test_csd[EXT_CSD_HC_WP_GRP_SIZE] && 1449 ext_csd[EXT_CSD_REV] 1450 == test_csd[EXT_CSD_REV] && 1451 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] 1452 == test_csd[EXT_CSD_HC_ERASE_GRP_SIZE] && 1453 memcmp(&ext_csd[EXT_CSD_SEC_CNT], 1454 &test_csd[EXT_CSD_SEC_CNT], 4) == 0) 1455 break; 1456 else 1457 err = SWITCH_ERR; 1458 } 1459 1460 if (err) 1461 return err; 1462 1463 if (mmc->card_caps & MMC_MODE_HS) { 1464 if (mmc->card_caps & MMC_MODE_HS_52MHz) 1465 mmc->tran_speed = 52000000; 1466 else 1467 mmc->tran_speed = 26000000; 1468 } 1469 } 1470 1471 mmc_set_clock(mmc, mmc->tran_speed); 1472 1473 /* Fix the block length for DDR mode */ 1474 if (mmc->ddr_mode) { 1475 mmc->read_bl_len = MMC_MAX_BLOCK_LEN; 1476 mmc->write_bl_len = MMC_MAX_BLOCK_LEN; 1477 } 1478 1479 /* fill in device description */ 1480 bdesc = mmc_get_blk_desc(mmc); 1481 bdesc->lun = 0; 1482 bdesc->hwpart = 0; 1483 bdesc->type = 0; 1484 bdesc->blksz = mmc->read_bl_len; 1485 bdesc->log2blksz = LOG2(bdesc->blksz); 1486 bdesc->lba = lldiv(mmc->capacity, mmc->read_bl_len); 1487 #if !defined(CONFIG_SPL_BUILD) || \ 1488 (defined(CONFIG_SPL_LIBCOMMON_SUPPORT) && \ 1489 !defined(CONFIG_USE_TINY_PRINTF)) 1490 sprintf(bdesc->vendor, "Man %06x Snr %04x%04x", 1491 mmc->cid[0] >> 24, (mmc->cid[2] & 0xffff), 1492 (mmc->cid[3] >> 16) & 0xffff); 1493 sprintf(bdesc->product, "%c%c%c%c%c%c", mmc->cid[0] & 0xff, 1494 (mmc->cid[1] >> 24), (mmc->cid[1] >> 16) & 0xff, 1495 (mmc->cid[1] >> 8) & 0xff, mmc->cid[1] & 0xff, 1496 (mmc->cid[2] >> 24) & 0xff); 1497 sprintf(bdesc->revision, "%d.%d", (mmc->cid[2] >> 20) & 0xf, 1498 (mmc->cid[2] >> 16) & 0xf); 1499 #else 1500 bdesc->vendor[0] = 0; 1501 bdesc->product[0] = 0; 1502 bdesc->revision[0] = 0; 1503 #endif 1504 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBDISK_SUPPORT) 1505 part_init(bdesc); 1506 #endif 1507 1508 return 0; 1509 } 1510 1511 static int mmc_send_if_cond(struct mmc *mmc) 1512 { 1513 struct mmc_cmd cmd; 1514 int err; 1515 1516 cmd.cmdidx = SD_CMD_SEND_IF_COND; 1517 /* We set the bit if the host supports voltages between 2.7 and 3.6 V */ 1518 cmd.cmdarg = ((mmc->cfg->voltages & 0xff8000) != 0) << 8 | 0xaa; 1519 cmd.resp_type = MMC_RSP_R7; 1520 1521 err = mmc_send_cmd(mmc, &cmd, NULL); 1522 1523 if (err) 1524 return err; 1525 1526 if ((cmd.response[0] & 0xff) != 0xaa) 1527 return UNUSABLE_ERR; 1528 else 1529 mmc->version = SD_VERSION_2; 1530 1531 return 0; 1532 } 1533 1534 #ifdef CONFIG_BLK 1535 int mmc_bind(struct udevice *dev, struct mmc *mmc, const struct mmc_config *cfg) 1536 { 1537 struct blk_desc *bdesc; 1538 struct udevice *bdev; 1539 int ret; 1540 1541 ret = blk_create_devicef(dev, "mmc_blk", "blk", IF_TYPE_MMC, -1, 512, 1542 0, &bdev); 1543 if (ret) { 1544 debug("Cannot create block device\n"); 1545 return ret; 1546 } 1547 bdesc = dev_get_uclass_platdata(bdev); 1548 mmc->cfg = cfg; 1549 mmc->priv = dev; 1550 1551 /* the following chunk was from mmc_register() */ 1552 1553 /* Setup dsr related values */ 1554 mmc->dsr_imp = 0; 1555 mmc->dsr = 0xffffffff; 1556 /* Setup the universal parts of the block interface just once */ 1557 bdesc->removable = 1; 1558 1559 /* setup initial part type */ 1560 bdesc->part_type = cfg->part_type; 1561 mmc->dev = dev; 1562 1563 return 0; 1564 } 1565 1566 int mmc_unbind(struct udevice *dev) 1567 { 1568 struct udevice *bdev; 1569 1570 device_find_first_child(dev, &bdev); 1571 if (bdev) { 1572 device_remove(bdev); 1573 device_unbind(bdev); 1574 } 1575 1576 return 0; 1577 } 1578 1579 #else 1580 struct mmc *mmc_create(const struct mmc_config *cfg, void *priv) 1581 { 1582 struct blk_desc *bdesc; 1583 struct mmc *mmc; 1584 1585 /* quick validation */ 1586 if (cfg == NULL || cfg->ops == NULL || cfg->ops->send_cmd == NULL || 1587 cfg->f_min == 0 || cfg->f_max == 0 || cfg->b_max == 0) 1588 return NULL; 1589 1590 mmc = calloc(1, sizeof(*mmc)); 1591 if (mmc == NULL) 1592 return NULL; 1593 1594 mmc->cfg = cfg; 1595 mmc->priv = priv; 1596 1597 /* the following chunk was mmc_register() */ 1598 1599 /* Setup dsr related values */ 1600 mmc->dsr_imp = 0; 1601 mmc->dsr = 0xffffffff; 1602 /* Setup the universal parts of the block interface just once */ 1603 bdesc = mmc_get_blk_desc(mmc); 1604 bdesc->if_type = IF_TYPE_MMC; 1605 bdesc->removable = 1; 1606 bdesc->devnum = mmc_get_next_devnum(); 1607 bdesc->block_read = mmc_bread; 1608 bdesc->block_write = mmc_bwrite; 1609 bdesc->block_erase = mmc_berase; 1610 1611 /* setup initial part type */ 1612 bdesc->part_type = mmc->cfg->part_type; 1613 mmc_list_add(mmc); 1614 1615 return mmc; 1616 } 1617 1618 void mmc_destroy(struct mmc *mmc) 1619 { 1620 /* only freeing memory for now */ 1621 free(mmc); 1622 } 1623 #endif 1624 1625 #ifndef CONFIG_BLK 1626 static int mmc_get_dev(int dev, struct blk_desc **descp) 1627 { 1628 struct mmc *mmc = find_mmc_device(dev); 1629 int ret; 1630 1631 if (!mmc) 1632 return -ENODEV; 1633 ret = mmc_init(mmc); 1634 if (ret) 1635 return ret; 1636 1637 *descp = &mmc->block_dev; 1638 1639 return 0; 1640 } 1641 #endif 1642 1643 /* board-specific MMC power initializations. */ 1644 __weak void board_mmc_power_init(void) 1645 { 1646 } 1647 1648 int mmc_start_init(struct mmc *mmc) 1649 { 1650 int err; 1651 1652 /* we pretend there's no card when init is NULL */ 1653 if (mmc_getcd(mmc) == 0 || mmc->cfg->ops->init == NULL) { 1654 mmc->has_init = 0; 1655 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) 1656 printf("MMC: no card present\n"); 1657 #endif 1658 return NO_CARD_ERR; 1659 } 1660 1661 if (mmc->has_init) 1662 return 0; 1663 1664 #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT 1665 mmc_adapter_card_type_ident(); 1666 #endif 1667 board_mmc_power_init(); 1668 1669 /* made sure it's not NULL earlier */ 1670 err = mmc->cfg->ops->init(mmc); 1671 1672 if (err) 1673 return err; 1674 1675 mmc->ddr_mode = 0; 1676 mmc_set_bus_width(mmc, 1); 1677 mmc_set_clock(mmc, 1); 1678 1679 /* Reset the Card */ 1680 err = mmc_go_idle(mmc); 1681 1682 if (err) 1683 return err; 1684 1685 /* The internal partition reset to user partition(0) at every CMD0*/ 1686 mmc_get_blk_desc(mmc)->hwpart = 0; 1687 1688 /* Test for SD version 2 */ 1689 err = mmc_send_if_cond(mmc); 1690 1691 /* Now try to get the SD card's operating condition */ 1692 err = sd_send_op_cond(mmc); 1693 1694 /* If the command timed out, we check for an MMC card */ 1695 if (err == TIMEOUT) { 1696 err = mmc_send_op_cond(mmc); 1697 1698 if (err) { 1699 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) 1700 printf("Card did not respond to voltage select!\n"); 1701 #endif 1702 return UNUSABLE_ERR; 1703 } 1704 } 1705 1706 if (!err) 1707 mmc->init_in_progress = 1; 1708 1709 return err; 1710 } 1711 1712 static int mmc_complete_init(struct mmc *mmc) 1713 { 1714 int err = 0; 1715 1716 mmc->init_in_progress = 0; 1717 if (mmc->op_cond_pending) 1718 err = mmc_complete_op_cond(mmc); 1719 1720 if (!err) 1721 err = mmc_startup(mmc); 1722 if (err) 1723 mmc->has_init = 0; 1724 else 1725 mmc->has_init = 1; 1726 return err; 1727 } 1728 1729 int mmc_init(struct mmc *mmc) 1730 { 1731 int err = 0; 1732 unsigned start; 1733 #ifdef CONFIG_DM_MMC 1734 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(mmc->dev); 1735 1736 upriv->mmc = mmc; 1737 #endif 1738 if (mmc->has_init) 1739 return 0; 1740 1741 start = get_timer(0); 1742 1743 if (!mmc->init_in_progress) 1744 err = mmc_start_init(mmc); 1745 1746 if (!err) 1747 err = mmc_complete_init(mmc); 1748 debug("%s: %d, time %lu\n", __func__, err, get_timer(start)); 1749 return err; 1750 } 1751 1752 int mmc_set_dsr(struct mmc *mmc, u16 val) 1753 { 1754 mmc->dsr = val; 1755 return 0; 1756 } 1757 1758 /* CPU-specific MMC initializations */ 1759 __weak int cpu_mmc_init(bd_t *bis) 1760 { 1761 return -1; 1762 } 1763 1764 /* board-specific MMC initializations. */ 1765 __weak int board_mmc_init(bd_t *bis) 1766 { 1767 return -1; 1768 } 1769 1770 void mmc_set_preinit(struct mmc *mmc, int preinit) 1771 { 1772 mmc->preinit = preinit; 1773 } 1774 1775 #if defined(CONFIG_DM_MMC) && defined(CONFIG_SPL_BUILD) 1776 static int mmc_probe(bd_t *bis) 1777 { 1778 return 0; 1779 } 1780 #elif defined(CONFIG_DM_MMC) 1781 static int mmc_probe(bd_t *bis) 1782 { 1783 int ret, i; 1784 struct uclass *uc; 1785 struct udevice *dev; 1786 1787 ret = uclass_get(UCLASS_MMC, &uc); 1788 if (ret) 1789 return ret; 1790 1791 /* 1792 * Try to add them in sequence order. Really with driver model we 1793 * should allow holes, but the current MMC list does not allow that. 1794 * So if we request 0, 1, 3 we will get 0, 1, 2. 1795 */ 1796 for (i = 0; ; i++) { 1797 ret = uclass_get_device_by_seq(UCLASS_MMC, i, &dev); 1798 if (ret == -ENODEV) 1799 break; 1800 } 1801 uclass_foreach_dev(dev, uc) { 1802 ret = device_probe(dev); 1803 if (ret) 1804 printf("%s - probe failed: %d\n", dev->name, ret); 1805 } 1806 1807 return 0; 1808 } 1809 #else 1810 static int mmc_probe(bd_t *bis) 1811 { 1812 if (board_mmc_init(bis) < 0) 1813 cpu_mmc_init(bis); 1814 1815 return 0; 1816 } 1817 #endif 1818 1819 int mmc_initialize(bd_t *bis) 1820 { 1821 static int initialized = 0; 1822 int ret; 1823 if (initialized) /* Avoid initializing mmc multiple times */ 1824 return 0; 1825 initialized = 1; 1826 1827 #ifndef CONFIG_BLK 1828 mmc_list_init(); 1829 #endif 1830 ret = mmc_probe(bis); 1831 if (ret) 1832 return ret; 1833 1834 #ifndef CONFIG_SPL_BUILD 1835 print_mmc_devices(','); 1836 #endif 1837 1838 mmc_do_preinit(); 1839 return 0; 1840 } 1841 1842 #ifdef CONFIG_SUPPORT_EMMC_BOOT 1843 /* 1844 * This function changes the size of boot partition and the size of rpmb 1845 * partition present on EMMC devices. 1846 * 1847 * Input Parameters: 1848 * struct *mmc: pointer for the mmc device strcuture 1849 * bootsize: size of boot partition 1850 * rpmbsize: size of rpmb partition 1851 * 1852 * Returns 0 on success. 1853 */ 1854 1855 int mmc_boot_partition_size_change(struct mmc *mmc, unsigned long bootsize, 1856 unsigned long rpmbsize) 1857 { 1858 int err; 1859 struct mmc_cmd cmd; 1860 1861 /* Only use this command for raw EMMC moviNAND. Enter backdoor mode */ 1862 cmd.cmdidx = MMC_CMD_RES_MAN; 1863 cmd.resp_type = MMC_RSP_R1b; 1864 cmd.cmdarg = MMC_CMD62_ARG1; 1865 1866 err = mmc_send_cmd(mmc, &cmd, NULL); 1867 if (err) { 1868 debug("mmc_boot_partition_size_change: Error1 = %d\n", err); 1869 return err; 1870 } 1871 1872 /* Boot partition changing mode */ 1873 cmd.cmdidx = MMC_CMD_RES_MAN; 1874 cmd.resp_type = MMC_RSP_R1b; 1875 cmd.cmdarg = MMC_CMD62_ARG2; 1876 1877 err = mmc_send_cmd(mmc, &cmd, NULL); 1878 if (err) { 1879 debug("mmc_boot_partition_size_change: Error2 = %d\n", err); 1880 return err; 1881 } 1882 /* boot partition size is multiple of 128KB */ 1883 bootsize = (bootsize * 1024) / 128; 1884 1885 /* Arg: boot partition size */ 1886 cmd.cmdidx = MMC_CMD_RES_MAN; 1887 cmd.resp_type = MMC_RSP_R1b; 1888 cmd.cmdarg = bootsize; 1889 1890 err = mmc_send_cmd(mmc, &cmd, NULL); 1891 if (err) { 1892 debug("mmc_boot_partition_size_change: Error3 = %d\n", err); 1893 return err; 1894 } 1895 /* RPMB partition size is multiple of 128KB */ 1896 rpmbsize = (rpmbsize * 1024) / 128; 1897 /* Arg: RPMB partition size */ 1898 cmd.cmdidx = MMC_CMD_RES_MAN; 1899 cmd.resp_type = MMC_RSP_R1b; 1900 cmd.cmdarg = rpmbsize; 1901 1902 err = mmc_send_cmd(mmc, &cmd, NULL); 1903 if (err) { 1904 debug("mmc_boot_partition_size_change: Error4 = %d\n", err); 1905 return err; 1906 } 1907 return 0; 1908 } 1909 1910 /* 1911 * Modify EXT_CSD[177] which is BOOT_BUS_WIDTH 1912 * based on the passed in values for BOOT_BUS_WIDTH, RESET_BOOT_BUS_WIDTH 1913 * and BOOT_MODE. 1914 * 1915 * Returns 0 on success. 1916 */ 1917 int mmc_set_boot_bus_width(struct mmc *mmc, u8 width, u8 reset, u8 mode) 1918 { 1919 int err; 1920 1921 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BOOT_BUS_WIDTH, 1922 EXT_CSD_BOOT_BUS_WIDTH_MODE(mode) | 1923 EXT_CSD_BOOT_BUS_WIDTH_RESET(reset) | 1924 EXT_CSD_BOOT_BUS_WIDTH_WIDTH(width)); 1925 1926 if (err) 1927 return err; 1928 return 0; 1929 } 1930 1931 /* 1932 * Modify EXT_CSD[179] which is PARTITION_CONFIG (formerly BOOT_CONFIG) 1933 * based on the passed in values for BOOT_ACK, BOOT_PARTITION_ENABLE and 1934 * PARTITION_ACCESS. 1935 * 1936 * Returns 0 on success. 1937 */ 1938 int mmc_set_part_conf(struct mmc *mmc, u8 ack, u8 part_num, u8 access) 1939 { 1940 int err; 1941 1942 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_PART_CONF, 1943 EXT_CSD_BOOT_ACK(ack) | 1944 EXT_CSD_BOOT_PART_NUM(part_num) | 1945 EXT_CSD_PARTITION_ACCESS(access)); 1946 1947 if (err) 1948 return err; 1949 return 0; 1950 } 1951 1952 /* 1953 * Modify EXT_CSD[162] which is RST_n_FUNCTION based on the given value 1954 * for enable. Note that this is a write-once field for non-zero values. 1955 * 1956 * Returns 0 on success. 1957 */ 1958 int mmc_set_rst_n_function(struct mmc *mmc, u8 enable) 1959 { 1960 return mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_RST_N_FUNCTION, 1961 enable); 1962 } 1963 #endif 1964 1965 #ifdef CONFIG_BLK 1966 static const struct blk_ops mmc_blk_ops = { 1967 .read = mmc_bread, 1968 .write = mmc_bwrite, 1969 .select_hwpart = mmc_select_hwpart, 1970 }; 1971 1972 U_BOOT_DRIVER(mmc_blk) = { 1973 .name = "mmc_blk", 1974 .id = UCLASS_BLK, 1975 .ops = &mmc_blk_ops, 1976 }; 1977 #else 1978 U_BOOT_LEGACY_BLK(mmc) = { 1979 .if_typename = "mmc", 1980 .if_type = IF_TYPE_MMC, 1981 .max_devs = -1, 1982 .get_dev = mmc_get_dev, 1983 .select_hwpart = mmc_select_hwpartp, 1984 }; 1985 #endif 1986