1 /* 2 * Copyright 2008, Freescale Semiconductor, Inc 3 * Andy Fleming 4 * 5 * Based vaguely on the Linux code 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #include <config.h> 11 #include <common.h> 12 #include <command.h> 13 #include <dm.h> 14 #include <dm/device-internal.h> 15 #include <errno.h> 16 #include <mmc.h> 17 #include <part.h> 18 #include <malloc.h> 19 #include <memalign.h> 20 #include <linux/list.h> 21 #include <div64.h> 22 #include "mmc_private.h" 23 24 __weak int board_mmc_getwp(struct mmc *mmc) 25 { 26 return -1; 27 } 28 29 int mmc_getwp(struct mmc *mmc) 30 { 31 int wp; 32 33 wp = board_mmc_getwp(mmc); 34 35 if (wp < 0) { 36 if (mmc->cfg->ops->getwp) 37 wp = mmc->cfg->ops->getwp(mmc); 38 else 39 wp = 0; 40 } 41 42 return wp; 43 } 44 45 __weak int board_mmc_getcd(struct mmc *mmc) 46 { 47 return -1; 48 } 49 50 int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) 51 { 52 int ret; 53 54 #ifdef CONFIG_MMC_TRACE 55 int i; 56 u8 *ptr; 57 58 printf("CMD_SEND:%d\n", cmd->cmdidx); 59 printf("\t\tARG\t\t\t 0x%08X\n", cmd->cmdarg); 60 ret = mmc->cfg->ops->send_cmd(mmc, cmd, data); 61 if (ret) { 62 printf("\t\tRET\t\t\t %d\n", ret); 63 } else { 64 switch (cmd->resp_type) { 65 case MMC_RSP_NONE: 66 printf("\t\tMMC_RSP_NONE\n"); 67 break; 68 case MMC_RSP_R1: 69 printf("\t\tMMC_RSP_R1,5,6,7 \t 0x%08X \n", 70 cmd->response[0]); 71 break; 72 case MMC_RSP_R1b: 73 printf("\t\tMMC_RSP_R1b\t\t 0x%08X \n", 74 cmd->response[0]); 75 break; 76 case MMC_RSP_R2: 77 printf("\t\tMMC_RSP_R2\t\t 0x%08X \n", 78 cmd->response[0]); 79 printf("\t\t \t\t 0x%08X \n", 80 cmd->response[1]); 81 printf("\t\t \t\t 0x%08X \n", 82 cmd->response[2]); 83 printf("\t\t \t\t 0x%08X \n", 84 cmd->response[3]); 85 printf("\n"); 86 printf("\t\t\t\t\tDUMPING DATA\n"); 87 for (i = 0; i < 4; i++) { 88 int j; 89 printf("\t\t\t\t\t%03d - ", i*4); 90 ptr = (u8 *)&cmd->response[i]; 91 ptr += 3; 92 for (j = 0; j < 4; j++) 93 printf("%02X ", *ptr--); 94 printf("\n"); 95 } 96 break; 97 case MMC_RSP_R3: 98 printf("\t\tMMC_RSP_R3,4\t\t 0x%08X \n", 99 cmd->response[0]); 100 break; 101 default: 102 printf("\t\tERROR MMC rsp not supported\n"); 103 break; 104 } 105 } 106 #else 107 ret = mmc->cfg->ops->send_cmd(mmc, cmd, data); 108 #endif 109 return ret; 110 } 111 112 int mmc_send_status(struct mmc *mmc, int timeout) 113 { 114 struct mmc_cmd cmd; 115 int err, retries = 5; 116 #ifdef CONFIG_MMC_TRACE 117 int status; 118 #endif 119 120 cmd.cmdidx = MMC_CMD_SEND_STATUS; 121 cmd.resp_type = MMC_RSP_R1; 122 if (!mmc_host_is_spi(mmc)) 123 cmd.cmdarg = mmc->rca << 16; 124 125 while (1) { 126 err = mmc_send_cmd(mmc, &cmd, NULL); 127 if (!err) { 128 if ((cmd.response[0] & MMC_STATUS_RDY_FOR_DATA) && 129 (cmd.response[0] & MMC_STATUS_CURR_STATE) != 130 MMC_STATE_PRG) 131 break; 132 else if (cmd.response[0] & MMC_STATUS_MASK) { 133 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) 134 printf("Status Error: 0x%08X\n", 135 cmd.response[0]); 136 #endif 137 return COMM_ERR; 138 } 139 } else if (--retries < 0) 140 return err; 141 142 if (timeout-- <= 0) 143 break; 144 145 udelay(1000); 146 } 147 148 #ifdef CONFIG_MMC_TRACE 149 status = (cmd.response[0] & MMC_STATUS_CURR_STATE) >> 9; 150 printf("CURR STATE:%d\n", status); 151 #endif 152 if (timeout <= 0) { 153 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) 154 printf("Timeout waiting card ready\n"); 155 #endif 156 return TIMEOUT; 157 } 158 159 return 0; 160 } 161 162 int mmc_set_blocklen(struct mmc *mmc, int len) 163 { 164 struct mmc_cmd cmd; 165 166 if (mmc->ddr_mode) 167 return 0; 168 169 cmd.cmdidx = MMC_CMD_SET_BLOCKLEN; 170 cmd.resp_type = MMC_RSP_R1; 171 cmd.cmdarg = len; 172 173 return mmc_send_cmd(mmc, &cmd, NULL); 174 } 175 176 static int mmc_read_blocks(struct mmc *mmc, void *dst, lbaint_t start, 177 lbaint_t blkcnt) 178 { 179 struct mmc_cmd cmd; 180 struct mmc_data data; 181 182 if (blkcnt > 1) 183 cmd.cmdidx = MMC_CMD_READ_MULTIPLE_BLOCK; 184 else 185 cmd.cmdidx = MMC_CMD_READ_SINGLE_BLOCK; 186 187 if (mmc->high_capacity) 188 cmd.cmdarg = start; 189 else 190 cmd.cmdarg = start * mmc->read_bl_len; 191 192 cmd.resp_type = MMC_RSP_R1; 193 194 data.dest = dst; 195 data.blocks = blkcnt; 196 data.blocksize = mmc->read_bl_len; 197 data.flags = MMC_DATA_READ; 198 199 if (mmc_send_cmd(mmc, &cmd, &data)) 200 return 0; 201 202 if (blkcnt > 1) { 203 cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION; 204 cmd.cmdarg = 0; 205 cmd.resp_type = MMC_RSP_R1b; 206 if (mmc_send_cmd(mmc, &cmd, NULL)) { 207 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) 208 printf("mmc fail to send stop cmd\n"); 209 #endif 210 return 0; 211 } 212 } 213 214 return blkcnt; 215 } 216 217 #ifdef CONFIG_BLK 218 ulong mmc_bread(struct udevice *dev, lbaint_t start, lbaint_t blkcnt, void *dst) 219 #else 220 ulong mmc_bread(struct blk_desc *block_dev, lbaint_t start, lbaint_t blkcnt, 221 void *dst) 222 #endif 223 { 224 #ifdef CONFIG_BLK 225 struct blk_desc *block_dev = dev_get_uclass_platdata(dev); 226 #endif 227 int dev_num = block_dev->devnum; 228 int err; 229 lbaint_t cur, blocks_todo = blkcnt; 230 231 if (blkcnt == 0) 232 return 0; 233 234 struct mmc *mmc = find_mmc_device(dev_num); 235 if (!mmc) 236 return 0; 237 238 err = blk_dselect_hwpart(block_dev, block_dev->hwpart); 239 if (err < 0) 240 return 0; 241 242 if ((start + blkcnt) > block_dev->lba) { 243 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) 244 printf("MMC: block number 0x" LBAF " exceeds max(0x" LBAF ")\n", 245 start + blkcnt, block_dev->lba); 246 #endif 247 return 0; 248 } 249 250 if (mmc_set_blocklen(mmc, mmc->read_bl_len)) { 251 debug("%s: Failed to set blocklen\n", __func__); 252 return 0; 253 } 254 255 do { 256 cur = (blocks_todo > mmc->cfg->b_max) ? 257 mmc->cfg->b_max : blocks_todo; 258 if (mmc_read_blocks(mmc, dst, start, cur) != cur) { 259 debug("%s: Failed to read blocks\n", __func__); 260 return 0; 261 } 262 blocks_todo -= cur; 263 start += cur; 264 dst += cur * mmc->read_bl_len; 265 } while (blocks_todo > 0); 266 267 return blkcnt; 268 } 269 270 static int mmc_go_idle(struct mmc *mmc) 271 { 272 struct mmc_cmd cmd; 273 int err; 274 275 udelay(1000); 276 277 cmd.cmdidx = MMC_CMD_GO_IDLE_STATE; 278 cmd.cmdarg = 0; 279 cmd.resp_type = MMC_RSP_NONE; 280 281 err = mmc_send_cmd(mmc, &cmd, NULL); 282 283 if (err) 284 return err; 285 286 udelay(2000); 287 288 return 0; 289 } 290 291 static int sd_send_op_cond(struct mmc *mmc) 292 { 293 int timeout = 1000; 294 int err; 295 struct mmc_cmd cmd; 296 297 while (1) { 298 cmd.cmdidx = MMC_CMD_APP_CMD; 299 cmd.resp_type = MMC_RSP_R1; 300 cmd.cmdarg = 0; 301 302 err = mmc_send_cmd(mmc, &cmd, NULL); 303 304 if (err) 305 return err; 306 307 cmd.cmdidx = SD_CMD_APP_SEND_OP_COND; 308 cmd.resp_type = MMC_RSP_R3; 309 310 /* 311 * Most cards do not answer if some reserved bits 312 * in the ocr are set. However, Some controller 313 * can set bit 7 (reserved for low voltages), but 314 * how to manage low voltages SD card is not yet 315 * specified. 316 */ 317 cmd.cmdarg = mmc_host_is_spi(mmc) ? 0 : 318 (mmc->cfg->voltages & 0xff8000); 319 320 if (mmc->version == SD_VERSION_2) 321 cmd.cmdarg |= OCR_HCS; 322 323 err = mmc_send_cmd(mmc, &cmd, NULL); 324 325 if (err) 326 return err; 327 328 if (cmd.response[0] & OCR_BUSY) 329 break; 330 331 if (timeout-- <= 0) 332 return UNUSABLE_ERR; 333 334 udelay(1000); 335 } 336 337 if (mmc->version != SD_VERSION_2) 338 mmc->version = SD_VERSION_1_0; 339 340 if (mmc_host_is_spi(mmc)) { /* read OCR for spi */ 341 cmd.cmdidx = MMC_CMD_SPI_READ_OCR; 342 cmd.resp_type = MMC_RSP_R3; 343 cmd.cmdarg = 0; 344 345 err = mmc_send_cmd(mmc, &cmd, NULL); 346 347 if (err) 348 return err; 349 } 350 351 mmc->ocr = cmd.response[0]; 352 353 mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS); 354 mmc->rca = 0; 355 356 return 0; 357 } 358 359 static int mmc_send_op_cond_iter(struct mmc *mmc, int use_arg) 360 { 361 struct mmc_cmd cmd; 362 int err; 363 364 cmd.cmdidx = MMC_CMD_SEND_OP_COND; 365 cmd.resp_type = MMC_RSP_R3; 366 cmd.cmdarg = 0; 367 if (use_arg && !mmc_host_is_spi(mmc)) 368 cmd.cmdarg = OCR_HCS | 369 (mmc->cfg->voltages & 370 (mmc->ocr & OCR_VOLTAGE_MASK)) | 371 (mmc->ocr & OCR_ACCESS_MODE); 372 373 err = mmc_send_cmd(mmc, &cmd, NULL); 374 if (err) 375 return err; 376 mmc->ocr = cmd.response[0]; 377 return 0; 378 } 379 380 static int mmc_send_op_cond(struct mmc *mmc) 381 { 382 int err, i; 383 384 /* Some cards seem to need this */ 385 mmc_go_idle(mmc); 386 387 /* Asking to the card its capabilities */ 388 for (i = 0; i < 2; i++) { 389 err = mmc_send_op_cond_iter(mmc, i != 0); 390 if (err) 391 return err; 392 393 /* exit if not busy (flag seems to be inverted) */ 394 if (mmc->ocr & OCR_BUSY) 395 break; 396 } 397 mmc->op_cond_pending = 1; 398 return 0; 399 } 400 401 static int mmc_complete_op_cond(struct mmc *mmc) 402 { 403 struct mmc_cmd cmd; 404 int timeout = 1000; 405 uint start; 406 int err; 407 408 mmc->op_cond_pending = 0; 409 if (!(mmc->ocr & OCR_BUSY)) { 410 start = get_timer(0); 411 while (1) { 412 err = mmc_send_op_cond_iter(mmc, 1); 413 if (err) 414 return err; 415 if (mmc->ocr & OCR_BUSY) 416 break; 417 if (get_timer(start) > timeout) 418 return UNUSABLE_ERR; 419 udelay(100); 420 } 421 } 422 423 if (mmc_host_is_spi(mmc)) { /* read OCR for spi */ 424 cmd.cmdidx = MMC_CMD_SPI_READ_OCR; 425 cmd.resp_type = MMC_RSP_R3; 426 cmd.cmdarg = 0; 427 428 err = mmc_send_cmd(mmc, &cmd, NULL); 429 430 if (err) 431 return err; 432 433 mmc->ocr = cmd.response[0]; 434 } 435 436 mmc->version = MMC_VERSION_UNKNOWN; 437 438 mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS); 439 mmc->rca = 1; 440 441 return 0; 442 } 443 444 445 static int mmc_send_ext_csd(struct mmc *mmc, u8 *ext_csd) 446 { 447 struct mmc_cmd cmd; 448 struct mmc_data data; 449 int err; 450 451 /* Get the Card Status Register */ 452 cmd.cmdidx = MMC_CMD_SEND_EXT_CSD; 453 cmd.resp_type = MMC_RSP_R1; 454 cmd.cmdarg = 0; 455 456 data.dest = (char *)ext_csd; 457 data.blocks = 1; 458 data.blocksize = MMC_MAX_BLOCK_LEN; 459 data.flags = MMC_DATA_READ; 460 461 err = mmc_send_cmd(mmc, &cmd, &data); 462 463 return err; 464 } 465 466 467 static int mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value) 468 { 469 struct mmc_cmd cmd; 470 int timeout = 1000; 471 int ret; 472 473 cmd.cmdidx = MMC_CMD_SWITCH; 474 cmd.resp_type = MMC_RSP_R1b; 475 cmd.cmdarg = (MMC_SWITCH_MODE_WRITE_BYTE << 24) | 476 (index << 16) | 477 (value << 8); 478 479 ret = mmc_send_cmd(mmc, &cmd, NULL); 480 481 /* Waiting for the ready status */ 482 if (!ret) 483 ret = mmc_send_status(mmc, timeout); 484 485 return ret; 486 487 } 488 489 static int mmc_change_freq(struct mmc *mmc) 490 { 491 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN); 492 char cardtype; 493 int err; 494 495 mmc->card_caps = 0; 496 497 if (mmc_host_is_spi(mmc)) 498 return 0; 499 500 /* Only version 4 supports high-speed */ 501 if (mmc->version < MMC_VERSION_4) 502 return 0; 503 504 mmc->card_caps |= MMC_MODE_4BIT | MMC_MODE_8BIT; 505 506 err = mmc_send_ext_csd(mmc, ext_csd); 507 508 if (err) 509 return err; 510 511 cardtype = ext_csd[EXT_CSD_CARD_TYPE] & 0xf; 512 513 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_HS_TIMING, 1); 514 515 if (err) 516 return err; 517 518 /* Now check to see that it worked */ 519 err = mmc_send_ext_csd(mmc, ext_csd); 520 521 if (err) 522 return err; 523 524 /* No high-speed support */ 525 if (!ext_csd[EXT_CSD_HS_TIMING]) 526 return 0; 527 528 /* High Speed is set, there are two types: 52MHz and 26MHz */ 529 if (cardtype & EXT_CSD_CARD_TYPE_52) { 530 if (cardtype & EXT_CSD_CARD_TYPE_DDR_1_8V) 531 mmc->card_caps |= MMC_MODE_DDR_52MHz; 532 mmc->card_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS; 533 } else { 534 mmc->card_caps |= MMC_MODE_HS; 535 } 536 537 return 0; 538 } 539 540 static int mmc_set_capacity(struct mmc *mmc, int part_num) 541 { 542 switch (part_num) { 543 case 0: 544 mmc->capacity = mmc->capacity_user; 545 break; 546 case 1: 547 case 2: 548 mmc->capacity = mmc->capacity_boot; 549 break; 550 case 3: 551 mmc->capacity = mmc->capacity_rpmb; 552 break; 553 case 4: 554 case 5: 555 case 6: 556 case 7: 557 mmc->capacity = mmc->capacity_gp[part_num - 4]; 558 break; 559 default: 560 return -1; 561 } 562 563 mmc_get_blk_desc(mmc)->lba = lldiv(mmc->capacity, mmc->read_bl_len); 564 565 return 0; 566 } 567 568 int mmc_switch_part(struct mmc *mmc, unsigned int part_num) 569 { 570 int ret; 571 572 ret = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_PART_CONF, 573 (mmc->part_config & ~PART_ACCESS_MASK) 574 | (part_num & PART_ACCESS_MASK)); 575 576 /* 577 * Set the capacity if the switch succeeded or was intended 578 * to return to representing the raw device. 579 */ 580 if ((ret == 0) || ((ret == -ENODEV) && (part_num == 0))) { 581 ret = mmc_set_capacity(mmc, part_num); 582 mmc_get_blk_desc(mmc)->hwpart = part_num; 583 } 584 585 return ret; 586 } 587 588 int mmc_hwpart_config(struct mmc *mmc, 589 const struct mmc_hwpart_conf *conf, 590 enum mmc_hwpart_conf_mode mode) 591 { 592 u8 part_attrs = 0; 593 u32 enh_size_mult; 594 u32 enh_start_addr; 595 u32 gp_size_mult[4]; 596 u32 max_enh_size_mult; 597 u32 tot_enh_size_mult = 0; 598 u8 wr_rel_set; 599 int i, pidx, err; 600 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN); 601 602 if (mode < MMC_HWPART_CONF_CHECK || mode > MMC_HWPART_CONF_COMPLETE) 603 return -EINVAL; 604 605 if (IS_SD(mmc) || (mmc->version < MMC_VERSION_4_41)) { 606 printf("eMMC >= 4.4 required for enhanced user data area\n"); 607 return -EMEDIUMTYPE; 608 } 609 610 if (!(mmc->part_support & PART_SUPPORT)) { 611 printf("Card does not support partitioning\n"); 612 return -EMEDIUMTYPE; 613 } 614 615 if (!mmc->hc_wp_grp_size) { 616 printf("Card does not define HC WP group size\n"); 617 return -EMEDIUMTYPE; 618 } 619 620 /* check partition alignment and total enhanced size */ 621 if (conf->user.enh_size) { 622 if (conf->user.enh_size % mmc->hc_wp_grp_size || 623 conf->user.enh_start % mmc->hc_wp_grp_size) { 624 printf("User data enhanced area not HC WP group " 625 "size aligned\n"); 626 return -EINVAL; 627 } 628 part_attrs |= EXT_CSD_ENH_USR; 629 enh_size_mult = conf->user.enh_size / mmc->hc_wp_grp_size; 630 if (mmc->high_capacity) { 631 enh_start_addr = conf->user.enh_start; 632 } else { 633 enh_start_addr = (conf->user.enh_start << 9); 634 } 635 } else { 636 enh_size_mult = 0; 637 enh_start_addr = 0; 638 } 639 tot_enh_size_mult += enh_size_mult; 640 641 for (pidx = 0; pidx < 4; pidx++) { 642 if (conf->gp_part[pidx].size % mmc->hc_wp_grp_size) { 643 printf("GP%i partition not HC WP group size " 644 "aligned\n", pidx+1); 645 return -EINVAL; 646 } 647 gp_size_mult[pidx] = conf->gp_part[pidx].size / mmc->hc_wp_grp_size; 648 if (conf->gp_part[pidx].size && conf->gp_part[pidx].enhanced) { 649 part_attrs |= EXT_CSD_ENH_GP(pidx); 650 tot_enh_size_mult += gp_size_mult[pidx]; 651 } 652 } 653 654 if (part_attrs && ! (mmc->part_support & ENHNCD_SUPPORT)) { 655 printf("Card does not support enhanced attribute\n"); 656 return -EMEDIUMTYPE; 657 } 658 659 err = mmc_send_ext_csd(mmc, ext_csd); 660 if (err) 661 return err; 662 663 max_enh_size_mult = 664 (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+2] << 16) + 665 (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+1] << 8) + 666 ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT]; 667 if (tot_enh_size_mult > max_enh_size_mult) { 668 printf("Total enhanced size exceeds maximum (%u > %u)\n", 669 tot_enh_size_mult, max_enh_size_mult); 670 return -EMEDIUMTYPE; 671 } 672 673 /* The default value of EXT_CSD_WR_REL_SET is device 674 * dependent, the values can only be changed if the 675 * EXT_CSD_HS_CTRL_REL bit is set. The values can be 676 * changed only once and before partitioning is completed. */ 677 wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET]; 678 if (conf->user.wr_rel_change) { 679 if (conf->user.wr_rel_set) 680 wr_rel_set |= EXT_CSD_WR_DATA_REL_USR; 681 else 682 wr_rel_set &= ~EXT_CSD_WR_DATA_REL_USR; 683 } 684 for (pidx = 0; pidx < 4; pidx++) { 685 if (conf->gp_part[pidx].wr_rel_change) { 686 if (conf->gp_part[pidx].wr_rel_set) 687 wr_rel_set |= EXT_CSD_WR_DATA_REL_GP(pidx); 688 else 689 wr_rel_set &= ~EXT_CSD_WR_DATA_REL_GP(pidx); 690 } 691 } 692 693 if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET] && 694 !(ext_csd[EXT_CSD_WR_REL_PARAM] & EXT_CSD_HS_CTRL_REL)) { 695 puts("Card does not support host controlled partition write " 696 "reliability settings\n"); 697 return -EMEDIUMTYPE; 698 } 699 700 if (ext_csd[EXT_CSD_PARTITION_SETTING] & 701 EXT_CSD_PARTITION_SETTING_COMPLETED) { 702 printf("Card already partitioned\n"); 703 return -EPERM; 704 } 705 706 if (mode == MMC_HWPART_CONF_CHECK) 707 return 0; 708 709 /* Partitioning requires high-capacity size definitions */ 710 if (!(ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01)) { 711 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, 712 EXT_CSD_ERASE_GROUP_DEF, 1); 713 714 if (err) 715 return err; 716 717 ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1; 718 719 /* update erase group size to be high-capacity */ 720 mmc->erase_grp_size = 721 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024; 722 723 } 724 725 /* all OK, write the configuration */ 726 for (i = 0; i < 4; i++) { 727 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, 728 EXT_CSD_ENH_START_ADDR+i, 729 (enh_start_addr >> (i*8)) & 0xFF); 730 if (err) 731 return err; 732 } 733 for (i = 0; i < 3; i++) { 734 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, 735 EXT_CSD_ENH_SIZE_MULT+i, 736 (enh_size_mult >> (i*8)) & 0xFF); 737 if (err) 738 return err; 739 } 740 for (pidx = 0; pidx < 4; pidx++) { 741 for (i = 0; i < 3; i++) { 742 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, 743 EXT_CSD_GP_SIZE_MULT+pidx*3+i, 744 (gp_size_mult[pidx] >> (i*8)) & 0xFF); 745 if (err) 746 return err; 747 } 748 } 749 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, 750 EXT_CSD_PARTITIONS_ATTRIBUTE, part_attrs); 751 if (err) 752 return err; 753 754 if (mode == MMC_HWPART_CONF_SET) 755 return 0; 756 757 /* The WR_REL_SET is a write-once register but shall be 758 * written before setting PART_SETTING_COMPLETED. As it is 759 * write-once we can only write it when completing the 760 * partitioning. */ 761 if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET]) { 762 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, 763 EXT_CSD_WR_REL_SET, wr_rel_set); 764 if (err) 765 return err; 766 } 767 768 /* Setting PART_SETTING_COMPLETED confirms the partition 769 * configuration but it only becomes effective after power 770 * cycle, so we do not adjust the partition related settings 771 * in the mmc struct. */ 772 773 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, 774 EXT_CSD_PARTITION_SETTING, 775 EXT_CSD_PARTITION_SETTING_COMPLETED); 776 if (err) 777 return err; 778 779 return 0; 780 } 781 782 int mmc_getcd(struct mmc *mmc) 783 { 784 int cd; 785 786 cd = board_mmc_getcd(mmc); 787 788 if (cd < 0) { 789 if (mmc->cfg->ops->getcd) 790 cd = mmc->cfg->ops->getcd(mmc); 791 else 792 cd = 1; 793 } 794 795 return cd; 796 } 797 798 static int sd_switch(struct mmc *mmc, int mode, int group, u8 value, u8 *resp) 799 { 800 struct mmc_cmd cmd; 801 struct mmc_data data; 802 803 /* Switch the frequency */ 804 cmd.cmdidx = SD_CMD_SWITCH_FUNC; 805 cmd.resp_type = MMC_RSP_R1; 806 cmd.cmdarg = (mode << 31) | 0xffffff; 807 cmd.cmdarg &= ~(0xf << (group * 4)); 808 cmd.cmdarg |= value << (group * 4); 809 810 data.dest = (char *)resp; 811 data.blocksize = 64; 812 data.blocks = 1; 813 data.flags = MMC_DATA_READ; 814 815 return mmc_send_cmd(mmc, &cmd, &data); 816 } 817 818 819 static int sd_change_freq(struct mmc *mmc) 820 { 821 int err; 822 struct mmc_cmd cmd; 823 ALLOC_CACHE_ALIGN_BUFFER(uint, scr, 2); 824 ALLOC_CACHE_ALIGN_BUFFER(uint, switch_status, 16); 825 struct mmc_data data; 826 int timeout; 827 828 mmc->card_caps = 0; 829 830 if (mmc_host_is_spi(mmc)) 831 return 0; 832 833 /* Read the SCR to find out if this card supports higher speeds */ 834 cmd.cmdidx = MMC_CMD_APP_CMD; 835 cmd.resp_type = MMC_RSP_R1; 836 cmd.cmdarg = mmc->rca << 16; 837 838 err = mmc_send_cmd(mmc, &cmd, NULL); 839 840 if (err) 841 return err; 842 843 cmd.cmdidx = SD_CMD_APP_SEND_SCR; 844 cmd.resp_type = MMC_RSP_R1; 845 cmd.cmdarg = 0; 846 847 timeout = 3; 848 849 retry_scr: 850 data.dest = (char *)scr; 851 data.blocksize = 8; 852 data.blocks = 1; 853 data.flags = MMC_DATA_READ; 854 855 err = mmc_send_cmd(mmc, &cmd, &data); 856 857 if (err) { 858 if (timeout--) 859 goto retry_scr; 860 861 return err; 862 } 863 864 mmc->scr[0] = __be32_to_cpu(scr[0]); 865 mmc->scr[1] = __be32_to_cpu(scr[1]); 866 867 switch ((mmc->scr[0] >> 24) & 0xf) { 868 case 0: 869 mmc->version = SD_VERSION_1_0; 870 break; 871 case 1: 872 mmc->version = SD_VERSION_1_10; 873 break; 874 case 2: 875 mmc->version = SD_VERSION_2; 876 if ((mmc->scr[0] >> 15) & 0x1) 877 mmc->version = SD_VERSION_3; 878 break; 879 default: 880 mmc->version = SD_VERSION_1_0; 881 break; 882 } 883 884 if (mmc->scr[0] & SD_DATA_4BIT) 885 mmc->card_caps |= MMC_MODE_4BIT; 886 887 /* Version 1.0 doesn't support switching */ 888 if (mmc->version == SD_VERSION_1_0) 889 return 0; 890 891 timeout = 4; 892 while (timeout--) { 893 err = sd_switch(mmc, SD_SWITCH_CHECK, 0, 1, 894 (u8 *)switch_status); 895 896 if (err) 897 return err; 898 899 /* The high-speed function is busy. Try again */ 900 if (!(__be32_to_cpu(switch_status[7]) & SD_HIGHSPEED_BUSY)) 901 break; 902 } 903 904 /* If high-speed isn't supported, we return */ 905 if (!(__be32_to_cpu(switch_status[3]) & SD_HIGHSPEED_SUPPORTED)) 906 return 0; 907 908 /* 909 * If the host doesn't support SD_HIGHSPEED, do not switch card to 910 * HIGHSPEED mode even if the card support SD_HIGHSPPED. 911 * This can avoid furthur problem when the card runs in different 912 * mode between the host. 913 */ 914 if (!((mmc->cfg->host_caps & MMC_MODE_HS_52MHz) && 915 (mmc->cfg->host_caps & MMC_MODE_HS))) 916 return 0; 917 918 err = sd_switch(mmc, SD_SWITCH_SWITCH, 0, 1, (u8 *)switch_status); 919 920 if (err) 921 return err; 922 923 if ((__be32_to_cpu(switch_status[4]) & 0x0f000000) == 0x01000000) 924 mmc->card_caps |= MMC_MODE_HS; 925 926 return 0; 927 } 928 929 /* frequency bases */ 930 /* divided by 10 to be nice to platforms without floating point */ 931 static const int fbase[] = { 932 10000, 933 100000, 934 1000000, 935 10000000, 936 }; 937 938 /* Multiplier values for TRAN_SPEED. Multiplied by 10 to be nice 939 * to platforms without floating point. 940 */ 941 static const u8 multipliers[] = { 942 0, /* reserved */ 943 10, 944 12, 945 13, 946 15, 947 20, 948 25, 949 30, 950 35, 951 40, 952 45, 953 50, 954 55, 955 60, 956 70, 957 80, 958 }; 959 960 static void mmc_set_ios(struct mmc *mmc) 961 { 962 if (mmc->cfg->ops->set_ios) 963 mmc->cfg->ops->set_ios(mmc); 964 } 965 966 void mmc_set_clock(struct mmc *mmc, uint clock) 967 { 968 if (clock > mmc->cfg->f_max) 969 clock = mmc->cfg->f_max; 970 971 if (clock < mmc->cfg->f_min) 972 clock = mmc->cfg->f_min; 973 974 mmc->clock = clock; 975 976 mmc_set_ios(mmc); 977 } 978 979 static void mmc_set_bus_width(struct mmc *mmc, uint width) 980 { 981 mmc->bus_width = width; 982 983 mmc_set_ios(mmc); 984 } 985 986 static int mmc_startup(struct mmc *mmc) 987 { 988 int err, i; 989 uint mult, freq; 990 u64 cmult, csize, capacity; 991 struct mmc_cmd cmd; 992 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN); 993 ALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, MMC_MAX_BLOCK_LEN); 994 int timeout = 1000; 995 bool has_parts = false; 996 bool part_completed; 997 struct blk_desc *bdesc; 998 999 #ifdef CONFIG_MMC_SPI_CRC_ON 1000 if (mmc_host_is_spi(mmc)) { /* enable CRC check for spi */ 1001 cmd.cmdidx = MMC_CMD_SPI_CRC_ON_OFF; 1002 cmd.resp_type = MMC_RSP_R1; 1003 cmd.cmdarg = 1; 1004 err = mmc_send_cmd(mmc, &cmd, NULL); 1005 1006 if (err) 1007 return err; 1008 } 1009 #endif 1010 1011 /* Put the Card in Identify Mode */ 1012 cmd.cmdidx = mmc_host_is_spi(mmc) ? MMC_CMD_SEND_CID : 1013 MMC_CMD_ALL_SEND_CID; /* cmd not supported in spi */ 1014 cmd.resp_type = MMC_RSP_R2; 1015 cmd.cmdarg = 0; 1016 1017 err = mmc_send_cmd(mmc, &cmd, NULL); 1018 1019 if (err) 1020 return err; 1021 1022 memcpy(mmc->cid, cmd.response, 16); 1023 1024 /* 1025 * For MMC cards, set the Relative Address. 1026 * For SD cards, get the Relatvie Address. 1027 * This also puts the cards into Standby State 1028 */ 1029 if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */ 1030 cmd.cmdidx = SD_CMD_SEND_RELATIVE_ADDR; 1031 cmd.cmdarg = mmc->rca << 16; 1032 cmd.resp_type = MMC_RSP_R6; 1033 1034 err = mmc_send_cmd(mmc, &cmd, NULL); 1035 1036 if (err) 1037 return err; 1038 1039 if (IS_SD(mmc)) 1040 mmc->rca = (cmd.response[0] >> 16) & 0xffff; 1041 } 1042 1043 /* Get the Card-Specific Data */ 1044 cmd.cmdidx = MMC_CMD_SEND_CSD; 1045 cmd.resp_type = MMC_RSP_R2; 1046 cmd.cmdarg = mmc->rca << 16; 1047 1048 err = mmc_send_cmd(mmc, &cmd, NULL); 1049 1050 /* Waiting for the ready status */ 1051 mmc_send_status(mmc, timeout); 1052 1053 if (err) 1054 return err; 1055 1056 mmc->csd[0] = cmd.response[0]; 1057 mmc->csd[1] = cmd.response[1]; 1058 mmc->csd[2] = cmd.response[2]; 1059 mmc->csd[3] = cmd.response[3]; 1060 1061 if (mmc->version == MMC_VERSION_UNKNOWN) { 1062 int version = (cmd.response[0] >> 26) & 0xf; 1063 1064 switch (version) { 1065 case 0: 1066 mmc->version = MMC_VERSION_1_2; 1067 break; 1068 case 1: 1069 mmc->version = MMC_VERSION_1_4; 1070 break; 1071 case 2: 1072 mmc->version = MMC_VERSION_2_2; 1073 break; 1074 case 3: 1075 mmc->version = MMC_VERSION_3; 1076 break; 1077 case 4: 1078 mmc->version = MMC_VERSION_4; 1079 break; 1080 default: 1081 mmc->version = MMC_VERSION_1_2; 1082 break; 1083 } 1084 } 1085 1086 /* divide frequency by 10, since the mults are 10x bigger */ 1087 freq = fbase[(cmd.response[0] & 0x7)]; 1088 mult = multipliers[((cmd.response[0] >> 3) & 0xf)]; 1089 1090 mmc->tran_speed = freq * mult; 1091 1092 mmc->dsr_imp = ((cmd.response[1] >> 12) & 0x1); 1093 mmc->read_bl_len = 1 << ((cmd.response[1] >> 16) & 0xf); 1094 1095 if (IS_SD(mmc)) 1096 mmc->write_bl_len = mmc->read_bl_len; 1097 else 1098 mmc->write_bl_len = 1 << ((cmd.response[3] >> 22) & 0xf); 1099 1100 if (mmc->high_capacity) { 1101 csize = (mmc->csd[1] & 0x3f) << 16 1102 | (mmc->csd[2] & 0xffff0000) >> 16; 1103 cmult = 8; 1104 } else { 1105 csize = (mmc->csd[1] & 0x3ff) << 2 1106 | (mmc->csd[2] & 0xc0000000) >> 30; 1107 cmult = (mmc->csd[2] & 0x00038000) >> 15; 1108 } 1109 1110 mmc->capacity_user = (csize + 1) << (cmult + 2); 1111 mmc->capacity_user *= mmc->read_bl_len; 1112 mmc->capacity_boot = 0; 1113 mmc->capacity_rpmb = 0; 1114 for (i = 0; i < 4; i++) 1115 mmc->capacity_gp[i] = 0; 1116 1117 if (mmc->read_bl_len > MMC_MAX_BLOCK_LEN) 1118 mmc->read_bl_len = MMC_MAX_BLOCK_LEN; 1119 1120 if (mmc->write_bl_len > MMC_MAX_BLOCK_LEN) 1121 mmc->write_bl_len = MMC_MAX_BLOCK_LEN; 1122 1123 if ((mmc->dsr_imp) && (0xffffffff != mmc->dsr)) { 1124 cmd.cmdidx = MMC_CMD_SET_DSR; 1125 cmd.cmdarg = (mmc->dsr & 0xffff) << 16; 1126 cmd.resp_type = MMC_RSP_NONE; 1127 if (mmc_send_cmd(mmc, &cmd, NULL)) 1128 printf("MMC: SET_DSR failed\n"); 1129 } 1130 1131 /* Select the card, and put it into Transfer Mode */ 1132 if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */ 1133 cmd.cmdidx = MMC_CMD_SELECT_CARD; 1134 cmd.resp_type = MMC_RSP_R1; 1135 cmd.cmdarg = mmc->rca << 16; 1136 err = mmc_send_cmd(mmc, &cmd, NULL); 1137 1138 if (err) 1139 return err; 1140 } 1141 1142 /* 1143 * For SD, its erase group is always one sector 1144 */ 1145 mmc->erase_grp_size = 1; 1146 mmc->part_config = MMCPART_NOAVAILABLE; 1147 if (!IS_SD(mmc) && (mmc->version >= MMC_VERSION_4)) { 1148 /* check ext_csd version and capacity */ 1149 err = mmc_send_ext_csd(mmc, ext_csd); 1150 if (err) 1151 return err; 1152 if (ext_csd[EXT_CSD_REV] >= 2) { 1153 /* 1154 * According to the JEDEC Standard, the value of 1155 * ext_csd's capacity is valid if the value is more 1156 * than 2GB 1157 */ 1158 capacity = ext_csd[EXT_CSD_SEC_CNT] << 0 1159 | ext_csd[EXT_CSD_SEC_CNT + 1] << 8 1160 | ext_csd[EXT_CSD_SEC_CNT + 2] << 16 1161 | ext_csd[EXT_CSD_SEC_CNT + 3] << 24; 1162 capacity *= MMC_MAX_BLOCK_LEN; 1163 if ((capacity >> 20) > 2 * 1024) 1164 mmc->capacity_user = capacity; 1165 } 1166 1167 switch (ext_csd[EXT_CSD_REV]) { 1168 case 1: 1169 mmc->version = MMC_VERSION_4_1; 1170 break; 1171 case 2: 1172 mmc->version = MMC_VERSION_4_2; 1173 break; 1174 case 3: 1175 mmc->version = MMC_VERSION_4_3; 1176 break; 1177 case 5: 1178 mmc->version = MMC_VERSION_4_41; 1179 break; 1180 case 6: 1181 mmc->version = MMC_VERSION_4_5; 1182 break; 1183 case 7: 1184 mmc->version = MMC_VERSION_5_0; 1185 break; 1186 case 8: 1187 mmc->version = MMC_VERSION_5_1; 1188 break; 1189 } 1190 1191 /* The partition data may be non-zero but it is only 1192 * effective if PARTITION_SETTING_COMPLETED is set in 1193 * EXT_CSD, so ignore any data if this bit is not set, 1194 * except for enabling the high-capacity group size 1195 * definition (see below). */ 1196 part_completed = !!(ext_csd[EXT_CSD_PARTITION_SETTING] & 1197 EXT_CSD_PARTITION_SETTING_COMPLETED); 1198 1199 /* store the partition info of emmc */ 1200 mmc->part_support = ext_csd[EXT_CSD_PARTITIONING_SUPPORT]; 1201 if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) || 1202 ext_csd[EXT_CSD_BOOT_MULT]) 1203 mmc->part_config = ext_csd[EXT_CSD_PART_CONF]; 1204 if (part_completed && 1205 (ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & ENHNCD_SUPPORT)) 1206 mmc->part_attr = ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE]; 1207 1208 mmc->capacity_boot = ext_csd[EXT_CSD_BOOT_MULT] << 17; 1209 1210 mmc->capacity_rpmb = ext_csd[EXT_CSD_RPMB_MULT] << 17; 1211 1212 for (i = 0; i < 4; i++) { 1213 int idx = EXT_CSD_GP_SIZE_MULT + i * 3; 1214 uint mult = (ext_csd[idx + 2] << 16) + 1215 (ext_csd[idx + 1] << 8) + ext_csd[idx]; 1216 if (mult) 1217 has_parts = true; 1218 if (!part_completed) 1219 continue; 1220 mmc->capacity_gp[i] = mult; 1221 mmc->capacity_gp[i] *= 1222 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]; 1223 mmc->capacity_gp[i] *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE]; 1224 mmc->capacity_gp[i] <<= 19; 1225 } 1226 1227 if (part_completed) { 1228 mmc->enh_user_size = 1229 (ext_csd[EXT_CSD_ENH_SIZE_MULT+2] << 16) + 1230 (ext_csd[EXT_CSD_ENH_SIZE_MULT+1] << 8) + 1231 ext_csd[EXT_CSD_ENH_SIZE_MULT]; 1232 mmc->enh_user_size *= ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]; 1233 mmc->enh_user_size *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE]; 1234 mmc->enh_user_size <<= 19; 1235 mmc->enh_user_start = 1236 (ext_csd[EXT_CSD_ENH_START_ADDR+3] << 24) + 1237 (ext_csd[EXT_CSD_ENH_START_ADDR+2] << 16) + 1238 (ext_csd[EXT_CSD_ENH_START_ADDR+1] << 8) + 1239 ext_csd[EXT_CSD_ENH_START_ADDR]; 1240 if (mmc->high_capacity) 1241 mmc->enh_user_start <<= 9; 1242 } 1243 1244 /* 1245 * Host needs to enable ERASE_GRP_DEF bit if device is 1246 * partitioned. This bit will be lost every time after a reset 1247 * or power off. This will affect erase size. 1248 */ 1249 if (part_completed) 1250 has_parts = true; 1251 if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) && 1252 (ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE] & PART_ENH_ATTRIB)) 1253 has_parts = true; 1254 if (has_parts) { 1255 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, 1256 EXT_CSD_ERASE_GROUP_DEF, 1); 1257 1258 if (err) 1259 return err; 1260 else 1261 ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1; 1262 } 1263 1264 if (ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01) { 1265 /* Read out group size from ext_csd */ 1266 mmc->erase_grp_size = 1267 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024; 1268 /* 1269 * if high capacity and partition setting completed 1270 * SEC_COUNT is valid even if it is smaller than 2 GiB 1271 * JEDEC Standard JESD84-B45, 6.2.4 1272 */ 1273 if (mmc->high_capacity && part_completed) { 1274 capacity = (ext_csd[EXT_CSD_SEC_CNT]) | 1275 (ext_csd[EXT_CSD_SEC_CNT + 1] << 8) | 1276 (ext_csd[EXT_CSD_SEC_CNT + 2] << 16) | 1277 (ext_csd[EXT_CSD_SEC_CNT + 3] << 24); 1278 capacity *= MMC_MAX_BLOCK_LEN; 1279 mmc->capacity_user = capacity; 1280 } 1281 } else { 1282 /* Calculate the group size from the csd value. */ 1283 int erase_gsz, erase_gmul; 1284 erase_gsz = (mmc->csd[2] & 0x00007c00) >> 10; 1285 erase_gmul = (mmc->csd[2] & 0x000003e0) >> 5; 1286 mmc->erase_grp_size = (erase_gsz + 1) 1287 * (erase_gmul + 1); 1288 } 1289 1290 mmc->hc_wp_grp_size = 1024 1291 * ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] 1292 * ext_csd[EXT_CSD_HC_WP_GRP_SIZE]; 1293 1294 mmc->wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET]; 1295 } 1296 1297 err = mmc_set_capacity(mmc, mmc_get_blk_desc(mmc)->hwpart); 1298 if (err) 1299 return err; 1300 1301 if (IS_SD(mmc)) 1302 err = sd_change_freq(mmc); 1303 else 1304 err = mmc_change_freq(mmc); 1305 1306 if (err) 1307 return err; 1308 1309 /* Restrict card's capabilities by what the host can do */ 1310 mmc->card_caps &= mmc->cfg->host_caps; 1311 1312 if (IS_SD(mmc)) { 1313 if (mmc->card_caps & MMC_MODE_4BIT) { 1314 cmd.cmdidx = MMC_CMD_APP_CMD; 1315 cmd.resp_type = MMC_RSP_R1; 1316 cmd.cmdarg = mmc->rca << 16; 1317 1318 err = mmc_send_cmd(mmc, &cmd, NULL); 1319 if (err) 1320 return err; 1321 1322 cmd.cmdidx = SD_CMD_APP_SET_BUS_WIDTH; 1323 cmd.resp_type = MMC_RSP_R1; 1324 cmd.cmdarg = 2; 1325 err = mmc_send_cmd(mmc, &cmd, NULL); 1326 if (err) 1327 return err; 1328 1329 mmc_set_bus_width(mmc, 4); 1330 } 1331 1332 if (mmc->card_caps & MMC_MODE_HS) 1333 mmc->tran_speed = 50000000; 1334 else 1335 mmc->tran_speed = 25000000; 1336 } else if (mmc->version >= MMC_VERSION_4) { 1337 /* Only version 4 of MMC supports wider bus widths */ 1338 int idx; 1339 1340 /* An array of possible bus widths in order of preference */ 1341 static unsigned ext_csd_bits[] = { 1342 EXT_CSD_DDR_BUS_WIDTH_8, 1343 EXT_CSD_DDR_BUS_WIDTH_4, 1344 EXT_CSD_BUS_WIDTH_8, 1345 EXT_CSD_BUS_WIDTH_4, 1346 EXT_CSD_BUS_WIDTH_1, 1347 }; 1348 1349 /* An array to map CSD bus widths to host cap bits */ 1350 static unsigned ext_to_hostcaps[] = { 1351 [EXT_CSD_DDR_BUS_WIDTH_4] = 1352 MMC_MODE_DDR_52MHz | MMC_MODE_4BIT, 1353 [EXT_CSD_DDR_BUS_WIDTH_8] = 1354 MMC_MODE_DDR_52MHz | MMC_MODE_8BIT, 1355 [EXT_CSD_BUS_WIDTH_4] = MMC_MODE_4BIT, 1356 [EXT_CSD_BUS_WIDTH_8] = MMC_MODE_8BIT, 1357 }; 1358 1359 /* An array to map chosen bus width to an integer */ 1360 static unsigned widths[] = { 1361 8, 4, 8, 4, 1, 1362 }; 1363 1364 for (idx=0; idx < ARRAY_SIZE(ext_csd_bits); idx++) { 1365 unsigned int extw = ext_csd_bits[idx]; 1366 unsigned int caps = ext_to_hostcaps[extw]; 1367 1368 /* 1369 * If the bus width is still not changed, 1370 * don't try to set the default again. 1371 * Otherwise, recover from switch attempts 1372 * by switching to 1-bit bus width. 1373 */ 1374 if (extw == EXT_CSD_BUS_WIDTH_1 && 1375 mmc->bus_width == 1) { 1376 err = 0; 1377 break; 1378 } 1379 1380 /* 1381 * Check to make sure the card and controller support 1382 * these capabilities 1383 */ 1384 if ((mmc->card_caps & caps) != caps) 1385 continue; 1386 1387 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, 1388 EXT_CSD_BUS_WIDTH, extw); 1389 1390 if (err) 1391 continue; 1392 1393 mmc->ddr_mode = (caps & MMC_MODE_DDR_52MHz) ? 1 : 0; 1394 mmc_set_bus_width(mmc, widths[idx]); 1395 1396 err = mmc_send_ext_csd(mmc, test_csd); 1397 1398 if (err) 1399 continue; 1400 1401 /* Only compare read only fields */ 1402 if (ext_csd[EXT_CSD_PARTITIONING_SUPPORT] 1403 == test_csd[EXT_CSD_PARTITIONING_SUPPORT] && 1404 ext_csd[EXT_CSD_HC_WP_GRP_SIZE] 1405 == test_csd[EXT_CSD_HC_WP_GRP_SIZE] && 1406 ext_csd[EXT_CSD_REV] 1407 == test_csd[EXT_CSD_REV] && 1408 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] 1409 == test_csd[EXT_CSD_HC_ERASE_GRP_SIZE] && 1410 memcmp(&ext_csd[EXT_CSD_SEC_CNT], 1411 &test_csd[EXT_CSD_SEC_CNT], 4) == 0) 1412 break; 1413 else 1414 err = SWITCH_ERR; 1415 } 1416 1417 if (err) 1418 return err; 1419 1420 if (mmc->card_caps & MMC_MODE_HS) { 1421 if (mmc->card_caps & MMC_MODE_HS_52MHz) 1422 mmc->tran_speed = 52000000; 1423 else 1424 mmc->tran_speed = 26000000; 1425 } 1426 } 1427 1428 mmc_set_clock(mmc, mmc->tran_speed); 1429 1430 /* Fix the block length for DDR mode */ 1431 if (mmc->ddr_mode) { 1432 mmc->read_bl_len = MMC_MAX_BLOCK_LEN; 1433 mmc->write_bl_len = MMC_MAX_BLOCK_LEN; 1434 } 1435 1436 /* fill in device description */ 1437 bdesc = mmc_get_blk_desc(mmc); 1438 bdesc->lun = 0; 1439 bdesc->hwpart = 0; 1440 bdesc->type = 0; 1441 bdesc->blksz = mmc->read_bl_len; 1442 bdesc->log2blksz = LOG2(bdesc->blksz); 1443 bdesc->lba = lldiv(mmc->capacity, mmc->read_bl_len); 1444 #if !defined(CONFIG_SPL_BUILD) || \ 1445 (defined(CONFIG_SPL_LIBCOMMON_SUPPORT) && \ 1446 !defined(CONFIG_USE_TINY_PRINTF)) 1447 sprintf(bdesc->vendor, "Man %06x Snr %04x%04x", 1448 mmc->cid[0] >> 24, (mmc->cid[2] & 0xffff), 1449 (mmc->cid[3] >> 16) & 0xffff); 1450 sprintf(bdesc->product, "%c%c%c%c%c%c", mmc->cid[0] & 0xff, 1451 (mmc->cid[1] >> 24), (mmc->cid[1] >> 16) & 0xff, 1452 (mmc->cid[1] >> 8) & 0xff, mmc->cid[1] & 0xff, 1453 (mmc->cid[2] >> 24) & 0xff); 1454 sprintf(bdesc->revision, "%d.%d", (mmc->cid[2] >> 20) & 0xf, 1455 (mmc->cid[2] >> 16) & 0xf); 1456 #else 1457 bdesc->vendor[0] = 0; 1458 bdesc->product[0] = 0; 1459 bdesc->revision[0] = 0; 1460 #endif 1461 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBDISK_SUPPORT) 1462 part_init(bdesc); 1463 #endif 1464 1465 return 0; 1466 } 1467 1468 static int mmc_send_if_cond(struct mmc *mmc) 1469 { 1470 struct mmc_cmd cmd; 1471 int err; 1472 1473 cmd.cmdidx = SD_CMD_SEND_IF_COND; 1474 /* We set the bit if the host supports voltages between 2.7 and 3.6 V */ 1475 cmd.cmdarg = ((mmc->cfg->voltages & 0xff8000) != 0) << 8 | 0xaa; 1476 cmd.resp_type = MMC_RSP_R7; 1477 1478 err = mmc_send_cmd(mmc, &cmd, NULL); 1479 1480 if (err) 1481 return err; 1482 1483 if ((cmd.response[0] & 0xff) != 0xaa) 1484 return UNUSABLE_ERR; 1485 else 1486 mmc->version = SD_VERSION_2; 1487 1488 return 0; 1489 } 1490 1491 /* board-specific MMC power initializations. */ 1492 __weak void board_mmc_power_init(void) 1493 { 1494 } 1495 1496 int mmc_start_init(struct mmc *mmc) 1497 { 1498 int err; 1499 1500 /* we pretend there's no card when init is NULL */ 1501 if (mmc_getcd(mmc) == 0 || mmc->cfg->ops->init == NULL) { 1502 mmc->has_init = 0; 1503 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) 1504 printf("MMC: no card present\n"); 1505 #endif 1506 return NO_CARD_ERR; 1507 } 1508 1509 if (mmc->has_init) 1510 return 0; 1511 1512 #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT 1513 mmc_adapter_card_type_ident(); 1514 #endif 1515 board_mmc_power_init(); 1516 1517 /* made sure it's not NULL earlier */ 1518 err = mmc->cfg->ops->init(mmc); 1519 1520 if (err) 1521 return err; 1522 1523 mmc->ddr_mode = 0; 1524 mmc_set_bus_width(mmc, 1); 1525 mmc_set_clock(mmc, 1); 1526 1527 /* Reset the Card */ 1528 err = mmc_go_idle(mmc); 1529 1530 if (err) 1531 return err; 1532 1533 /* The internal partition reset to user partition(0) at every CMD0*/ 1534 mmc_get_blk_desc(mmc)->hwpart = 0; 1535 1536 /* Test for SD version 2 */ 1537 err = mmc_send_if_cond(mmc); 1538 1539 /* Now try to get the SD card's operating condition */ 1540 err = sd_send_op_cond(mmc); 1541 1542 /* If the command timed out, we check for an MMC card */ 1543 if (err == TIMEOUT) { 1544 err = mmc_send_op_cond(mmc); 1545 1546 if (err) { 1547 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) 1548 printf("Card did not respond to voltage select!\n"); 1549 #endif 1550 return UNUSABLE_ERR; 1551 } 1552 } 1553 1554 if (!err) 1555 mmc->init_in_progress = 1; 1556 1557 return err; 1558 } 1559 1560 static int mmc_complete_init(struct mmc *mmc) 1561 { 1562 int err = 0; 1563 1564 mmc->init_in_progress = 0; 1565 if (mmc->op_cond_pending) 1566 err = mmc_complete_op_cond(mmc); 1567 1568 if (!err) 1569 err = mmc_startup(mmc); 1570 if (err) 1571 mmc->has_init = 0; 1572 else 1573 mmc->has_init = 1; 1574 return err; 1575 } 1576 1577 int mmc_init(struct mmc *mmc) 1578 { 1579 int err = 0; 1580 unsigned start; 1581 #ifdef CONFIG_DM_MMC 1582 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(mmc->dev); 1583 1584 upriv->mmc = mmc; 1585 #endif 1586 if (mmc->has_init) 1587 return 0; 1588 1589 start = get_timer(0); 1590 1591 if (!mmc->init_in_progress) 1592 err = mmc_start_init(mmc); 1593 1594 if (!err) 1595 err = mmc_complete_init(mmc); 1596 debug("%s: %d, time %lu\n", __func__, err, get_timer(start)); 1597 return err; 1598 } 1599 1600 int mmc_set_dsr(struct mmc *mmc, u16 val) 1601 { 1602 mmc->dsr = val; 1603 return 0; 1604 } 1605 1606 /* CPU-specific MMC initializations */ 1607 __weak int cpu_mmc_init(bd_t *bis) 1608 { 1609 return -1; 1610 } 1611 1612 /* board-specific MMC initializations. */ 1613 __weak int board_mmc_init(bd_t *bis) 1614 { 1615 return -1; 1616 } 1617 1618 void mmc_set_preinit(struct mmc *mmc, int preinit) 1619 { 1620 mmc->preinit = preinit; 1621 } 1622 1623 #if defined(CONFIG_DM_MMC) && defined(CONFIG_SPL_BUILD) 1624 static int mmc_probe(bd_t *bis) 1625 { 1626 return 0; 1627 } 1628 #elif defined(CONFIG_DM_MMC) 1629 static int mmc_probe(bd_t *bis) 1630 { 1631 int ret, i; 1632 struct uclass *uc; 1633 struct udevice *dev; 1634 1635 ret = uclass_get(UCLASS_MMC, &uc); 1636 if (ret) 1637 return ret; 1638 1639 /* 1640 * Try to add them in sequence order. Really with driver model we 1641 * should allow holes, but the current MMC list does not allow that. 1642 * So if we request 0, 1, 3 we will get 0, 1, 2. 1643 */ 1644 for (i = 0; ; i++) { 1645 ret = uclass_get_device_by_seq(UCLASS_MMC, i, &dev); 1646 if (ret == -ENODEV) 1647 break; 1648 } 1649 uclass_foreach_dev(dev, uc) { 1650 ret = device_probe(dev); 1651 if (ret) 1652 printf("%s - probe failed: %d\n", dev->name, ret); 1653 } 1654 1655 return 0; 1656 } 1657 #else 1658 static int mmc_probe(bd_t *bis) 1659 { 1660 if (board_mmc_init(bis) < 0) 1661 cpu_mmc_init(bis); 1662 1663 return 0; 1664 } 1665 #endif 1666 1667 int mmc_initialize(bd_t *bis) 1668 { 1669 static int initialized = 0; 1670 int ret; 1671 if (initialized) /* Avoid initializing mmc multiple times */ 1672 return 0; 1673 initialized = 1; 1674 1675 #ifndef CONFIG_BLK 1676 mmc_list_init(); 1677 #endif 1678 ret = mmc_probe(bis); 1679 if (ret) 1680 return ret; 1681 1682 #ifndef CONFIG_SPL_BUILD 1683 print_mmc_devices(','); 1684 #endif 1685 1686 mmc_do_preinit(); 1687 return 0; 1688 } 1689 1690 #ifdef CONFIG_SUPPORT_EMMC_BOOT 1691 /* 1692 * This function changes the size of boot partition and the size of rpmb 1693 * partition present on EMMC devices. 1694 * 1695 * Input Parameters: 1696 * struct *mmc: pointer for the mmc device strcuture 1697 * bootsize: size of boot partition 1698 * rpmbsize: size of rpmb partition 1699 * 1700 * Returns 0 on success. 1701 */ 1702 1703 int mmc_boot_partition_size_change(struct mmc *mmc, unsigned long bootsize, 1704 unsigned long rpmbsize) 1705 { 1706 int err; 1707 struct mmc_cmd cmd; 1708 1709 /* Only use this command for raw EMMC moviNAND. Enter backdoor mode */ 1710 cmd.cmdidx = MMC_CMD_RES_MAN; 1711 cmd.resp_type = MMC_RSP_R1b; 1712 cmd.cmdarg = MMC_CMD62_ARG1; 1713 1714 err = mmc_send_cmd(mmc, &cmd, NULL); 1715 if (err) { 1716 debug("mmc_boot_partition_size_change: Error1 = %d\n", err); 1717 return err; 1718 } 1719 1720 /* Boot partition changing mode */ 1721 cmd.cmdidx = MMC_CMD_RES_MAN; 1722 cmd.resp_type = MMC_RSP_R1b; 1723 cmd.cmdarg = MMC_CMD62_ARG2; 1724 1725 err = mmc_send_cmd(mmc, &cmd, NULL); 1726 if (err) { 1727 debug("mmc_boot_partition_size_change: Error2 = %d\n", err); 1728 return err; 1729 } 1730 /* boot partition size is multiple of 128KB */ 1731 bootsize = (bootsize * 1024) / 128; 1732 1733 /* Arg: boot partition size */ 1734 cmd.cmdidx = MMC_CMD_RES_MAN; 1735 cmd.resp_type = MMC_RSP_R1b; 1736 cmd.cmdarg = bootsize; 1737 1738 err = mmc_send_cmd(mmc, &cmd, NULL); 1739 if (err) { 1740 debug("mmc_boot_partition_size_change: Error3 = %d\n", err); 1741 return err; 1742 } 1743 /* RPMB partition size is multiple of 128KB */ 1744 rpmbsize = (rpmbsize * 1024) / 128; 1745 /* Arg: RPMB partition size */ 1746 cmd.cmdidx = MMC_CMD_RES_MAN; 1747 cmd.resp_type = MMC_RSP_R1b; 1748 cmd.cmdarg = rpmbsize; 1749 1750 err = mmc_send_cmd(mmc, &cmd, NULL); 1751 if (err) { 1752 debug("mmc_boot_partition_size_change: Error4 = %d\n", err); 1753 return err; 1754 } 1755 return 0; 1756 } 1757 1758 /* 1759 * Modify EXT_CSD[177] which is BOOT_BUS_WIDTH 1760 * based on the passed in values for BOOT_BUS_WIDTH, RESET_BOOT_BUS_WIDTH 1761 * and BOOT_MODE. 1762 * 1763 * Returns 0 on success. 1764 */ 1765 int mmc_set_boot_bus_width(struct mmc *mmc, u8 width, u8 reset, u8 mode) 1766 { 1767 int err; 1768 1769 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BOOT_BUS_WIDTH, 1770 EXT_CSD_BOOT_BUS_WIDTH_MODE(mode) | 1771 EXT_CSD_BOOT_BUS_WIDTH_RESET(reset) | 1772 EXT_CSD_BOOT_BUS_WIDTH_WIDTH(width)); 1773 1774 if (err) 1775 return err; 1776 return 0; 1777 } 1778 1779 /* 1780 * Modify EXT_CSD[179] which is PARTITION_CONFIG (formerly BOOT_CONFIG) 1781 * based on the passed in values for BOOT_ACK, BOOT_PARTITION_ENABLE and 1782 * PARTITION_ACCESS. 1783 * 1784 * Returns 0 on success. 1785 */ 1786 int mmc_set_part_conf(struct mmc *mmc, u8 ack, u8 part_num, u8 access) 1787 { 1788 int err; 1789 1790 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_PART_CONF, 1791 EXT_CSD_BOOT_ACK(ack) | 1792 EXT_CSD_BOOT_PART_NUM(part_num) | 1793 EXT_CSD_PARTITION_ACCESS(access)); 1794 1795 if (err) 1796 return err; 1797 return 0; 1798 } 1799 1800 /* 1801 * Modify EXT_CSD[162] which is RST_n_FUNCTION based on the given value 1802 * for enable. Note that this is a write-once field for non-zero values. 1803 * 1804 * Returns 0 on success. 1805 */ 1806 int mmc_set_rst_n_function(struct mmc *mmc, u8 enable) 1807 { 1808 return mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_RST_N_FUNCTION, 1809 enable); 1810 } 1811 #endif 1812