1 /* 2 * Copyright 2008, Freescale Semiconductor, Inc 3 * Andy Fleming 4 * 5 * Based vaguely on the Linux code 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #include <config.h> 11 #include <common.h> 12 #include <command.h> 13 #include <errno.h> 14 #include <mmc.h> 15 #include <part.h> 16 #include <malloc.h> 17 #include <linux/list.h> 18 #include <div64.h> 19 #include "mmc_private.h" 20 21 static struct list_head mmc_devices; 22 static int cur_dev_num = -1; 23 24 __weak int board_mmc_getwp(struct mmc *mmc) 25 { 26 return -1; 27 } 28 29 int mmc_getwp(struct mmc *mmc) 30 { 31 int wp; 32 33 wp = board_mmc_getwp(mmc); 34 35 if (wp < 0) { 36 if (mmc->cfg->ops->getwp) 37 wp = mmc->cfg->ops->getwp(mmc); 38 else 39 wp = 0; 40 } 41 42 return wp; 43 } 44 45 __weak int board_mmc_getcd(struct mmc *mmc) 46 { 47 return -1; 48 } 49 50 int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) 51 { 52 int ret; 53 54 #ifdef CONFIG_MMC_TRACE 55 int i; 56 u8 *ptr; 57 58 printf("CMD_SEND:%d\n", cmd->cmdidx); 59 printf("\t\tARG\t\t\t 0x%08X\n", cmd->cmdarg); 60 ret = mmc->cfg->ops->send_cmd(mmc, cmd, data); 61 switch (cmd->resp_type) { 62 case MMC_RSP_NONE: 63 printf("\t\tMMC_RSP_NONE\n"); 64 break; 65 case MMC_RSP_R1: 66 printf("\t\tMMC_RSP_R1,5,6,7 \t 0x%08X \n", 67 cmd->response[0]); 68 break; 69 case MMC_RSP_R1b: 70 printf("\t\tMMC_RSP_R1b\t\t 0x%08X \n", 71 cmd->response[0]); 72 break; 73 case MMC_RSP_R2: 74 printf("\t\tMMC_RSP_R2\t\t 0x%08X \n", 75 cmd->response[0]); 76 printf("\t\t \t\t 0x%08X \n", 77 cmd->response[1]); 78 printf("\t\t \t\t 0x%08X \n", 79 cmd->response[2]); 80 printf("\t\t \t\t 0x%08X \n", 81 cmd->response[3]); 82 printf("\n"); 83 printf("\t\t\t\t\tDUMPING DATA\n"); 84 for (i = 0; i < 4; i++) { 85 int j; 86 printf("\t\t\t\t\t%03d - ", i*4); 87 ptr = (u8 *)&cmd->response[i]; 88 ptr += 3; 89 for (j = 0; j < 4; j++) 90 printf("%02X ", *ptr--); 91 printf("\n"); 92 } 93 break; 94 case MMC_RSP_R3: 95 printf("\t\tMMC_RSP_R3,4\t\t 0x%08X \n", 96 cmd->response[0]); 97 break; 98 default: 99 printf("\t\tERROR MMC rsp not supported\n"); 100 break; 101 } 102 #else 103 ret = mmc->cfg->ops->send_cmd(mmc, cmd, data); 104 #endif 105 return ret; 106 } 107 108 int mmc_send_status(struct mmc *mmc, int timeout) 109 { 110 struct mmc_cmd cmd; 111 int err, retries = 5; 112 #ifdef CONFIG_MMC_TRACE 113 int status; 114 #endif 115 116 cmd.cmdidx = MMC_CMD_SEND_STATUS; 117 cmd.resp_type = MMC_RSP_R1; 118 if (!mmc_host_is_spi(mmc)) 119 cmd.cmdarg = mmc->rca << 16; 120 121 do { 122 err = mmc_send_cmd(mmc, &cmd, NULL); 123 if (!err) { 124 if ((cmd.response[0] & MMC_STATUS_RDY_FOR_DATA) && 125 (cmd.response[0] & MMC_STATUS_CURR_STATE) != 126 MMC_STATE_PRG) 127 break; 128 else if (cmd.response[0] & MMC_STATUS_MASK) { 129 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) 130 printf("Status Error: 0x%08X\n", 131 cmd.response[0]); 132 #endif 133 return COMM_ERR; 134 } 135 } else if (--retries < 0) 136 return err; 137 138 udelay(1000); 139 140 } while (timeout--); 141 142 #ifdef CONFIG_MMC_TRACE 143 status = (cmd.response[0] & MMC_STATUS_CURR_STATE) >> 9; 144 printf("CURR STATE:%d\n", status); 145 #endif 146 if (timeout <= 0) { 147 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) 148 printf("Timeout waiting card ready\n"); 149 #endif 150 return TIMEOUT; 151 } 152 if (cmd.response[0] & MMC_STATUS_SWITCH_ERROR) 153 return SWITCH_ERR; 154 155 return 0; 156 } 157 158 int mmc_set_blocklen(struct mmc *mmc, int len) 159 { 160 struct mmc_cmd cmd; 161 162 if (mmc->ddr_mode) 163 return 0; 164 165 cmd.cmdidx = MMC_CMD_SET_BLOCKLEN; 166 cmd.resp_type = MMC_RSP_R1; 167 cmd.cmdarg = len; 168 169 return mmc_send_cmd(mmc, &cmd, NULL); 170 } 171 172 struct mmc *find_mmc_device(int dev_num) 173 { 174 struct mmc *m; 175 struct list_head *entry; 176 177 list_for_each(entry, &mmc_devices) { 178 m = list_entry(entry, struct mmc, link); 179 180 if (m->block_dev.dev == dev_num) 181 return m; 182 } 183 184 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) 185 printf("MMC Device %d not found\n", dev_num); 186 #endif 187 188 return NULL; 189 } 190 191 static int mmc_read_blocks(struct mmc *mmc, void *dst, lbaint_t start, 192 lbaint_t blkcnt) 193 { 194 struct mmc_cmd cmd; 195 struct mmc_data data; 196 197 if (blkcnt > 1) 198 cmd.cmdidx = MMC_CMD_READ_MULTIPLE_BLOCK; 199 else 200 cmd.cmdidx = MMC_CMD_READ_SINGLE_BLOCK; 201 202 if (mmc->high_capacity) 203 cmd.cmdarg = start; 204 else 205 cmd.cmdarg = start * mmc->read_bl_len; 206 207 cmd.resp_type = MMC_RSP_R1; 208 209 data.dest = dst; 210 data.blocks = blkcnt; 211 data.blocksize = mmc->read_bl_len; 212 data.flags = MMC_DATA_READ; 213 214 if (mmc_send_cmd(mmc, &cmd, &data)) 215 return 0; 216 217 if (blkcnt > 1) { 218 cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION; 219 cmd.cmdarg = 0; 220 cmd.resp_type = MMC_RSP_R1b; 221 if (mmc_send_cmd(mmc, &cmd, NULL)) { 222 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) 223 printf("mmc fail to send stop cmd\n"); 224 #endif 225 return 0; 226 } 227 } 228 229 return blkcnt; 230 } 231 232 static ulong mmc_bread(int dev_num, lbaint_t start, lbaint_t blkcnt, void *dst) 233 { 234 lbaint_t cur, blocks_todo = blkcnt; 235 236 if (blkcnt == 0) 237 return 0; 238 239 struct mmc *mmc = find_mmc_device(dev_num); 240 if (!mmc) 241 return 0; 242 243 if ((start + blkcnt) > mmc->block_dev.lba) { 244 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) 245 printf("MMC: block number 0x" LBAF " exceeds max(0x" LBAF ")\n", 246 start + blkcnt, mmc->block_dev.lba); 247 #endif 248 return 0; 249 } 250 251 if (mmc_set_blocklen(mmc, mmc->read_bl_len)) 252 return 0; 253 254 do { 255 cur = (blocks_todo > mmc->cfg->b_max) ? 256 mmc->cfg->b_max : blocks_todo; 257 if(mmc_read_blocks(mmc, dst, start, cur) != cur) 258 return 0; 259 blocks_todo -= cur; 260 start += cur; 261 dst += cur * mmc->read_bl_len; 262 } while (blocks_todo > 0); 263 264 return blkcnt; 265 } 266 267 static int mmc_go_idle(struct mmc *mmc) 268 { 269 struct mmc_cmd cmd; 270 int err; 271 272 udelay(1000); 273 274 cmd.cmdidx = MMC_CMD_GO_IDLE_STATE; 275 cmd.cmdarg = 0; 276 cmd.resp_type = MMC_RSP_NONE; 277 278 err = mmc_send_cmd(mmc, &cmd, NULL); 279 280 if (err) 281 return err; 282 283 udelay(2000); 284 285 return 0; 286 } 287 288 static int sd_send_op_cond(struct mmc *mmc) 289 { 290 int timeout = 1000; 291 int err; 292 struct mmc_cmd cmd; 293 294 do { 295 cmd.cmdidx = MMC_CMD_APP_CMD; 296 cmd.resp_type = MMC_RSP_R1; 297 cmd.cmdarg = 0; 298 299 err = mmc_send_cmd(mmc, &cmd, NULL); 300 301 if (err) 302 return err; 303 304 cmd.cmdidx = SD_CMD_APP_SEND_OP_COND; 305 cmd.resp_type = MMC_RSP_R3; 306 307 /* 308 * Most cards do not answer if some reserved bits 309 * in the ocr are set. However, Some controller 310 * can set bit 7 (reserved for low voltages), but 311 * how to manage low voltages SD card is not yet 312 * specified. 313 */ 314 cmd.cmdarg = mmc_host_is_spi(mmc) ? 0 : 315 (mmc->cfg->voltages & 0xff8000); 316 317 if (mmc->version == SD_VERSION_2) 318 cmd.cmdarg |= OCR_HCS; 319 320 err = mmc_send_cmd(mmc, &cmd, NULL); 321 322 if (err) 323 return err; 324 325 udelay(1000); 326 } while ((!(cmd.response[0] & OCR_BUSY)) && timeout--); 327 328 if (timeout <= 0) 329 return UNUSABLE_ERR; 330 331 if (mmc->version != SD_VERSION_2) 332 mmc->version = SD_VERSION_1_0; 333 334 if (mmc_host_is_spi(mmc)) { /* read OCR for spi */ 335 cmd.cmdidx = MMC_CMD_SPI_READ_OCR; 336 cmd.resp_type = MMC_RSP_R3; 337 cmd.cmdarg = 0; 338 339 err = mmc_send_cmd(mmc, &cmd, NULL); 340 341 if (err) 342 return err; 343 } 344 345 mmc->ocr = cmd.response[0]; 346 347 mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS); 348 mmc->rca = 0; 349 350 return 0; 351 } 352 353 static int mmc_send_op_cond_iter(struct mmc *mmc, int use_arg) 354 { 355 struct mmc_cmd cmd; 356 int err; 357 358 cmd.cmdidx = MMC_CMD_SEND_OP_COND; 359 cmd.resp_type = MMC_RSP_R3; 360 cmd.cmdarg = 0; 361 if (use_arg && !mmc_host_is_spi(mmc)) { 362 cmd.cmdarg = 363 (mmc->cfg->voltages & 364 (mmc->ocr & OCR_VOLTAGE_MASK)) | 365 (mmc->ocr & OCR_ACCESS_MODE); 366 367 if (mmc->cfg->host_caps & MMC_MODE_HC) 368 cmd.cmdarg |= OCR_HCS; 369 } 370 err = mmc_send_cmd(mmc, &cmd, NULL); 371 if (err) 372 return err; 373 mmc->ocr = cmd.response[0]; 374 return 0; 375 } 376 377 static int mmc_send_op_cond(struct mmc *mmc) 378 { 379 int err, i; 380 381 /* Some cards seem to need this */ 382 mmc_go_idle(mmc); 383 384 /* Asking to the card its capabilities */ 385 mmc->op_cond_pending = 1; 386 for (i = 0; i < 2; i++) { 387 err = mmc_send_op_cond_iter(mmc, i != 0); 388 if (err) 389 return err; 390 391 /* exit if not busy (flag seems to be inverted) */ 392 if (mmc->ocr & OCR_BUSY) 393 return 0; 394 } 395 return IN_PROGRESS; 396 } 397 398 static int mmc_complete_op_cond(struct mmc *mmc) 399 { 400 struct mmc_cmd cmd; 401 int timeout = 1000; 402 uint start; 403 int err; 404 405 mmc->op_cond_pending = 0; 406 start = get_timer(0); 407 do { 408 err = mmc_send_op_cond_iter(mmc, 1); 409 if (err) 410 return err; 411 if (get_timer(start) > timeout) 412 return UNUSABLE_ERR; 413 udelay(100); 414 } while (!(mmc->ocr & OCR_BUSY)); 415 416 if (mmc_host_is_spi(mmc)) { /* read OCR for spi */ 417 cmd.cmdidx = MMC_CMD_SPI_READ_OCR; 418 cmd.resp_type = MMC_RSP_R3; 419 cmd.cmdarg = 0; 420 421 err = mmc_send_cmd(mmc, &cmd, NULL); 422 423 if (err) 424 return err; 425 426 mmc->ocr = cmd.response[0]; 427 } 428 429 mmc->version = MMC_VERSION_UNKNOWN; 430 431 mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS); 432 mmc->rca = 1; 433 434 return 0; 435 } 436 437 438 static int mmc_send_ext_csd(struct mmc *mmc, u8 *ext_csd) 439 { 440 struct mmc_cmd cmd; 441 struct mmc_data data; 442 int err; 443 444 /* Get the Card Status Register */ 445 cmd.cmdidx = MMC_CMD_SEND_EXT_CSD; 446 cmd.resp_type = MMC_RSP_R1; 447 cmd.cmdarg = 0; 448 449 data.dest = (char *)ext_csd; 450 data.blocks = 1; 451 data.blocksize = MMC_MAX_BLOCK_LEN; 452 data.flags = MMC_DATA_READ; 453 454 err = mmc_send_cmd(mmc, &cmd, &data); 455 456 return err; 457 } 458 459 460 static int mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value) 461 { 462 struct mmc_cmd cmd; 463 int timeout = 1000; 464 int ret; 465 466 cmd.cmdidx = MMC_CMD_SWITCH; 467 cmd.resp_type = MMC_RSP_R1b; 468 cmd.cmdarg = (MMC_SWITCH_MODE_WRITE_BYTE << 24) | 469 (index << 16) | 470 (value << 8); 471 472 ret = mmc_send_cmd(mmc, &cmd, NULL); 473 474 /* Waiting for the ready status */ 475 if (!ret) 476 ret = mmc_send_status(mmc, timeout); 477 478 return ret; 479 480 } 481 482 static int mmc_change_freq(struct mmc *mmc) 483 { 484 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN); 485 char cardtype; 486 int err; 487 488 mmc->card_caps = 0; 489 490 if (mmc_host_is_spi(mmc)) 491 return 0; 492 493 /* Only version 4 supports high-speed */ 494 if (mmc->version < MMC_VERSION_4) 495 return 0; 496 497 mmc->card_caps |= MMC_MODE_4BIT | MMC_MODE_8BIT; 498 499 err = mmc_send_ext_csd(mmc, ext_csd); 500 501 if (err) 502 return err; 503 504 cardtype = ext_csd[EXT_CSD_CARD_TYPE] & 0xf; 505 506 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_HS_TIMING, 1); 507 508 if (err) 509 return err == SWITCH_ERR ? 0 : err; 510 511 /* Now check to see that it worked */ 512 err = mmc_send_ext_csd(mmc, ext_csd); 513 514 if (err) 515 return err; 516 517 /* No high-speed support */ 518 if (!ext_csd[EXT_CSD_HS_TIMING]) 519 return 0; 520 521 /* High Speed is set, there are two types: 52MHz and 26MHz */ 522 if (cardtype & EXT_CSD_CARD_TYPE_52) { 523 if (cardtype & EXT_CSD_CARD_TYPE_DDR_1_8V) 524 mmc->card_caps |= MMC_MODE_DDR_52MHz; 525 mmc->card_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS; 526 } else { 527 mmc->card_caps |= MMC_MODE_HS; 528 } 529 530 return 0; 531 } 532 533 static int mmc_set_capacity(struct mmc *mmc, int part_num) 534 { 535 switch (part_num) { 536 case 0: 537 mmc->capacity = mmc->capacity_user; 538 break; 539 case 1: 540 case 2: 541 mmc->capacity = mmc->capacity_boot; 542 break; 543 case 3: 544 mmc->capacity = mmc->capacity_rpmb; 545 break; 546 case 4: 547 case 5: 548 case 6: 549 case 7: 550 mmc->capacity = mmc->capacity_gp[part_num - 4]; 551 break; 552 default: 553 return -1; 554 } 555 556 mmc->block_dev.lba = lldiv(mmc->capacity, mmc->read_bl_len); 557 558 return 0; 559 } 560 561 int mmc_select_hwpart(int dev_num, int hwpart) 562 { 563 struct mmc *mmc = find_mmc_device(dev_num); 564 int ret; 565 566 if (!mmc) 567 return -ENODEV; 568 569 if (mmc->part_num == hwpart) 570 return 0; 571 572 if (mmc->part_config == MMCPART_NOAVAILABLE) { 573 printf("Card doesn't support part_switch\n"); 574 return -EMEDIUMTYPE; 575 } 576 577 ret = mmc_switch_part(dev_num, hwpart); 578 if (ret) 579 return ret; 580 581 mmc->part_num = hwpart; 582 583 return 0; 584 } 585 586 587 int mmc_switch_part(int dev_num, unsigned int part_num) 588 { 589 struct mmc *mmc = find_mmc_device(dev_num); 590 int ret; 591 592 if (!mmc) 593 return -1; 594 595 ret = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_PART_CONF, 596 (mmc->part_config & ~PART_ACCESS_MASK) 597 | (part_num & PART_ACCESS_MASK)); 598 599 /* 600 * Set the capacity if the switch succeeded or was intended 601 * to return to representing the raw device. 602 */ 603 if ((ret == 0) || ((ret == -ENODEV) && (part_num == 0))) 604 ret = mmc_set_capacity(mmc, part_num); 605 606 return ret; 607 } 608 609 int mmc_hwpart_config(struct mmc *mmc, 610 const struct mmc_hwpart_conf *conf, 611 enum mmc_hwpart_conf_mode mode) 612 { 613 u8 part_attrs = 0; 614 u32 enh_size_mult; 615 u32 enh_start_addr; 616 u32 gp_size_mult[4]; 617 u32 max_enh_size_mult; 618 u32 tot_enh_size_mult = 0; 619 u8 wr_rel_set; 620 int i, pidx, err; 621 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN); 622 623 if (mode < MMC_HWPART_CONF_CHECK || mode > MMC_HWPART_CONF_COMPLETE) 624 return -EINVAL; 625 626 if (IS_SD(mmc) || (mmc->version < MMC_VERSION_4_41)) { 627 printf("eMMC >= 4.4 required for enhanced user data area\n"); 628 return -EMEDIUMTYPE; 629 } 630 631 if (!(mmc->part_support & PART_SUPPORT)) { 632 printf("Card does not support partitioning\n"); 633 return -EMEDIUMTYPE; 634 } 635 636 if (!mmc->hc_wp_grp_size) { 637 printf("Card does not define HC WP group size\n"); 638 return -EMEDIUMTYPE; 639 } 640 641 /* check partition alignment and total enhanced size */ 642 if (conf->user.enh_size) { 643 if (conf->user.enh_size % mmc->hc_wp_grp_size || 644 conf->user.enh_start % mmc->hc_wp_grp_size) { 645 printf("User data enhanced area not HC WP group " 646 "size aligned\n"); 647 return -EINVAL; 648 } 649 part_attrs |= EXT_CSD_ENH_USR; 650 enh_size_mult = conf->user.enh_size / mmc->hc_wp_grp_size; 651 if (mmc->high_capacity) { 652 enh_start_addr = conf->user.enh_start; 653 } else { 654 enh_start_addr = (conf->user.enh_start << 9); 655 } 656 } else { 657 enh_size_mult = 0; 658 enh_start_addr = 0; 659 } 660 tot_enh_size_mult += enh_size_mult; 661 662 for (pidx = 0; pidx < 4; pidx++) { 663 if (conf->gp_part[pidx].size % mmc->hc_wp_grp_size) { 664 printf("GP%i partition not HC WP group size " 665 "aligned\n", pidx+1); 666 return -EINVAL; 667 } 668 gp_size_mult[pidx] = conf->gp_part[pidx].size / mmc->hc_wp_grp_size; 669 if (conf->gp_part[pidx].size && conf->gp_part[pidx].enhanced) { 670 part_attrs |= EXT_CSD_ENH_GP(pidx); 671 tot_enh_size_mult += gp_size_mult[pidx]; 672 } 673 } 674 675 if (part_attrs && ! (mmc->part_support & ENHNCD_SUPPORT)) { 676 printf("Card does not support enhanced attribute\n"); 677 return -EMEDIUMTYPE; 678 } 679 680 err = mmc_send_ext_csd(mmc, ext_csd); 681 if (err) 682 return err; 683 684 max_enh_size_mult = 685 (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+2] << 16) + 686 (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+1] << 8) + 687 ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT]; 688 if (tot_enh_size_mult > max_enh_size_mult) { 689 printf("Total enhanced size exceeds maximum (%u > %u)\n", 690 tot_enh_size_mult, max_enh_size_mult); 691 return -EMEDIUMTYPE; 692 } 693 694 /* The default value of EXT_CSD_WR_REL_SET is device 695 * dependent, the values can only be changed if the 696 * EXT_CSD_HS_CTRL_REL bit is set. The values can be 697 * changed only once and before partitioning is completed. */ 698 wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET]; 699 if (conf->user.wr_rel_change) { 700 if (conf->user.wr_rel_set) 701 wr_rel_set |= EXT_CSD_WR_DATA_REL_USR; 702 else 703 wr_rel_set &= ~EXT_CSD_WR_DATA_REL_USR; 704 } 705 for (pidx = 0; pidx < 4; pidx++) { 706 if (conf->gp_part[pidx].wr_rel_change) { 707 if (conf->gp_part[pidx].wr_rel_set) 708 wr_rel_set |= EXT_CSD_WR_DATA_REL_GP(pidx); 709 else 710 wr_rel_set &= ~EXT_CSD_WR_DATA_REL_GP(pidx); 711 } 712 } 713 714 if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET] && 715 !(ext_csd[EXT_CSD_WR_REL_PARAM] & EXT_CSD_HS_CTRL_REL)) { 716 puts("Card does not support host controlled partition write " 717 "reliability settings\n"); 718 return -EMEDIUMTYPE; 719 } 720 721 if (ext_csd[EXT_CSD_PARTITION_SETTING] & 722 EXT_CSD_PARTITION_SETTING_COMPLETED) { 723 printf("Card already partitioned\n"); 724 return -EPERM; 725 } 726 727 if (mode == MMC_HWPART_CONF_CHECK) 728 return 0; 729 730 /* Partitioning requires high-capacity size definitions */ 731 if (!(ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01)) { 732 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, 733 EXT_CSD_ERASE_GROUP_DEF, 1); 734 735 if (err) 736 return err; 737 738 ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1; 739 740 /* update erase group size to be high-capacity */ 741 mmc->erase_grp_size = 742 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024; 743 744 } 745 746 /* all OK, write the configuration */ 747 for (i = 0; i < 4; i++) { 748 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, 749 EXT_CSD_ENH_START_ADDR+i, 750 (enh_start_addr >> (i*8)) & 0xFF); 751 if (err) 752 return err; 753 } 754 for (i = 0; i < 3; i++) { 755 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, 756 EXT_CSD_ENH_SIZE_MULT+i, 757 (enh_size_mult >> (i*8)) & 0xFF); 758 if (err) 759 return err; 760 } 761 for (pidx = 0; pidx < 4; pidx++) { 762 for (i = 0; i < 3; i++) { 763 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, 764 EXT_CSD_GP_SIZE_MULT+pidx*3+i, 765 (gp_size_mult[pidx] >> (i*8)) & 0xFF); 766 if (err) 767 return err; 768 } 769 } 770 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, 771 EXT_CSD_PARTITIONS_ATTRIBUTE, part_attrs); 772 if (err) 773 return err; 774 775 if (mode == MMC_HWPART_CONF_SET) 776 return 0; 777 778 /* The WR_REL_SET is a write-once register but shall be 779 * written before setting PART_SETTING_COMPLETED. As it is 780 * write-once we can only write it when completing the 781 * partitioning. */ 782 if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET]) { 783 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, 784 EXT_CSD_WR_REL_SET, wr_rel_set); 785 if (err) 786 return err; 787 } 788 789 /* Setting PART_SETTING_COMPLETED confirms the partition 790 * configuration but it only becomes effective after power 791 * cycle, so we do not adjust the partition related settings 792 * in the mmc struct. */ 793 794 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, 795 EXT_CSD_PARTITION_SETTING, 796 EXT_CSD_PARTITION_SETTING_COMPLETED); 797 if (err) 798 return err; 799 800 return 0; 801 } 802 803 int mmc_getcd(struct mmc *mmc) 804 { 805 int cd; 806 807 cd = board_mmc_getcd(mmc); 808 809 if (cd < 0) { 810 if (mmc->cfg->ops->getcd) 811 cd = mmc->cfg->ops->getcd(mmc); 812 else 813 cd = 1; 814 } 815 816 return cd; 817 } 818 819 static int sd_switch(struct mmc *mmc, int mode, int group, u8 value, u8 *resp) 820 { 821 struct mmc_cmd cmd; 822 struct mmc_data data; 823 824 /* Switch the frequency */ 825 cmd.cmdidx = SD_CMD_SWITCH_FUNC; 826 cmd.resp_type = MMC_RSP_R1; 827 cmd.cmdarg = (mode << 31) | 0xffffff; 828 cmd.cmdarg &= ~(0xf << (group * 4)); 829 cmd.cmdarg |= value << (group * 4); 830 831 data.dest = (char *)resp; 832 data.blocksize = 64; 833 data.blocks = 1; 834 data.flags = MMC_DATA_READ; 835 836 return mmc_send_cmd(mmc, &cmd, &data); 837 } 838 839 840 static int sd_change_freq(struct mmc *mmc) 841 { 842 int err; 843 struct mmc_cmd cmd; 844 ALLOC_CACHE_ALIGN_BUFFER(uint, scr, 2); 845 ALLOC_CACHE_ALIGN_BUFFER(uint, switch_status, 16); 846 struct mmc_data data; 847 int timeout; 848 849 mmc->card_caps = 0; 850 851 if (mmc_host_is_spi(mmc)) 852 return 0; 853 854 /* Read the SCR to find out if this card supports higher speeds */ 855 cmd.cmdidx = MMC_CMD_APP_CMD; 856 cmd.resp_type = MMC_RSP_R1; 857 cmd.cmdarg = mmc->rca << 16; 858 859 err = mmc_send_cmd(mmc, &cmd, NULL); 860 861 if (err) 862 return err; 863 864 cmd.cmdidx = SD_CMD_APP_SEND_SCR; 865 cmd.resp_type = MMC_RSP_R1; 866 cmd.cmdarg = 0; 867 868 timeout = 3; 869 870 retry_scr: 871 data.dest = (char *)scr; 872 data.blocksize = 8; 873 data.blocks = 1; 874 data.flags = MMC_DATA_READ; 875 876 err = mmc_send_cmd(mmc, &cmd, &data); 877 878 if (err) { 879 if (timeout--) 880 goto retry_scr; 881 882 return err; 883 } 884 885 mmc->scr[0] = __be32_to_cpu(scr[0]); 886 mmc->scr[1] = __be32_to_cpu(scr[1]); 887 888 switch ((mmc->scr[0] >> 24) & 0xf) { 889 case 0: 890 mmc->version = SD_VERSION_1_0; 891 break; 892 case 1: 893 mmc->version = SD_VERSION_1_10; 894 break; 895 case 2: 896 mmc->version = SD_VERSION_2; 897 if ((mmc->scr[0] >> 15) & 0x1) 898 mmc->version = SD_VERSION_3; 899 break; 900 default: 901 mmc->version = SD_VERSION_1_0; 902 break; 903 } 904 905 if (mmc->scr[0] & SD_DATA_4BIT) 906 mmc->card_caps |= MMC_MODE_4BIT; 907 908 /* Version 1.0 doesn't support switching */ 909 if (mmc->version == SD_VERSION_1_0) 910 return 0; 911 912 timeout = 4; 913 while (timeout--) { 914 err = sd_switch(mmc, SD_SWITCH_CHECK, 0, 1, 915 (u8 *)switch_status); 916 917 if (err) 918 return err; 919 920 /* The high-speed function is busy. Try again */ 921 if (!(__be32_to_cpu(switch_status[7]) & SD_HIGHSPEED_BUSY)) 922 break; 923 } 924 925 /* If high-speed isn't supported, we return */ 926 if (!(__be32_to_cpu(switch_status[3]) & SD_HIGHSPEED_SUPPORTED)) 927 return 0; 928 929 /* 930 * If the host doesn't support SD_HIGHSPEED, do not switch card to 931 * HIGHSPEED mode even if the card support SD_HIGHSPPED. 932 * This can avoid furthur problem when the card runs in different 933 * mode between the host. 934 */ 935 if (!((mmc->cfg->host_caps & MMC_MODE_HS_52MHz) && 936 (mmc->cfg->host_caps & MMC_MODE_HS))) 937 return 0; 938 939 err = sd_switch(mmc, SD_SWITCH_SWITCH, 0, 1, (u8 *)switch_status); 940 941 if (err) 942 return err; 943 944 if ((__be32_to_cpu(switch_status[4]) & 0x0f000000) == 0x01000000) 945 mmc->card_caps |= MMC_MODE_HS; 946 947 return 0; 948 } 949 950 /* frequency bases */ 951 /* divided by 10 to be nice to platforms without floating point */ 952 static const int fbase[] = { 953 10000, 954 100000, 955 1000000, 956 10000000, 957 }; 958 959 /* Multiplier values for TRAN_SPEED. Multiplied by 10 to be nice 960 * to platforms without floating point. 961 */ 962 static const int multipliers[] = { 963 0, /* reserved */ 964 10, 965 12, 966 13, 967 15, 968 20, 969 25, 970 30, 971 35, 972 40, 973 45, 974 50, 975 55, 976 60, 977 70, 978 80, 979 }; 980 981 static void mmc_set_ios(struct mmc *mmc) 982 { 983 if (mmc->cfg->ops->set_ios) 984 mmc->cfg->ops->set_ios(mmc); 985 } 986 987 void mmc_set_clock(struct mmc *mmc, uint clock) 988 { 989 if (clock > mmc->cfg->f_max) 990 clock = mmc->cfg->f_max; 991 992 if (clock < mmc->cfg->f_min) 993 clock = mmc->cfg->f_min; 994 995 mmc->clock = clock; 996 997 mmc_set_ios(mmc); 998 } 999 1000 static void mmc_set_bus_width(struct mmc *mmc, uint width) 1001 { 1002 mmc->bus_width = width; 1003 1004 mmc_set_ios(mmc); 1005 } 1006 1007 static int mmc_startup(struct mmc *mmc) 1008 { 1009 int err, i; 1010 uint mult, freq; 1011 u64 cmult, csize, capacity; 1012 struct mmc_cmd cmd; 1013 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN); 1014 ALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, MMC_MAX_BLOCK_LEN); 1015 int timeout = 1000; 1016 bool has_parts = false; 1017 bool part_completed; 1018 1019 #ifdef CONFIG_MMC_SPI_CRC_ON 1020 if (mmc_host_is_spi(mmc)) { /* enable CRC check for spi */ 1021 cmd.cmdidx = MMC_CMD_SPI_CRC_ON_OFF; 1022 cmd.resp_type = MMC_RSP_R1; 1023 cmd.cmdarg = 1; 1024 err = mmc_send_cmd(mmc, &cmd, NULL); 1025 1026 if (err) 1027 return err; 1028 } 1029 #endif 1030 1031 /* Put the Card in Identify Mode */ 1032 cmd.cmdidx = mmc_host_is_spi(mmc) ? MMC_CMD_SEND_CID : 1033 MMC_CMD_ALL_SEND_CID; /* cmd not supported in spi */ 1034 cmd.resp_type = MMC_RSP_R2; 1035 cmd.cmdarg = 0; 1036 1037 err = mmc_send_cmd(mmc, &cmd, NULL); 1038 1039 if (err) 1040 return err; 1041 1042 memcpy(mmc->cid, cmd.response, 16); 1043 1044 /* 1045 * For MMC cards, set the Relative Address. 1046 * For SD cards, get the Relatvie Address. 1047 * This also puts the cards into Standby State 1048 */ 1049 if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */ 1050 cmd.cmdidx = SD_CMD_SEND_RELATIVE_ADDR; 1051 cmd.cmdarg = mmc->rca << 16; 1052 cmd.resp_type = MMC_RSP_R6; 1053 1054 err = mmc_send_cmd(mmc, &cmd, NULL); 1055 1056 if (err) 1057 return err; 1058 1059 if (IS_SD(mmc)) 1060 mmc->rca = (cmd.response[0] >> 16) & 0xffff; 1061 } 1062 1063 /* Get the Card-Specific Data */ 1064 cmd.cmdidx = MMC_CMD_SEND_CSD; 1065 cmd.resp_type = MMC_RSP_R2; 1066 cmd.cmdarg = mmc->rca << 16; 1067 1068 err = mmc_send_cmd(mmc, &cmd, NULL); 1069 1070 /* Waiting for the ready status */ 1071 mmc_send_status(mmc, timeout); 1072 1073 if (err) 1074 return err; 1075 1076 mmc->csd[0] = cmd.response[0]; 1077 mmc->csd[1] = cmd.response[1]; 1078 mmc->csd[2] = cmd.response[2]; 1079 mmc->csd[3] = cmd.response[3]; 1080 1081 if (mmc->version == MMC_VERSION_UNKNOWN) { 1082 int version = (cmd.response[0] >> 26) & 0xf; 1083 1084 switch (version) { 1085 case 0: 1086 mmc->version = MMC_VERSION_1_2; 1087 break; 1088 case 1: 1089 mmc->version = MMC_VERSION_1_4; 1090 break; 1091 case 2: 1092 mmc->version = MMC_VERSION_2_2; 1093 break; 1094 case 3: 1095 mmc->version = MMC_VERSION_3; 1096 break; 1097 case 4: 1098 mmc->version = MMC_VERSION_4; 1099 break; 1100 default: 1101 mmc->version = MMC_VERSION_1_2; 1102 break; 1103 } 1104 } 1105 1106 /* divide frequency by 10, since the mults are 10x bigger */ 1107 freq = fbase[(cmd.response[0] & 0x7)]; 1108 mult = multipliers[((cmd.response[0] >> 3) & 0xf)]; 1109 1110 mmc->tran_speed = freq * mult; 1111 1112 mmc->dsr_imp = ((cmd.response[1] >> 12) & 0x1); 1113 mmc->read_bl_len = 1 << ((cmd.response[1] >> 16) & 0xf); 1114 1115 if (IS_SD(mmc)) 1116 mmc->write_bl_len = mmc->read_bl_len; 1117 else 1118 mmc->write_bl_len = 1 << ((cmd.response[3] >> 22) & 0xf); 1119 1120 if (mmc->high_capacity) { 1121 csize = (mmc->csd[1] & 0x3f) << 16 1122 | (mmc->csd[2] & 0xffff0000) >> 16; 1123 cmult = 8; 1124 } else { 1125 csize = (mmc->csd[1] & 0x3ff) << 2 1126 | (mmc->csd[2] & 0xc0000000) >> 30; 1127 cmult = (mmc->csd[2] & 0x00038000) >> 15; 1128 } 1129 1130 mmc->capacity_user = (csize + 1) << (cmult + 2); 1131 mmc->capacity_user *= mmc->read_bl_len; 1132 mmc->capacity_boot = 0; 1133 mmc->capacity_rpmb = 0; 1134 for (i = 0; i < 4; i++) 1135 mmc->capacity_gp[i] = 0; 1136 1137 if (mmc->read_bl_len > MMC_MAX_BLOCK_LEN) 1138 mmc->read_bl_len = MMC_MAX_BLOCK_LEN; 1139 1140 if (mmc->write_bl_len > MMC_MAX_BLOCK_LEN) 1141 mmc->write_bl_len = MMC_MAX_BLOCK_LEN; 1142 1143 if ((mmc->dsr_imp) && (0xffffffff != mmc->dsr)) { 1144 cmd.cmdidx = MMC_CMD_SET_DSR; 1145 cmd.cmdarg = (mmc->dsr & 0xffff) << 16; 1146 cmd.resp_type = MMC_RSP_NONE; 1147 if (mmc_send_cmd(mmc, &cmd, NULL)) 1148 printf("MMC: SET_DSR failed\n"); 1149 } 1150 1151 /* Select the card, and put it into Transfer Mode */ 1152 if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */ 1153 cmd.cmdidx = MMC_CMD_SELECT_CARD; 1154 cmd.resp_type = MMC_RSP_R1; 1155 cmd.cmdarg = mmc->rca << 16; 1156 err = mmc_send_cmd(mmc, &cmd, NULL); 1157 1158 if (err) 1159 return err; 1160 } 1161 1162 /* 1163 * For SD, its erase group is always one sector 1164 */ 1165 mmc->erase_grp_size = 1; 1166 mmc->part_config = MMCPART_NOAVAILABLE; 1167 if (!IS_SD(mmc) && (mmc->version >= MMC_VERSION_4)) { 1168 /* check ext_csd version and capacity */ 1169 err = mmc_send_ext_csd(mmc, ext_csd); 1170 if (err) 1171 return err; 1172 if (ext_csd[EXT_CSD_REV] >= 2) { 1173 /* 1174 * According to the JEDEC Standard, the value of 1175 * ext_csd's capacity is valid if the value is more 1176 * than 2GB 1177 */ 1178 capacity = ext_csd[EXT_CSD_SEC_CNT] << 0 1179 | ext_csd[EXT_CSD_SEC_CNT + 1] << 8 1180 | ext_csd[EXT_CSD_SEC_CNT + 2] << 16 1181 | ext_csd[EXT_CSD_SEC_CNT + 3] << 24; 1182 capacity *= MMC_MAX_BLOCK_LEN; 1183 if ((capacity >> 20) > 2 * 1024) 1184 mmc->capacity_user = capacity; 1185 } 1186 1187 switch (ext_csd[EXT_CSD_REV]) { 1188 case 1: 1189 mmc->version = MMC_VERSION_4_1; 1190 break; 1191 case 2: 1192 mmc->version = MMC_VERSION_4_2; 1193 break; 1194 case 3: 1195 mmc->version = MMC_VERSION_4_3; 1196 break; 1197 case 5: 1198 mmc->version = MMC_VERSION_4_41; 1199 break; 1200 case 6: 1201 mmc->version = MMC_VERSION_4_5; 1202 break; 1203 case 7: 1204 mmc->version = MMC_VERSION_5_0; 1205 break; 1206 } 1207 1208 /* The partition data may be non-zero but it is only 1209 * effective if PARTITION_SETTING_COMPLETED is set in 1210 * EXT_CSD, so ignore any data if this bit is not set, 1211 * except for enabling the high-capacity group size 1212 * definition (see below). */ 1213 part_completed = !!(ext_csd[EXT_CSD_PARTITION_SETTING] & 1214 EXT_CSD_PARTITION_SETTING_COMPLETED); 1215 1216 /* store the partition info of emmc */ 1217 mmc->part_support = ext_csd[EXT_CSD_PARTITIONING_SUPPORT]; 1218 if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) || 1219 ext_csd[EXT_CSD_BOOT_MULT]) 1220 mmc->part_config = ext_csd[EXT_CSD_PART_CONF]; 1221 if (part_completed && 1222 (ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & ENHNCD_SUPPORT)) 1223 mmc->part_attr = ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE]; 1224 1225 mmc->capacity_boot = ext_csd[EXT_CSD_BOOT_MULT] << 17; 1226 1227 mmc->capacity_rpmb = ext_csd[EXT_CSD_RPMB_MULT] << 17; 1228 1229 for (i = 0; i < 4; i++) { 1230 int idx = EXT_CSD_GP_SIZE_MULT + i * 3; 1231 uint mult = (ext_csd[idx + 2] << 16) + 1232 (ext_csd[idx + 1] << 8) + ext_csd[idx]; 1233 if (mult) 1234 has_parts = true; 1235 if (!part_completed) 1236 continue; 1237 mmc->capacity_gp[i] = mult; 1238 mmc->capacity_gp[i] *= 1239 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]; 1240 mmc->capacity_gp[i] *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE]; 1241 mmc->capacity_gp[i] <<= 19; 1242 } 1243 1244 if (part_completed) { 1245 mmc->enh_user_size = 1246 (ext_csd[EXT_CSD_ENH_SIZE_MULT+2] << 16) + 1247 (ext_csd[EXT_CSD_ENH_SIZE_MULT+1] << 8) + 1248 ext_csd[EXT_CSD_ENH_SIZE_MULT]; 1249 mmc->enh_user_size *= ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]; 1250 mmc->enh_user_size *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE]; 1251 mmc->enh_user_size <<= 19; 1252 mmc->enh_user_start = 1253 (ext_csd[EXT_CSD_ENH_START_ADDR+3] << 24) + 1254 (ext_csd[EXT_CSD_ENH_START_ADDR+2] << 16) + 1255 (ext_csd[EXT_CSD_ENH_START_ADDR+1] << 8) + 1256 ext_csd[EXT_CSD_ENH_START_ADDR]; 1257 if (mmc->high_capacity) 1258 mmc->enh_user_start <<= 9; 1259 } 1260 1261 /* 1262 * Host needs to enable ERASE_GRP_DEF bit if device is 1263 * partitioned. This bit will be lost every time after a reset 1264 * or power off. This will affect erase size. 1265 */ 1266 if (part_completed) 1267 has_parts = true; 1268 if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) && 1269 (ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE] & PART_ENH_ATTRIB)) 1270 has_parts = true; 1271 if (has_parts) { 1272 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, 1273 EXT_CSD_ERASE_GROUP_DEF, 1); 1274 1275 if (err) 1276 return err; 1277 else 1278 ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1; 1279 } 1280 1281 if (ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01) { 1282 /* Read out group size from ext_csd */ 1283 mmc->erase_grp_size = 1284 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024; 1285 /* 1286 * if high capacity and partition setting completed 1287 * SEC_COUNT is valid even if it is smaller than 2 GiB 1288 * JEDEC Standard JESD84-B45, 6.2.4 1289 */ 1290 if (mmc->high_capacity && part_completed) { 1291 capacity = (ext_csd[EXT_CSD_SEC_CNT]) | 1292 (ext_csd[EXT_CSD_SEC_CNT + 1] << 8) | 1293 (ext_csd[EXT_CSD_SEC_CNT + 2] << 16) | 1294 (ext_csd[EXT_CSD_SEC_CNT + 3] << 24); 1295 capacity *= MMC_MAX_BLOCK_LEN; 1296 mmc->capacity_user = capacity; 1297 } 1298 } else { 1299 /* Calculate the group size from the csd value. */ 1300 int erase_gsz, erase_gmul; 1301 erase_gsz = (mmc->csd[2] & 0x00007c00) >> 10; 1302 erase_gmul = (mmc->csd[2] & 0x000003e0) >> 5; 1303 mmc->erase_grp_size = (erase_gsz + 1) 1304 * (erase_gmul + 1); 1305 } 1306 1307 mmc->hc_wp_grp_size = 1024 1308 * ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] 1309 * ext_csd[EXT_CSD_HC_WP_GRP_SIZE]; 1310 1311 mmc->wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET]; 1312 } 1313 1314 err = mmc_set_capacity(mmc, mmc->part_num); 1315 if (err) 1316 return err; 1317 1318 if (IS_SD(mmc)) 1319 err = sd_change_freq(mmc); 1320 else 1321 err = mmc_change_freq(mmc); 1322 1323 if (err) 1324 return err; 1325 1326 /* Restrict card's capabilities by what the host can do */ 1327 mmc->card_caps &= mmc->cfg->host_caps; 1328 1329 if (IS_SD(mmc)) { 1330 if (mmc->card_caps & MMC_MODE_4BIT) { 1331 cmd.cmdidx = MMC_CMD_APP_CMD; 1332 cmd.resp_type = MMC_RSP_R1; 1333 cmd.cmdarg = mmc->rca << 16; 1334 1335 err = mmc_send_cmd(mmc, &cmd, NULL); 1336 if (err) 1337 return err; 1338 1339 cmd.cmdidx = SD_CMD_APP_SET_BUS_WIDTH; 1340 cmd.resp_type = MMC_RSP_R1; 1341 cmd.cmdarg = 2; 1342 err = mmc_send_cmd(mmc, &cmd, NULL); 1343 if (err) 1344 return err; 1345 1346 mmc_set_bus_width(mmc, 4); 1347 } 1348 1349 if (mmc->card_caps & MMC_MODE_HS) 1350 mmc->tran_speed = 50000000; 1351 else 1352 mmc->tran_speed = 25000000; 1353 } else if (mmc->version >= MMC_VERSION_4) { 1354 /* Only version 4 of MMC supports wider bus widths */ 1355 int idx; 1356 1357 /* An array of possible bus widths in order of preference */ 1358 static unsigned ext_csd_bits[] = { 1359 EXT_CSD_DDR_BUS_WIDTH_8, 1360 EXT_CSD_DDR_BUS_WIDTH_4, 1361 EXT_CSD_BUS_WIDTH_8, 1362 EXT_CSD_BUS_WIDTH_4, 1363 EXT_CSD_BUS_WIDTH_1, 1364 }; 1365 1366 /* An array to map CSD bus widths to host cap bits */ 1367 static unsigned ext_to_hostcaps[] = { 1368 [EXT_CSD_DDR_BUS_WIDTH_4] = 1369 MMC_MODE_DDR_52MHz | MMC_MODE_4BIT, 1370 [EXT_CSD_DDR_BUS_WIDTH_8] = 1371 MMC_MODE_DDR_52MHz | MMC_MODE_8BIT, 1372 [EXT_CSD_BUS_WIDTH_4] = MMC_MODE_4BIT, 1373 [EXT_CSD_BUS_WIDTH_8] = MMC_MODE_8BIT, 1374 }; 1375 1376 /* An array to map chosen bus width to an integer */ 1377 static unsigned widths[] = { 1378 8, 4, 8, 4, 1, 1379 }; 1380 1381 for (idx=0; idx < ARRAY_SIZE(ext_csd_bits); idx++) { 1382 unsigned int extw = ext_csd_bits[idx]; 1383 unsigned int caps = ext_to_hostcaps[extw]; 1384 1385 /* 1386 * If the bus width is still not changed, 1387 * don't try to set the default again. 1388 * Otherwise, recover from switch attempts 1389 * by switching to 1-bit bus width. 1390 */ 1391 if (extw == EXT_CSD_BUS_WIDTH_1 && 1392 mmc->bus_width == 1) { 1393 err = 0; 1394 break; 1395 } 1396 1397 /* 1398 * Check to make sure the card and controller support 1399 * these capabilities 1400 */ 1401 if ((mmc->card_caps & caps) != caps) 1402 continue; 1403 1404 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, 1405 EXT_CSD_BUS_WIDTH, extw); 1406 1407 if (err) 1408 continue; 1409 1410 mmc->ddr_mode = (caps & MMC_MODE_DDR_52MHz) ? 1 : 0; 1411 mmc_set_bus_width(mmc, widths[idx]); 1412 1413 err = mmc_send_ext_csd(mmc, test_csd); 1414 1415 if (err) 1416 continue; 1417 1418 /* Only compare read only fields */ 1419 if (ext_csd[EXT_CSD_PARTITIONING_SUPPORT] 1420 == test_csd[EXT_CSD_PARTITIONING_SUPPORT] && 1421 ext_csd[EXT_CSD_HC_WP_GRP_SIZE] 1422 == test_csd[EXT_CSD_HC_WP_GRP_SIZE] && 1423 ext_csd[EXT_CSD_REV] 1424 == test_csd[EXT_CSD_REV] && 1425 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] 1426 == test_csd[EXT_CSD_HC_ERASE_GRP_SIZE] && 1427 memcmp(&ext_csd[EXT_CSD_SEC_CNT], 1428 &test_csd[EXT_CSD_SEC_CNT], 4) == 0) 1429 break; 1430 else 1431 err = SWITCH_ERR; 1432 } 1433 1434 if (err) 1435 return err; 1436 1437 if (mmc->card_caps & MMC_MODE_HS) { 1438 if (mmc->card_caps & MMC_MODE_HS_52MHz) 1439 mmc->tran_speed = 52000000; 1440 else 1441 mmc->tran_speed = 26000000; 1442 } 1443 } 1444 1445 mmc_set_clock(mmc, mmc->tran_speed); 1446 1447 /* Fix the block length for DDR mode */ 1448 if (mmc->ddr_mode) { 1449 mmc->read_bl_len = MMC_MAX_BLOCK_LEN; 1450 mmc->write_bl_len = MMC_MAX_BLOCK_LEN; 1451 } 1452 1453 /* fill in device description */ 1454 mmc->block_dev.lun = 0; 1455 mmc->block_dev.type = 0; 1456 mmc->block_dev.blksz = mmc->read_bl_len; 1457 mmc->block_dev.log2blksz = LOG2(mmc->block_dev.blksz); 1458 mmc->block_dev.lba = lldiv(mmc->capacity, mmc->read_bl_len); 1459 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) 1460 sprintf(mmc->block_dev.vendor, "Man %06x Snr %04x%04x", 1461 mmc->cid[0] >> 24, (mmc->cid[2] & 0xffff), 1462 (mmc->cid[3] >> 16) & 0xffff); 1463 sprintf(mmc->block_dev.product, "%c%c%c%c%c%c", mmc->cid[0] & 0xff, 1464 (mmc->cid[1] >> 24), (mmc->cid[1] >> 16) & 0xff, 1465 (mmc->cid[1] >> 8) & 0xff, mmc->cid[1] & 0xff, 1466 (mmc->cid[2] >> 24) & 0xff); 1467 sprintf(mmc->block_dev.revision, "%d.%d", (mmc->cid[2] >> 20) & 0xf, 1468 (mmc->cid[2] >> 16) & 0xf); 1469 #else 1470 mmc->block_dev.vendor[0] = 0; 1471 mmc->block_dev.product[0] = 0; 1472 mmc->block_dev.revision[0] = 0; 1473 #endif 1474 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBDISK_SUPPORT) 1475 init_part(&mmc->block_dev); 1476 #endif 1477 1478 return 0; 1479 } 1480 1481 static int mmc_send_if_cond(struct mmc *mmc) 1482 { 1483 struct mmc_cmd cmd; 1484 int err; 1485 1486 cmd.cmdidx = SD_CMD_SEND_IF_COND; 1487 /* We set the bit if the host supports voltages between 2.7 and 3.6 V */ 1488 cmd.cmdarg = ((mmc->cfg->voltages & 0xff8000) != 0) << 8 | 0xaa; 1489 cmd.resp_type = MMC_RSP_R7; 1490 1491 err = mmc_send_cmd(mmc, &cmd, NULL); 1492 1493 if (err) 1494 return err; 1495 1496 if ((cmd.response[0] & 0xff) != 0xaa) 1497 return UNUSABLE_ERR; 1498 else 1499 mmc->version = SD_VERSION_2; 1500 1501 return 0; 1502 } 1503 1504 /* not used any more */ 1505 int __deprecated mmc_register(struct mmc *mmc) 1506 { 1507 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) 1508 printf("%s is deprecated! use mmc_create() instead.\n", __func__); 1509 #endif 1510 return -1; 1511 } 1512 1513 struct mmc *mmc_create(const struct mmc_config *cfg, void *priv) 1514 { 1515 struct mmc *mmc; 1516 1517 /* quick validation */ 1518 if (cfg == NULL || cfg->ops == NULL || cfg->ops->send_cmd == NULL || 1519 cfg->f_min == 0 || cfg->f_max == 0 || cfg->b_max == 0) 1520 return NULL; 1521 1522 mmc = calloc(1, sizeof(*mmc)); 1523 if (mmc == NULL) 1524 return NULL; 1525 1526 mmc->cfg = cfg; 1527 mmc->priv = priv; 1528 1529 /* the following chunk was mmc_register() */ 1530 1531 /* Setup dsr related values */ 1532 mmc->dsr_imp = 0; 1533 mmc->dsr = 0xffffffff; 1534 /* Setup the universal parts of the block interface just once */ 1535 mmc->block_dev.if_type = IF_TYPE_MMC; 1536 mmc->block_dev.dev = cur_dev_num++; 1537 mmc->block_dev.removable = 1; 1538 mmc->block_dev.block_read = mmc_bread; 1539 mmc->block_dev.block_write = mmc_bwrite; 1540 mmc->block_dev.block_erase = mmc_berase; 1541 1542 /* setup initial part type */ 1543 mmc->block_dev.part_type = mmc->cfg->part_type; 1544 1545 INIT_LIST_HEAD(&mmc->link); 1546 1547 list_add_tail(&mmc->link, &mmc_devices); 1548 1549 return mmc; 1550 } 1551 1552 void mmc_destroy(struct mmc *mmc) 1553 { 1554 /* only freeing memory for now */ 1555 free(mmc); 1556 } 1557 1558 #ifdef CONFIG_PARTITIONS 1559 block_dev_desc_t *mmc_get_dev(int dev) 1560 { 1561 struct mmc *mmc = find_mmc_device(dev); 1562 if (!mmc || mmc_init(mmc)) 1563 return NULL; 1564 1565 return &mmc->block_dev; 1566 } 1567 #endif 1568 1569 /* board-specific MMC power initializations. */ 1570 __weak void board_mmc_power_init(void) 1571 { 1572 } 1573 1574 int mmc_start_init(struct mmc *mmc) 1575 { 1576 int err; 1577 1578 /* we pretend there's no card when init is NULL */ 1579 if (mmc_getcd(mmc) == 0 || mmc->cfg->ops->init == NULL) { 1580 mmc->has_init = 0; 1581 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) 1582 printf("MMC: no card present\n"); 1583 #endif 1584 return NO_CARD_ERR; 1585 } 1586 1587 if (mmc->has_init) 1588 return 0; 1589 1590 board_mmc_power_init(); 1591 1592 /* made sure it's not NULL earlier */ 1593 err = mmc->cfg->ops->init(mmc); 1594 1595 if (err) 1596 return err; 1597 1598 mmc->ddr_mode = 0; 1599 mmc_set_bus_width(mmc, 1); 1600 mmc_set_clock(mmc, 1); 1601 1602 /* Reset the Card */ 1603 err = mmc_go_idle(mmc); 1604 1605 if (err) 1606 return err; 1607 1608 /* The internal partition reset to user partition(0) at every CMD0*/ 1609 mmc->part_num = 0; 1610 1611 /* Test for SD version 2 */ 1612 err = mmc_send_if_cond(mmc); 1613 1614 /* Now try to get the SD card's operating condition */ 1615 err = sd_send_op_cond(mmc); 1616 1617 /* If the command timed out, we check for an MMC card */ 1618 if (err == TIMEOUT) { 1619 err = mmc_send_op_cond(mmc); 1620 1621 if (err && err != IN_PROGRESS) { 1622 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) 1623 printf("Card did not respond to voltage select!\n"); 1624 #endif 1625 return UNUSABLE_ERR; 1626 } 1627 } 1628 1629 if (err == IN_PROGRESS) 1630 mmc->init_in_progress = 1; 1631 1632 return err; 1633 } 1634 1635 static int mmc_complete_init(struct mmc *mmc) 1636 { 1637 int err = 0; 1638 1639 if (mmc->op_cond_pending) 1640 err = mmc_complete_op_cond(mmc); 1641 1642 if (!err) 1643 err = mmc_startup(mmc); 1644 if (err) 1645 mmc->has_init = 0; 1646 else 1647 mmc->has_init = 1; 1648 mmc->init_in_progress = 0; 1649 return err; 1650 } 1651 1652 int mmc_init(struct mmc *mmc) 1653 { 1654 int err = IN_PROGRESS; 1655 unsigned start; 1656 1657 if (mmc->has_init) 1658 return 0; 1659 1660 start = get_timer(0); 1661 1662 if (!mmc->init_in_progress) 1663 err = mmc_start_init(mmc); 1664 1665 if (!err || err == IN_PROGRESS) 1666 err = mmc_complete_init(mmc); 1667 debug("%s: %d, time %lu\n", __func__, err, get_timer(start)); 1668 return err; 1669 } 1670 1671 int mmc_set_dsr(struct mmc *mmc, u16 val) 1672 { 1673 mmc->dsr = val; 1674 return 0; 1675 } 1676 1677 /* CPU-specific MMC initializations */ 1678 __weak int cpu_mmc_init(bd_t *bis) 1679 { 1680 return -1; 1681 } 1682 1683 /* board-specific MMC initializations. */ 1684 __weak int board_mmc_init(bd_t *bis) 1685 { 1686 return -1; 1687 } 1688 1689 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) 1690 1691 void print_mmc_devices(char separator) 1692 { 1693 struct mmc *m; 1694 struct list_head *entry; 1695 char *mmc_type; 1696 1697 list_for_each(entry, &mmc_devices) { 1698 m = list_entry(entry, struct mmc, link); 1699 1700 if (m->has_init) 1701 mmc_type = IS_SD(m) ? "SD" : "eMMC"; 1702 else 1703 mmc_type = NULL; 1704 1705 printf("%s: %d", m->cfg->name, m->block_dev.dev); 1706 if (mmc_type) 1707 printf(" (%s)", mmc_type); 1708 1709 if (entry->next != &mmc_devices) { 1710 printf("%c", separator); 1711 if (separator != '\n') 1712 puts (" "); 1713 } 1714 } 1715 1716 printf("\n"); 1717 } 1718 1719 #else 1720 void print_mmc_devices(char separator) { } 1721 #endif 1722 1723 int get_mmc_num(void) 1724 { 1725 return cur_dev_num; 1726 } 1727 1728 void mmc_set_preinit(struct mmc *mmc, int preinit) 1729 { 1730 mmc->preinit = preinit; 1731 } 1732 1733 static void do_preinit(void) 1734 { 1735 struct mmc *m; 1736 struct list_head *entry; 1737 1738 list_for_each(entry, &mmc_devices) { 1739 m = list_entry(entry, struct mmc, link); 1740 1741 if (m->preinit) 1742 mmc_start_init(m); 1743 } 1744 } 1745 1746 1747 int mmc_initialize(bd_t *bis) 1748 { 1749 INIT_LIST_HEAD (&mmc_devices); 1750 cur_dev_num = 0; 1751 1752 if (board_mmc_init(bis) < 0) 1753 cpu_mmc_init(bis); 1754 1755 #ifndef CONFIG_SPL_BUILD 1756 print_mmc_devices(','); 1757 #endif 1758 1759 do_preinit(); 1760 return 0; 1761 } 1762 1763 #ifdef CONFIG_SUPPORT_EMMC_BOOT 1764 /* 1765 * This function changes the size of boot partition and the size of rpmb 1766 * partition present on EMMC devices. 1767 * 1768 * Input Parameters: 1769 * struct *mmc: pointer for the mmc device strcuture 1770 * bootsize: size of boot partition 1771 * rpmbsize: size of rpmb partition 1772 * 1773 * Returns 0 on success. 1774 */ 1775 1776 int mmc_boot_partition_size_change(struct mmc *mmc, unsigned long bootsize, 1777 unsigned long rpmbsize) 1778 { 1779 int err; 1780 struct mmc_cmd cmd; 1781 1782 /* Only use this command for raw EMMC moviNAND. Enter backdoor mode */ 1783 cmd.cmdidx = MMC_CMD_RES_MAN; 1784 cmd.resp_type = MMC_RSP_R1b; 1785 cmd.cmdarg = MMC_CMD62_ARG1; 1786 1787 err = mmc_send_cmd(mmc, &cmd, NULL); 1788 if (err) { 1789 debug("mmc_boot_partition_size_change: Error1 = %d\n", err); 1790 return err; 1791 } 1792 1793 /* Boot partition changing mode */ 1794 cmd.cmdidx = MMC_CMD_RES_MAN; 1795 cmd.resp_type = MMC_RSP_R1b; 1796 cmd.cmdarg = MMC_CMD62_ARG2; 1797 1798 err = mmc_send_cmd(mmc, &cmd, NULL); 1799 if (err) { 1800 debug("mmc_boot_partition_size_change: Error2 = %d\n", err); 1801 return err; 1802 } 1803 /* boot partition size is multiple of 128KB */ 1804 bootsize = (bootsize * 1024) / 128; 1805 1806 /* Arg: boot partition size */ 1807 cmd.cmdidx = MMC_CMD_RES_MAN; 1808 cmd.resp_type = MMC_RSP_R1b; 1809 cmd.cmdarg = bootsize; 1810 1811 err = mmc_send_cmd(mmc, &cmd, NULL); 1812 if (err) { 1813 debug("mmc_boot_partition_size_change: Error3 = %d\n", err); 1814 return err; 1815 } 1816 /* RPMB partition size is multiple of 128KB */ 1817 rpmbsize = (rpmbsize * 1024) / 128; 1818 /* Arg: RPMB partition size */ 1819 cmd.cmdidx = MMC_CMD_RES_MAN; 1820 cmd.resp_type = MMC_RSP_R1b; 1821 cmd.cmdarg = rpmbsize; 1822 1823 err = mmc_send_cmd(mmc, &cmd, NULL); 1824 if (err) { 1825 debug("mmc_boot_partition_size_change: Error4 = %d\n", err); 1826 return err; 1827 } 1828 return 0; 1829 } 1830 1831 /* 1832 * Modify EXT_CSD[177] which is BOOT_BUS_WIDTH 1833 * based on the passed in values for BOOT_BUS_WIDTH, RESET_BOOT_BUS_WIDTH 1834 * and BOOT_MODE. 1835 * 1836 * Returns 0 on success. 1837 */ 1838 int mmc_set_boot_bus_width(struct mmc *mmc, u8 width, u8 reset, u8 mode) 1839 { 1840 int err; 1841 1842 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BOOT_BUS_WIDTH, 1843 EXT_CSD_BOOT_BUS_WIDTH_MODE(mode) | 1844 EXT_CSD_BOOT_BUS_WIDTH_RESET(reset) | 1845 EXT_CSD_BOOT_BUS_WIDTH_WIDTH(width)); 1846 1847 if (err) 1848 return err; 1849 return 0; 1850 } 1851 1852 /* 1853 * Modify EXT_CSD[179] which is PARTITION_CONFIG (formerly BOOT_CONFIG) 1854 * based on the passed in values for BOOT_ACK, BOOT_PARTITION_ENABLE and 1855 * PARTITION_ACCESS. 1856 * 1857 * Returns 0 on success. 1858 */ 1859 int mmc_set_part_conf(struct mmc *mmc, u8 ack, u8 part_num, u8 access) 1860 { 1861 int err; 1862 1863 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_PART_CONF, 1864 EXT_CSD_BOOT_ACK(ack) | 1865 EXT_CSD_BOOT_PART_NUM(part_num) | 1866 EXT_CSD_PARTITION_ACCESS(access)); 1867 1868 if (err) 1869 return err; 1870 return 0; 1871 } 1872 1873 /* 1874 * Modify EXT_CSD[162] which is RST_n_FUNCTION based on the given value 1875 * for enable. Note that this is a write-once field for non-zero values. 1876 * 1877 * Returns 0 on success. 1878 */ 1879 int mmc_set_rst_n_function(struct mmc *mmc, u8 enable) 1880 { 1881 return mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_RST_N_FUNCTION, 1882 enable); 1883 } 1884 #endif 1885