1 /* 2 * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc 3 * Andy Fleming 4 * 5 * Based vaguely on the pxa mmc code: 6 * (C) Copyright 2003 7 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net 8 * 9 * SPDX-License-Identifier: GPL-2.0+ 10 */ 11 12 #include <config.h> 13 #include <common.h> 14 #include <command.h> 15 #include <hwconfig.h> 16 #include <mmc.h> 17 #include <part.h> 18 #include <malloc.h> 19 #include <mmc.h> 20 #include <fsl_esdhc.h> 21 #include <fdt_support.h> 22 #include <asm/io.h> 23 24 DECLARE_GLOBAL_DATA_PTR; 25 26 struct fsl_esdhc { 27 uint dsaddr; /* SDMA system address register */ 28 uint blkattr; /* Block attributes register */ 29 uint cmdarg; /* Command argument register */ 30 uint xfertyp; /* Transfer type register */ 31 uint cmdrsp0; /* Command response 0 register */ 32 uint cmdrsp1; /* Command response 1 register */ 33 uint cmdrsp2; /* Command response 2 register */ 34 uint cmdrsp3; /* Command response 3 register */ 35 uint datport; /* Buffer data port register */ 36 uint prsstat; /* Present state register */ 37 uint proctl; /* Protocol control register */ 38 uint sysctl; /* System Control Register */ 39 uint irqstat; /* Interrupt status register */ 40 uint irqstaten; /* Interrupt status enable register */ 41 uint irqsigen; /* Interrupt signal enable register */ 42 uint autoc12err; /* Auto CMD error status register */ 43 uint hostcapblt; /* Host controller capabilities register */ 44 uint wml; /* Watermark level register */ 45 uint mixctrl; /* For USDHC */ 46 char reserved1[4]; /* reserved */ 47 uint fevt; /* Force event register */ 48 uint admaes; /* ADMA error status register */ 49 uint adsaddr; /* ADMA system address register */ 50 char reserved2[160]; /* reserved */ 51 uint hostver; /* Host controller version register */ 52 char reserved3[4]; /* reserved */ 53 uint dmaerraddr; /* DMA error address register */ 54 char reserved4[4]; /* reserved */ 55 uint dmaerrattr; /* DMA error attribute register */ 56 char reserved5[4]; /* reserved */ 57 uint hostcapblt2; /* Host controller capabilities register 2 */ 58 char reserved6[8]; /* reserved */ 59 uint tcr; /* Tuning control register */ 60 char reserved7[28]; /* reserved */ 61 uint sddirctl; /* SD direction control register */ 62 char reserved8[712]; /* reserved */ 63 uint scr; /* eSDHC control register */ 64 }; 65 66 /* Return the XFERTYP flags for a given command and data packet */ 67 static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data) 68 { 69 uint xfertyp = 0; 70 71 if (data) { 72 xfertyp |= XFERTYP_DPSEL; 73 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO 74 xfertyp |= XFERTYP_DMAEN; 75 #endif 76 if (data->blocks > 1) { 77 xfertyp |= XFERTYP_MSBSEL; 78 xfertyp |= XFERTYP_BCEN; 79 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111 80 xfertyp |= XFERTYP_AC12EN; 81 #endif 82 } 83 84 if (data->flags & MMC_DATA_READ) 85 xfertyp |= XFERTYP_DTDSEL; 86 } 87 88 if (cmd->resp_type & MMC_RSP_CRC) 89 xfertyp |= XFERTYP_CCCEN; 90 if (cmd->resp_type & MMC_RSP_OPCODE) 91 xfertyp |= XFERTYP_CICEN; 92 if (cmd->resp_type & MMC_RSP_136) 93 xfertyp |= XFERTYP_RSPTYP_136; 94 else if (cmd->resp_type & MMC_RSP_BUSY) 95 xfertyp |= XFERTYP_RSPTYP_48_BUSY; 96 else if (cmd->resp_type & MMC_RSP_PRESENT) 97 xfertyp |= XFERTYP_RSPTYP_48; 98 99 #if defined(CONFIG_MX53) || defined(CONFIG_T4240QDS) 100 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) 101 xfertyp |= XFERTYP_CMDTYP_ABORT; 102 #endif 103 return XFERTYP_CMD(cmd->cmdidx) | xfertyp; 104 } 105 106 #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO 107 /* 108 * PIO Read/Write Mode reduce the performace as DMA is not used in this mode. 109 */ 110 static void 111 esdhc_pio_read_write(struct mmc *mmc, struct mmc_data *data) 112 { 113 struct fsl_esdhc_cfg *cfg = mmc->priv; 114 struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; 115 uint blocks; 116 char *buffer; 117 uint databuf; 118 uint size; 119 uint irqstat; 120 uint timeout; 121 122 if (data->flags & MMC_DATA_READ) { 123 blocks = data->blocks; 124 buffer = data->dest; 125 while (blocks) { 126 timeout = PIO_TIMEOUT; 127 size = data->blocksize; 128 irqstat = esdhc_read32(®s->irqstat); 129 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BREN) 130 && --timeout); 131 if (timeout <= 0) { 132 printf("\nData Read Failed in PIO Mode."); 133 return; 134 } 135 while (size && (!(irqstat & IRQSTAT_TC))) { 136 udelay(100); /* Wait before last byte transfer complete */ 137 irqstat = esdhc_read32(®s->irqstat); 138 databuf = in_le32(®s->datport); 139 *((uint *)buffer) = databuf; 140 buffer += 4; 141 size -= 4; 142 } 143 blocks--; 144 } 145 } else { 146 blocks = data->blocks; 147 buffer = (char *)data->src; 148 while (blocks) { 149 timeout = PIO_TIMEOUT; 150 size = data->blocksize; 151 irqstat = esdhc_read32(®s->irqstat); 152 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BWEN) 153 && --timeout); 154 if (timeout <= 0) { 155 printf("\nData Write Failed in PIO Mode."); 156 return; 157 } 158 while (size && (!(irqstat & IRQSTAT_TC))) { 159 udelay(100); /* Wait before last byte transfer complete */ 160 databuf = *((uint *)buffer); 161 buffer += 4; 162 size -= 4; 163 irqstat = esdhc_read32(®s->irqstat); 164 out_le32(®s->datport, databuf); 165 } 166 blocks--; 167 } 168 } 169 } 170 #endif 171 172 static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data) 173 { 174 int timeout; 175 struct fsl_esdhc_cfg *cfg = mmc->priv; 176 struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; 177 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO 178 uint wml_value; 179 180 wml_value = data->blocksize/4; 181 182 if (data->flags & MMC_DATA_READ) { 183 if (wml_value > WML_RD_WML_MAX) 184 wml_value = WML_RD_WML_MAX_VAL; 185 186 esdhc_clrsetbits32(®s->wml, WML_RD_WML_MASK, wml_value); 187 esdhc_write32(®s->dsaddr, (u32)data->dest); 188 } else { 189 flush_dcache_range((ulong)data->src, 190 (ulong)data->src+data->blocks 191 *data->blocksize); 192 193 if (wml_value > WML_WR_WML_MAX) 194 wml_value = WML_WR_WML_MAX_VAL; 195 if ((esdhc_read32(®s->prsstat) & PRSSTAT_WPSPL) == 0) { 196 printf("\nThe SD card is locked. Can not write to a locked card.\n\n"); 197 return TIMEOUT; 198 } 199 200 esdhc_clrsetbits32(®s->wml, WML_WR_WML_MASK, 201 wml_value << 16); 202 esdhc_write32(®s->dsaddr, (u32)data->src); 203 } 204 #else /* CONFIG_SYS_FSL_ESDHC_USE_PIO */ 205 if (!(data->flags & MMC_DATA_READ)) { 206 if ((esdhc_read32(®s->prsstat) & PRSSTAT_WPSPL) == 0) { 207 printf("\nThe SD card is locked. " 208 "Can not write to a locked card.\n\n"); 209 return TIMEOUT; 210 } 211 esdhc_write32(®s->dsaddr, (u32)data->src); 212 } else 213 esdhc_write32(®s->dsaddr, (u32)data->dest); 214 #endif /* CONFIG_SYS_FSL_ESDHC_USE_PIO */ 215 216 esdhc_write32(®s->blkattr, data->blocks << 16 | data->blocksize); 217 218 /* Calculate the timeout period for data transactions */ 219 /* 220 * 1)Timeout period = (2^(timeout+13)) SD Clock cycles 221 * 2)Timeout period should be minimum 0.250sec as per SD Card spec 222 * So, Number of SD Clock cycles for 0.25sec should be minimum 223 * (SD Clock/sec * 0.25 sec) SD Clock cycles 224 * = (mmc->clock * 1/4) SD Clock cycles 225 * As 1) >= 2) 226 * => (2^(timeout+13)) >= mmc->clock * 1/4 227 * Taking log2 both the sides 228 * => timeout + 13 >= log2(mmc->clock/4) 229 * Rounding up to next power of 2 230 * => timeout + 13 = log2(mmc->clock/4) + 1 231 * => timeout + 13 = fls(mmc->clock/4) 232 */ 233 timeout = fls(mmc->clock/4); 234 timeout -= 13; 235 236 if (timeout > 14) 237 timeout = 14; 238 239 if (timeout < 0) 240 timeout = 0; 241 242 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC_A001 243 if ((timeout == 4) || (timeout == 8) || (timeout == 12)) 244 timeout++; 245 #endif 246 247 esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16); 248 249 return 0; 250 } 251 252 static void check_and_invalidate_dcache_range 253 (struct mmc_cmd *cmd, 254 struct mmc_data *data) { 255 unsigned start = (unsigned)data->dest ; 256 unsigned size = roundup(ARCH_DMA_MINALIGN, 257 data->blocks*data->blocksize); 258 unsigned end = start+size ; 259 invalidate_dcache_range(start, end); 260 } 261 /* 262 * Sends a command out on the bus. Takes the mmc pointer, 263 * a command pointer, and an optional data pointer. 264 */ 265 static int 266 esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) 267 { 268 int err = 0; 269 uint xfertyp; 270 uint irqstat; 271 struct fsl_esdhc_cfg *cfg = mmc->priv; 272 volatile struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; 273 274 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111 275 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) 276 return 0; 277 #endif 278 279 esdhc_write32(®s->irqstat, -1); 280 281 sync(); 282 283 /* Wait for the bus to be idle */ 284 while ((esdhc_read32(®s->prsstat) & PRSSTAT_CICHB) || 285 (esdhc_read32(®s->prsstat) & PRSSTAT_CIDHB)) 286 ; 287 288 while (esdhc_read32(®s->prsstat) & PRSSTAT_DLA) 289 ; 290 291 /* Wait at least 8 SD clock cycles before the next command */ 292 /* 293 * Note: This is way more than 8 cycles, but 1ms seems to 294 * resolve timing issues with some cards 295 */ 296 udelay(1000); 297 298 /* Set up for a data transfer if we have one */ 299 if (data) { 300 err = esdhc_setup_data(mmc, data); 301 if(err) 302 return err; 303 } 304 305 /* Figure out the transfer arguments */ 306 xfertyp = esdhc_xfertyp(cmd, data); 307 308 /* Mask all irqs */ 309 esdhc_write32(®s->irqsigen, 0); 310 311 /* Send the command */ 312 esdhc_write32(®s->cmdarg, cmd->cmdarg); 313 #if defined(CONFIG_FSL_USDHC) 314 esdhc_write32(®s->mixctrl, 315 (esdhc_read32(®s->mixctrl) & 0xFFFFFF80) | (xfertyp & 0x7F)); 316 esdhc_write32(®s->xfertyp, xfertyp & 0xFFFF0000); 317 #else 318 esdhc_write32(®s->xfertyp, xfertyp); 319 #endif 320 321 /* Wait for the command to complete */ 322 while (!(esdhc_read32(®s->irqstat) & (IRQSTAT_CC | IRQSTAT_CTOE))) 323 ; 324 325 irqstat = esdhc_read32(®s->irqstat); 326 327 if (irqstat & CMD_ERR) { 328 err = COMM_ERR; 329 goto out; 330 } 331 332 if (irqstat & IRQSTAT_CTOE) { 333 err = TIMEOUT; 334 goto out; 335 } 336 337 /* Workaround for ESDHC errata ENGcm03648 */ 338 if (!data && (cmd->resp_type & MMC_RSP_BUSY)) { 339 int timeout = 2500; 340 341 /* Poll on DATA0 line for cmd with busy signal for 250 ms */ 342 while (timeout > 0 && !(esdhc_read32(®s->prsstat) & 343 PRSSTAT_DAT0)) { 344 udelay(100); 345 timeout--; 346 } 347 348 if (timeout <= 0) { 349 printf("Timeout waiting for DAT0 to go high!\n"); 350 err = TIMEOUT; 351 goto out; 352 } 353 } 354 355 /* Copy the response to the response buffer */ 356 if (cmd->resp_type & MMC_RSP_136) { 357 u32 cmdrsp3, cmdrsp2, cmdrsp1, cmdrsp0; 358 359 cmdrsp3 = esdhc_read32(®s->cmdrsp3); 360 cmdrsp2 = esdhc_read32(®s->cmdrsp2); 361 cmdrsp1 = esdhc_read32(®s->cmdrsp1); 362 cmdrsp0 = esdhc_read32(®s->cmdrsp0); 363 cmd->response[0] = (cmdrsp3 << 8) | (cmdrsp2 >> 24); 364 cmd->response[1] = (cmdrsp2 << 8) | (cmdrsp1 >> 24); 365 cmd->response[2] = (cmdrsp1 << 8) | (cmdrsp0 >> 24); 366 cmd->response[3] = (cmdrsp0 << 8); 367 } else 368 cmd->response[0] = esdhc_read32(®s->cmdrsp0); 369 370 /* Wait until all of the blocks are transferred */ 371 if (data) { 372 #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO 373 esdhc_pio_read_write(mmc, data); 374 #else 375 do { 376 irqstat = esdhc_read32(®s->irqstat); 377 378 if (irqstat & IRQSTAT_DTOE) { 379 err = TIMEOUT; 380 goto out; 381 } 382 383 if (irqstat & DATA_ERR) { 384 err = COMM_ERR; 385 goto out; 386 } 387 } while ((irqstat & DATA_COMPLETE) != DATA_COMPLETE); 388 #endif 389 if (data->flags & MMC_DATA_READ) 390 check_and_invalidate_dcache_range(cmd, data); 391 } 392 393 out: 394 /* Reset CMD and DATA portions on error */ 395 if (err) { 396 esdhc_write32(®s->sysctl, esdhc_read32(®s->sysctl) | 397 SYSCTL_RSTC); 398 while (esdhc_read32(®s->sysctl) & SYSCTL_RSTC) 399 ; 400 401 if (data) { 402 esdhc_write32(®s->sysctl, 403 esdhc_read32(®s->sysctl) | 404 SYSCTL_RSTD); 405 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTD)) 406 ; 407 } 408 } 409 410 esdhc_write32(®s->irqstat, -1); 411 412 return err; 413 } 414 415 static void set_sysctl(struct mmc *mmc, uint clock) 416 { 417 int div, pre_div; 418 struct fsl_esdhc_cfg *cfg = mmc->priv; 419 volatile struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; 420 int sdhc_clk = cfg->sdhc_clk; 421 uint clk; 422 423 if (clock < mmc->cfg->f_min) 424 clock = mmc->cfg->f_min; 425 426 if (sdhc_clk / 16 > clock) { 427 for (pre_div = 2; pre_div < 256; pre_div *= 2) 428 if ((sdhc_clk / pre_div) <= (clock * 16)) 429 break; 430 } else 431 pre_div = 2; 432 433 for (div = 1; div <= 16; div++) 434 if ((sdhc_clk / (div * pre_div)) <= clock) 435 break; 436 437 pre_div >>= 1; 438 div -= 1; 439 440 clk = (pre_div << 8) | (div << 4); 441 442 esdhc_clrbits32(®s->sysctl, SYSCTL_CKEN); 443 444 esdhc_clrsetbits32(®s->sysctl, SYSCTL_CLOCK_MASK, clk); 445 446 udelay(10000); 447 448 clk = SYSCTL_PEREN | SYSCTL_CKEN; 449 450 esdhc_setbits32(®s->sysctl, clk); 451 } 452 453 static void esdhc_set_ios(struct mmc *mmc) 454 { 455 struct fsl_esdhc_cfg *cfg = mmc->priv; 456 struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; 457 458 /* Set the clock speed */ 459 set_sysctl(mmc, mmc->clock); 460 461 /* Set the bus width */ 462 esdhc_clrbits32(®s->proctl, PROCTL_DTW_4 | PROCTL_DTW_8); 463 464 if (mmc->bus_width == 4) 465 esdhc_setbits32(®s->proctl, PROCTL_DTW_4); 466 else if (mmc->bus_width == 8) 467 esdhc_setbits32(®s->proctl, PROCTL_DTW_8); 468 469 } 470 471 static int esdhc_init(struct mmc *mmc) 472 { 473 struct fsl_esdhc_cfg *cfg = mmc->priv; 474 struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; 475 int timeout = 1000; 476 477 /* Reset the entire host controller */ 478 esdhc_setbits32(®s->sysctl, SYSCTL_RSTA); 479 480 /* Wait until the controller is available */ 481 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA) && --timeout) 482 udelay(1000); 483 484 #ifndef ARCH_MXC 485 /* Enable cache snooping */ 486 esdhc_write32(®s->scr, 0x00000040); 487 #endif 488 489 esdhc_setbits32(®s->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN); 490 491 /* Set the initial clock speed */ 492 mmc_set_clock(mmc, 400000); 493 494 /* Disable the BRR and BWR bits in IRQSTAT */ 495 esdhc_clrbits32(®s->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR); 496 497 /* Put the PROCTL reg back to the default */ 498 esdhc_write32(®s->proctl, PROCTL_INIT); 499 500 /* Set timout to the maximum value */ 501 esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16); 502 503 return 0; 504 } 505 506 static int esdhc_getcd(struct mmc *mmc) 507 { 508 struct fsl_esdhc_cfg *cfg = mmc->priv; 509 struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; 510 int timeout = 1000; 511 512 #ifdef CONFIG_ESDHC_DETECT_QUIRK 513 if (CONFIG_ESDHC_DETECT_QUIRK) 514 return 1; 515 #endif 516 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_CINS) && --timeout) 517 udelay(1000); 518 519 return timeout > 0; 520 } 521 522 static void esdhc_reset(struct fsl_esdhc *regs) 523 { 524 unsigned long timeout = 100; /* wait max 100 ms */ 525 526 /* reset the controller */ 527 esdhc_setbits32(®s->sysctl, SYSCTL_RSTA); 528 529 /* hardware clears the bit when it is done */ 530 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA) && --timeout) 531 udelay(1000); 532 if (!timeout) 533 printf("MMC/SD: Reset never completed.\n"); 534 } 535 536 static const struct mmc_ops esdhc_ops = { 537 .send_cmd = esdhc_send_cmd, 538 .set_ios = esdhc_set_ios, 539 .init = esdhc_init, 540 .getcd = esdhc_getcd, 541 }; 542 543 int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg) 544 { 545 struct fsl_esdhc *regs; 546 struct mmc *mmc; 547 u32 caps, voltage_caps; 548 549 if (!cfg) 550 return -1; 551 552 regs = (struct fsl_esdhc *)cfg->esdhc_base; 553 554 /* First reset the eSDHC controller */ 555 esdhc_reset(regs); 556 557 esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_HCKEN 558 | SYSCTL_IPGEN | SYSCTL_CKEN); 559 560 memset(&cfg->cfg, 0, sizeof(cfg->cfg)); 561 562 voltage_caps = 0; 563 caps = regs->hostcapblt; 564 565 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC135 566 caps = caps & ~(ESDHC_HOSTCAPBLT_SRS | 567 ESDHC_HOSTCAPBLT_VS18 | ESDHC_HOSTCAPBLT_VS30); 568 #endif 569 570 /* T4240 host controller capabilities register should have VS33 bit */ 571 #ifdef CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 572 caps = caps | ESDHC_HOSTCAPBLT_VS33; 573 #endif 574 575 if (caps & ESDHC_HOSTCAPBLT_VS18) 576 voltage_caps |= MMC_VDD_165_195; 577 if (caps & ESDHC_HOSTCAPBLT_VS30) 578 voltage_caps |= MMC_VDD_29_30 | MMC_VDD_30_31; 579 if (caps & ESDHC_HOSTCAPBLT_VS33) 580 voltage_caps |= MMC_VDD_32_33 | MMC_VDD_33_34; 581 582 cfg->cfg.name = "FSL_SDHC"; 583 cfg->cfg.ops = &esdhc_ops; 584 #ifdef CONFIG_SYS_SD_VOLTAGE 585 cfg->cfg.voltages = CONFIG_SYS_SD_VOLTAGE; 586 #else 587 cfg->cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34; 588 #endif 589 if ((cfg->cfg.voltages & voltage_caps) == 0) { 590 printf("voltage not supported by controller\n"); 591 return -1; 592 } 593 594 cfg->cfg.host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT | MMC_MODE_HC; 595 596 if (cfg->max_bus_width > 0) { 597 if (cfg->max_bus_width < 8) 598 cfg->cfg.host_caps &= ~MMC_MODE_8BIT; 599 if (cfg->max_bus_width < 4) 600 cfg->cfg.host_caps &= ~MMC_MODE_4BIT; 601 } 602 603 if (caps & ESDHC_HOSTCAPBLT_HSS) 604 cfg->cfg.host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS; 605 606 #ifdef CONFIG_ESDHC_DETECT_8_BIT_QUIRK 607 if (CONFIG_ESDHC_DETECT_8_BIT_QUIRK) 608 cfg->cfg.host_caps &= ~MMC_MODE_8BIT; 609 #endif 610 611 cfg->cfg.f_min = 400000; 612 cfg->cfg.f_max = MIN(gd->arch.sdhc_clk, 52000000); 613 614 cfg->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; 615 616 mmc = mmc_create(&cfg->cfg, cfg); 617 if (mmc == NULL) 618 return -1; 619 620 return 0; 621 } 622 623 int fsl_esdhc_mmc_init(bd_t *bis) 624 { 625 struct fsl_esdhc_cfg *cfg; 626 627 cfg = calloc(sizeof(struct fsl_esdhc_cfg), 1); 628 cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR; 629 cfg->sdhc_clk = gd->arch.sdhc_clk; 630 return fsl_esdhc_initialize(bis, cfg); 631 } 632 633 #ifdef CONFIG_OF_LIBFDT 634 void fdt_fixup_esdhc(void *blob, bd_t *bd) 635 { 636 const char *compat = "fsl,esdhc"; 637 638 #ifdef CONFIG_FSL_ESDHC_PIN_MUX 639 if (!hwconfig("esdhc")) { 640 do_fixup_by_compat(blob, compat, "status", "disabled", 641 8 + 1, 1); 642 return; 643 } 644 #endif 645 646 do_fixup_by_compat_u32(blob, compat, "clock-frequency", 647 gd->arch.sdhc_clk, 1); 648 649 do_fixup_by_compat(blob, compat, "status", "okay", 650 4 + 1, 1); 651 } 652 #endif 653