1 /* 2 * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc 3 * Andy Fleming 4 * 5 * Based vaguely on the pxa mmc code: 6 * (C) Copyright 2003 7 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net 8 * 9 * SPDX-License-Identifier: GPL-2.0+ 10 */ 11 12 #include <config.h> 13 #include <common.h> 14 #include <command.h> 15 #include <hwconfig.h> 16 #include <mmc.h> 17 #include <part.h> 18 #include <malloc.h> 19 #include <mmc.h> 20 #include <fsl_esdhc.h> 21 #include <fdt_support.h> 22 #include <asm/io.h> 23 24 DECLARE_GLOBAL_DATA_PTR; 25 26 #define SDHCI_IRQ_EN_BITS (IRQSTATEN_CC | IRQSTATEN_TC | \ 27 IRQSTATEN_CINT | \ 28 IRQSTATEN_CTOE | IRQSTATEN_CCE | IRQSTATEN_CEBE | \ 29 IRQSTATEN_CIE | IRQSTATEN_DTOE | IRQSTATEN_DCE | \ 30 IRQSTATEN_DEBE | IRQSTATEN_BRR | IRQSTATEN_BWR | \ 31 IRQSTATEN_DINT) 32 33 struct fsl_esdhc { 34 uint dsaddr; /* SDMA system address register */ 35 uint blkattr; /* Block attributes register */ 36 uint cmdarg; /* Command argument register */ 37 uint xfertyp; /* Transfer type register */ 38 uint cmdrsp0; /* Command response 0 register */ 39 uint cmdrsp1; /* Command response 1 register */ 40 uint cmdrsp2; /* Command response 2 register */ 41 uint cmdrsp3; /* Command response 3 register */ 42 uint datport; /* Buffer data port register */ 43 uint prsstat; /* Present state register */ 44 uint proctl; /* Protocol control register */ 45 uint sysctl; /* System Control Register */ 46 uint irqstat; /* Interrupt status register */ 47 uint irqstaten; /* Interrupt status enable register */ 48 uint irqsigen; /* Interrupt signal enable register */ 49 uint autoc12err; /* Auto CMD error status register */ 50 uint hostcapblt; /* Host controller capabilities register */ 51 uint wml; /* Watermark level register */ 52 uint mixctrl; /* For USDHC */ 53 char reserved1[4]; /* reserved */ 54 uint fevt; /* Force event register */ 55 uint admaes; /* ADMA error status register */ 56 uint adsaddr; /* ADMA system address register */ 57 char reserved2[100]; /* reserved */ 58 uint vendorspec; /* Vendor Specific register */ 59 char reserved3[56]; /* reserved */ 60 uint hostver; /* Host controller version register */ 61 char reserved4[4]; /* reserved */ 62 uint dmaerraddr; /* DMA error address register */ 63 char reserved5[4]; /* reserved */ 64 uint dmaerrattr; /* DMA error attribute register */ 65 char reserved6[4]; /* reserved */ 66 uint hostcapblt2; /* Host controller capabilities register 2 */ 67 char reserved7[8]; /* reserved */ 68 uint tcr; /* Tuning control register */ 69 char reserved8[28]; /* reserved */ 70 uint sddirctl; /* SD direction control register */ 71 char reserved9[712]; /* reserved */ 72 uint scr; /* eSDHC control register */ 73 }; 74 75 /* Return the XFERTYP flags for a given command and data packet */ 76 static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data) 77 { 78 uint xfertyp = 0; 79 80 if (data) { 81 xfertyp |= XFERTYP_DPSEL; 82 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO 83 xfertyp |= XFERTYP_DMAEN; 84 #endif 85 if (data->blocks > 1) { 86 xfertyp |= XFERTYP_MSBSEL; 87 xfertyp |= XFERTYP_BCEN; 88 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111 89 xfertyp |= XFERTYP_AC12EN; 90 #endif 91 } 92 93 if (data->flags & MMC_DATA_READ) 94 xfertyp |= XFERTYP_DTDSEL; 95 } 96 97 if (cmd->resp_type & MMC_RSP_CRC) 98 xfertyp |= XFERTYP_CCCEN; 99 if (cmd->resp_type & MMC_RSP_OPCODE) 100 xfertyp |= XFERTYP_CICEN; 101 if (cmd->resp_type & MMC_RSP_136) 102 xfertyp |= XFERTYP_RSPTYP_136; 103 else if (cmd->resp_type & MMC_RSP_BUSY) 104 xfertyp |= XFERTYP_RSPTYP_48_BUSY; 105 else if (cmd->resp_type & MMC_RSP_PRESENT) 106 xfertyp |= XFERTYP_RSPTYP_48; 107 108 #if defined(CONFIG_MX53) || defined(CONFIG_PPC_T4240) || \ 109 defined(CONFIG_LS102XA) || defined(CONFIG_LS2085A) 110 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) 111 xfertyp |= XFERTYP_CMDTYP_ABORT; 112 #endif 113 return XFERTYP_CMD(cmd->cmdidx) | xfertyp; 114 } 115 116 #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO 117 /* 118 * PIO Read/Write Mode reduce the performace as DMA is not used in this mode. 119 */ 120 static void 121 esdhc_pio_read_write(struct mmc *mmc, struct mmc_data *data) 122 { 123 struct fsl_esdhc_cfg *cfg = mmc->priv; 124 struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; 125 uint blocks; 126 char *buffer; 127 uint databuf; 128 uint size; 129 uint irqstat; 130 uint timeout; 131 132 if (data->flags & MMC_DATA_READ) { 133 blocks = data->blocks; 134 buffer = data->dest; 135 while (blocks) { 136 timeout = PIO_TIMEOUT; 137 size = data->blocksize; 138 irqstat = esdhc_read32(®s->irqstat); 139 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BREN) 140 && --timeout); 141 if (timeout <= 0) { 142 printf("\nData Read Failed in PIO Mode."); 143 return; 144 } 145 while (size && (!(irqstat & IRQSTAT_TC))) { 146 udelay(100); /* Wait before last byte transfer complete */ 147 irqstat = esdhc_read32(®s->irqstat); 148 databuf = in_le32(®s->datport); 149 *((uint *)buffer) = databuf; 150 buffer += 4; 151 size -= 4; 152 } 153 blocks--; 154 } 155 } else { 156 blocks = data->blocks; 157 buffer = (char *)data->src; 158 while (blocks) { 159 timeout = PIO_TIMEOUT; 160 size = data->blocksize; 161 irqstat = esdhc_read32(®s->irqstat); 162 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BWEN) 163 && --timeout); 164 if (timeout <= 0) { 165 printf("\nData Write Failed in PIO Mode."); 166 return; 167 } 168 while (size && (!(irqstat & IRQSTAT_TC))) { 169 udelay(100); /* Wait before last byte transfer complete */ 170 databuf = *((uint *)buffer); 171 buffer += 4; 172 size -= 4; 173 irqstat = esdhc_read32(®s->irqstat); 174 out_le32(®s->datport, databuf); 175 } 176 blocks--; 177 } 178 } 179 } 180 #endif 181 182 static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data) 183 { 184 int timeout; 185 struct fsl_esdhc_cfg *cfg = mmc->priv; 186 struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; 187 #ifdef CONFIG_LS2085A 188 dma_addr_t addr; 189 #endif 190 uint wml_value; 191 192 wml_value = data->blocksize/4; 193 194 if (data->flags & MMC_DATA_READ) { 195 if (wml_value > WML_RD_WML_MAX) 196 wml_value = WML_RD_WML_MAX_VAL; 197 198 esdhc_clrsetbits32(®s->wml, WML_RD_WML_MASK, wml_value); 199 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO 200 #ifdef CONFIG_LS2085A 201 addr = virt_to_phys((void *)(data->dest)); 202 if (upper_32_bits(addr)) 203 printf("Error found for upper 32 bits\n"); 204 else 205 esdhc_write32(®s->dsaddr, lower_32_bits(addr)); 206 #else 207 esdhc_write32(®s->dsaddr, (u32)data->dest); 208 #endif 209 #endif 210 } else { 211 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO 212 flush_dcache_range((ulong)data->src, 213 (ulong)data->src+data->blocks 214 *data->blocksize); 215 #endif 216 if (wml_value > WML_WR_WML_MAX) 217 wml_value = WML_WR_WML_MAX_VAL; 218 if ((esdhc_read32(®s->prsstat) & PRSSTAT_WPSPL) == 0) { 219 printf("\nThe SD card is locked. Can not write to a locked card.\n\n"); 220 return TIMEOUT; 221 } 222 223 esdhc_clrsetbits32(®s->wml, WML_WR_WML_MASK, 224 wml_value << 16); 225 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO 226 #ifdef CONFIG_LS2085A 227 addr = virt_to_phys((void *)(data->src)); 228 if (upper_32_bits(addr)) 229 printf("Error found for upper 32 bits\n"); 230 else 231 esdhc_write32(®s->dsaddr, lower_32_bits(addr)); 232 #else 233 esdhc_write32(®s->dsaddr, (u32)data->src); 234 #endif 235 #endif 236 } 237 238 esdhc_write32(®s->blkattr, data->blocks << 16 | data->blocksize); 239 240 /* Calculate the timeout period for data transactions */ 241 /* 242 * 1)Timeout period = (2^(timeout+13)) SD Clock cycles 243 * 2)Timeout period should be minimum 0.250sec as per SD Card spec 244 * So, Number of SD Clock cycles for 0.25sec should be minimum 245 * (SD Clock/sec * 0.25 sec) SD Clock cycles 246 * = (mmc->clock * 1/4) SD Clock cycles 247 * As 1) >= 2) 248 * => (2^(timeout+13)) >= mmc->clock * 1/4 249 * Taking log2 both the sides 250 * => timeout + 13 >= log2(mmc->clock/4) 251 * Rounding up to next power of 2 252 * => timeout + 13 = log2(mmc->clock/4) + 1 253 * => timeout + 13 = fls(mmc->clock/4) 254 */ 255 timeout = fls(mmc->clock/4); 256 timeout -= 13; 257 258 if (timeout > 14) 259 timeout = 14; 260 261 if (timeout < 0) 262 timeout = 0; 263 264 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC_A001 265 if ((timeout == 4) || (timeout == 8) || (timeout == 12)) 266 timeout++; 267 #endif 268 269 #ifdef ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE 270 timeout = 0xE; 271 #endif 272 esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16); 273 274 return 0; 275 } 276 277 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO 278 static void check_and_invalidate_dcache_range 279 (struct mmc_cmd *cmd, 280 struct mmc_data *data) { 281 #ifdef CONFIG_LS2085A 282 unsigned start = 0; 283 #else 284 unsigned start = (unsigned)data->dest ; 285 #endif 286 unsigned size = roundup(ARCH_DMA_MINALIGN, 287 data->blocks*data->blocksize); 288 unsigned end = start+size ; 289 #ifdef CONFIG_LS2085A 290 dma_addr_t addr; 291 292 addr = virt_to_phys((void *)(data->dest)); 293 if (upper_32_bits(addr)) 294 printf("Error found for upper 32 bits\n"); 295 else 296 start = lower_32_bits(addr); 297 #endif 298 invalidate_dcache_range(start, end); 299 } 300 #endif 301 302 /* 303 * Sends a command out on the bus. Takes the mmc pointer, 304 * a command pointer, and an optional data pointer. 305 */ 306 static int 307 esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) 308 { 309 int err = 0; 310 uint xfertyp; 311 uint irqstat; 312 struct fsl_esdhc_cfg *cfg = mmc->priv; 313 volatile struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; 314 315 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111 316 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) 317 return 0; 318 #endif 319 320 esdhc_write32(®s->irqstat, -1); 321 322 sync(); 323 324 /* Wait for the bus to be idle */ 325 while ((esdhc_read32(®s->prsstat) & PRSSTAT_CICHB) || 326 (esdhc_read32(®s->prsstat) & PRSSTAT_CIDHB)) 327 ; 328 329 while (esdhc_read32(®s->prsstat) & PRSSTAT_DLA) 330 ; 331 332 /* Wait at least 8 SD clock cycles before the next command */ 333 /* 334 * Note: This is way more than 8 cycles, but 1ms seems to 335 * resolve timing issues with some cards 336 */ 337 udelay(1000); 338 339 /* Set up for a data transfer if we have one */ 340 if (data) { 341 err = esdhc_setup_data(mmc, data); 342 if(err) 343 return err; 344 345 if (data->flags & MMC_DATA_READ) 346 check_and_invalidate_dcache_range(cmd, data); 347 } 348 349 /* Figure out the transfer arguments */ 350 xfertyp = esdhc_xfertyp(cmd, data); 351 352 /* Mask all irqs */ 353 esdhc_write32(®s->irqsigen, 0); 354 355 /* Send the command */ 356 esdhc_write32(®s->cmdarg, cmd->cmdarg); 357 #if defined(CONFIG_FSL_USDHC) 358 esdhc_write32(®s->mixctrl, 359 (esdhc_read32(®s->mixctrl) & 0xFFFFFF80) | (xfertyp & 0x7F) 360 | (mmc->ddr_mode ? XFERTYP_DDREN : 0)); 361 esdhc_write32(®s->xfertyp, xfertyp & 0xFFFF0000); 362 #else 363 esdhc_write32(®s->xfertyp, xfertyp); 364 #endif 365 366 /* Wait for the command to complete */ 367 while (!(esdhc_read32(®s->irqstat) & (IRQSTAT_CC | IRQSTAT_CTOE))) 368 ; 369 370 irqstat = esdhc_read32(®s->irqstat); 371 372 if (irqstat & CMD_ERR) { 373 err = COMM_ERR; 374 goto out; 375 } 376 377 if (irqstat & IRQSTAT_CTOE) { 378 err = TIMEOUT; 379 goto out; 380 } 381 382 /* Switch voltage to 1.8V if CMD11 succeeded */ 383 if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V) { 384 esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT); 385 386 printf("Run CMD11 1.8V switch\n"); 387 /* Sleep for 5 ms - max time for card to switch to 1.8V */ 388 udelay(5000); 389 } 390 391 /* Workaround for ESDHC errata ENGcm03648 */ 392 if (!data && (cmd->resp_type & MMC_RSP_BUSY)) { 393 int timeout = 6000; 394 395 /* Poll on DATA0 line for cmd with busy signal for 600 ms */ 396 while (timeout > 0 && !(esdhc_read32(®s->prsstat) & 397 PRSSTAT_DAT0)) { 398 udelay(100); 399 timeout--; 400 } 401 402 if (timeout <= 0) { 403 printf("Timeout waiting for DAT0 to go high!\n"); 404 err = TIMEOUT; 405 goto out; 406 } 407 } 408 409 /* Copy the response to the response buffer */ 410 if (cmd->resp_type & MMC_RSP_136) { 411 u32 cmdrsp3, cmdrsp2, cmdrsp1, cmdrsp0; 412 413 cmdrsp3 = esdhc_read32(®s->cmdrsp3); 414 cmdrsp2 = esdhc_read32(®s->cmdrsp2); 415 cmdrsp1 = esdhc_read32(®s->cmdrsp1); 416 cmdrsp0 = esdhc_read32(®s->cmdrsp0); 417 cmd->response[0] = (cmdrsp3 << 8) | (cmdrsp2 >> 24); 418 cmd->response[1] = (cmdrsp2 << 8) | (cmdrsp1 >> 24); 419 cmd->response[2] = (cmdrsp1 << 8) | (cmdrsp0 >> 24); 420 cmd->response[3] = (cmdrsp0 << 8); 421 } else 422 cmd->response[0] = esdhc_read32(®s->cmdrsp0); 423 424 /* Wait until all of the blocks are transferred */ 425 if (data) { 426 #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO 427 esdhc_pio_read_write(mmc, data); 428 #else 429 do { 430 irqstat = esdhc_read32(®s->irqstat); 431 432 if (irqstat & IRQSTAT_DTOE) { 433 err = TIMEOUT; 434 goto out; 435 } 436 437 if (irqstat & DATA_ERR) { 438 err = COMM_ERR; 439 goto out; 440 } 441 } while ((irqstat & DATA_COMPLETE) != DATA_COMPLETE); 442 443 /* 444 * Need invalidate the dcache here again to avoid any 445 * cache-fill during the DMA operations such as the 446 * speculative pre-fetching etc. 447 */ 448 if (data->flags & MMC_DATA_READ) 449 check_and_invalidate_dcache_range(cmd, data); 450 #endif 451 } 452 453 out: 454 /* Reset CMD and DATA portions on error */ 455 if (err) { 456 esdhc_write32(®s->sysctl, esdhc_read32(®s->sysctl) | 457 SYSCTL_RSTC); 458 while (esdhc_read32(®s->sysctl) & SYSCTL_RSTC) 459 ; 460 461 if (data) { 462 esdhc_write32(®s->sysctl, 463 esdhc_read32(®s->sysctl) | 464 SYSCTL_RSTD); 465 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTD)) 466 ; 467 } 468 469 /* If this was CMD11, then notify that power cycle is needed */ 470 if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V) 471 printf("CMD11 to switch to 1.8V mode failed, card requires power cycle.\n"); 472 } 473 474 esdhc_write32(®s->irqstat, -1); 475 476 return err; 477 } 478 479 static void set_sysctl(struct mmc *mmc, uint clock) 480 { 481 int div, pre_div; 482 struct fsl_esdhc_cfg *cfg = mmc->priv; 483 volatile struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; 484 int sdhc_clk = cfg->sdhc_clk; 485 uint clk; 486 487 if (clock < mmc->cfg->f_min) 488 clock = mmc->cfg->f_min; 489 490 if (sdhc_clk / 16 > clock) { 491 for (pre_div = 2; pre_div < 256; pre_div *= 2) 492 if ((sdhc_clk / pre_div) <= (clock * 16)) 493 break; 494 } else 495 pre_div = 2; 496 497 for (div = 1; div <= 16; div++) 498 if ((sdhc_clk / (div * pre_div)) <= clock) 499 break; 500 501 pre_div >>= mmc->ddr_mode ? 2 : 1; 502 div -= 1; 503 504 clk = (pre_div << 8) | (div << 4); 505 506 esdhc_clrbits32(®s->sysctl, SYSCTL_CKEN); 507 508 esdhc_clrsetbits32(®s->sysctl, SYSCTL_CLOCK_MASK, clk); 509 510 udelay(10000); 511 512 clk = SYSCTL_PEREN | SYSCTL_CKEN; 513 514 esdhc_setbits32(®s->sysctl, clk); 515 } 516 517 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK 518 static void esdhc_clock_control(struct mmc *mmc, bool enable) 519 { 520 struct fsl_esdhc_cfg *cfg = mmc->priv; 521 struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; 522 u32 value; 523 u32 time_out; 524 525 value = esdhc_read32(®s->sysctl); 526 527 if (enable) 528 value |= SYSCTL_CKEN; 529 else 530 value &= ~SYSCTL_CKEN; 531 532 esdhc_write32(®s->sysctl, value); 533 534 time_out = 20; 535 value = PRSSTAT_SDSTB; 536 while (!(esdhc_read32(®s->prsstat) & value)) { 537 if (time_out == 0) { 538 printf("fsl_esdhc: Internal clock never stabilised.\n"); 539 break; 540 } 541 time_out--; 542 mdelay(1); 543 } 544 } 545 #endif 546 547 static void esdhc_set_ios(struct mmc *mmc) 548 { 549 struct fsl_esdhc_cfg *cfg = mmc->priv; 550 struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; 551 552 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK 553 /* Select to use peripheral clock */ 554 esdhc_clock_control(mmc, false); 555 esdhc_setbits32(®s->scr, ESDHCCTL_PCS); 556 esdhc_clock_control(mmc, true); 557 #endif 558 /* Set the clock speed */ 559 set_sysctl(mmc, mmc->clock); 560 561 /* Set the bus width */ 562 esdhc_clrbits32(®s->proctl, PROCTL_DTW_4 | PROCTL_DTW_8); 563 564 if (mmc->bus_width == 4) 565 esdhc_setbits32(®s->proctl, PROCTL_DTW_4); 566 else if (mmc->bus_width == 8) 567 esdhc_setbits32(®s->proctl, PROCTL_DTW_8); 568 569 } 570 571 static int esdhc_init(struct mmc *mmc) 572 { 573 struct fsl_esdhc_cfg *cfg = mmc->priv; 574 struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; 575 int timeout = 1000; 576 577 /* Reset the entire host controller */ 578 esdhc_setbits32(®s->sysctl, SYSCTL_RSTA); 579 580 /* Wait until the controller is available */ 581 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA) && --timeout) 582 udelay(1000); 583 584 #ifndef ARCH_MXC 585 /* Enable cache snooping */ 586 esdhc_write32(®s->scr, 0x00000040); 587 #endif 588 589 esdhc_setbits32(®s->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN); 590 591 /* Set the initial clock speed */ 592 mmc_set_clock(mmc, 400000); 593 594 /* Disable the BRR and BWR bits in IRQSTAT */ 595 esdhc_clrbits32(®s->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR); 596 597 /* Put the PROCTL reg back to the default */ 598 esdhc_write32(®s->proctl, PROCTL_INIT); 599 600 /* Set timout to the maximum value */ 601 esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16); 602 603 #ifdef CONFIG_SYS_FSL_ESDHC_FORCE_VSELECT 604 esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT); 605 #endif 606 607 return 0; 608 } 609 610 static int esdhc_getcd(struct mmc *mmc) 611 { 612 struct fsl_esdhc_cfg *cfg = mmc->priv; 613 struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; 614 int timeout = 1000; 615 616 #ifdef CONFIG_ESDHC_DETECT_QUIRK 617 if (CONFIG_ESDHC_DETECT_QUIRK) 618 return 1; 619 #endif 620 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_CINS) && --timeout) 621 udelay(1000); 622 623 return timeout > 0; 624 } 625 626 static void esdhc_reset(struct fsl_esdhc *regs) 627 { 628 unsigned long timeout = 100; /* wait max 100 ms */ 629 630 /* reset the controller */ 631 esdhc_setbits32(®s->sysctl, SYSCTL_RSTA); 632 633 /* hardware clears the bit when it is done */ 634 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA) && --timeout) 635 udelay(1000); 636 if (!timeout) 637 printf("MMC/SD: Reset never completed.\n"); 638 } 639 640 static const struct mmc_ops esdhc_ops = { 641 .send_cmd = esdhc_send_cmd, 642 .set_ios = esdhc_set_ios, 643 .init = esdhc_init, 644 .getcd = esdhc_getcd, 645 }; 646 647 int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg) 648 { 649 struct fsl_esdhc *regs; 650 struct mmc *mmc; 651 u32 caps, voltage_caps; 652 653 if (!cfg) 654 return -1; 655 656 regs = (struct fsl_esdhc *)cfg->esdhc_base; 657 658 /* First reset the eSDHC controller */ 659 esdhc_reset(regs); 660 661 esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_HCKEN 662 | SYSCTL_IPGEN | SYSCTL_CKEN); 663 664 writel(SDHCI_IRQ_EN_BITS, ®s->irqstaten); 665 memset(&cfg->cfg, 0, sizeof(cfg->cfg)); 666 667 voltage_caps = 0; 668 caps = esdhc_read32(®s->hostcapblt); 669 670 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC135 671 caps = caps & ~(ESDHC_HOSTCAPBLT_SRS | 672 ESDHC_HOSTCAPBLT_VS18 | ESDHC_HOSTCAPBLT_VS30); 673 #endif 674 675 /* T4240 host controller capabilities register should have VS33 bit */ 676 #ifdef CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 677 caps = caps | ESDHC_HOSTCAPBLT_VS33; 678 #endif 679 680 if (caps & ESDHC_HOSTCAPBLT_VS18) 681 voltage_caps |= MMC_VDD_165_195; 682 if (caps & ESDHC_HOSTCAPBLT_VS30) 683 voltage_caps |= MMC_VDD_29_30 | MMC_VDD_30_31; 684 if (caps & ESDHC_HOSTCAPBLT_VS33) 685 voltage_caps |= MMC_VDD_32_33 | MMC_VDD_33_34; 686 687 cfg->cfg.name = "FSL_SDHC"; 688 cfg->cfg.ops = &esdhc_ops; 689 #ifdef CONFIG_SYS_SD_VOLTAGE 690 cfg->cfg.voltages = CONFIG_SYS_SD_VOLTAGE; 691 #else 692 cfg->cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34; 693 #endif 694 if ((cfg->cfg.voltages & voltage_caps) == 0) { 695 printf("voltage not supported by controller\n"); 696 return -1; 697 } 698 699 cfg->cfg.host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT; 700 #ifdef CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE 701 cfg->cfg.host_caps |= MMC_MODE_DDR_52MHz; 702 #endif 703 704 if (cfg->max_bus_width > 0) { 705 if (cfg->max_bus_width < 8) 706 cfg->cfg.host_caps &= ~MMC_MODE_8BIT; 707 if (cfg->max_bus_width < 4) 708 cfg->cfg.host_caps &= ~MMC_MODE_4BIT; 709 } 710 711 if (caps & ESDHC_HOSTCAPBLT_HSS) 712 cfg->cfg.host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS; 713 714 #ifdef CONFIG_ESDHC_DETECT_8_BIT_QUIRK 715 if (CONFIG_ESDHC_DETECT_8_BIT_QUIRK) 716 cfg->cfg.host_caps &= ~MMC_MODE_8BIT; 717 #endif 718 719 cfg->cfg.f_min = 400000; 720 cfg->cfg.f_max = min(cfg->sdhc_clk, (u32)52000000); 721 722 cfg->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; 723 724 mmc = mmc_create(&cfg->cfg, cfg); 725 if (mmc == NULL) 726 return -1; 727 728 return 0; 729 } 730 731 int fsl_esdhc_mmc_init(bd_t *bis) 732 { 733 struct fsl_esdhc_cfg *cfg; 734 735 cfg = calloc(sizeof(struct fsl_esdhc_cfg), 1); 736 cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR; 737 cfg->sdhc_clk = gd->arch.sdhc_clk; 738 return fsl_esdhc_initialize(bis, cfg); 739 } 740 741 #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT 742 void mmc_adapter_card_type_ident(void) 743 { 744 u8 card_id; 745 u8 value; 746 747 card_id = QIXIS_READ(present) & QIXIS_SDID_MASK; 748 gd->arch.sdhc_adapter = card_id; 749 750 switch (card_id) { 751 case QIXIS_ESDHC_ADAPTER_TYPE_EMMC45: 752 break; 753 case QIXIS_ESDHC_ADAPTER_TYPE_SDMMC_LEGACY: 754 break; 755 case QIXIS_ESDHC_ADAPTER_TYPE_EMMC44: 756 value = QIXIS_READ(brdcfg[5]); 757 value |= (QIXIS_SDCLKIN | QIXIS_SDCLKOUT); 758 QIXIS_WRITE(brdcfg[5], value); 759 break; 760 case QIXIS_ESDHC_ADAPTER_TYPE_RSV: 761 break; 762 case QIXIS_ESDHC_ADAPTER_TYPE_MMC: 763 break; 764 case QIXIS_ESDHC_ADAPTER_TYPE_SD: 765 break; 766 case QIXIS_ESDHC_NO_ADAPTER: 767 break; 768 default: 769 break; 770 } 771 } 772 #endif 773 774 #ifdef CONFIG_OF_LIBFDT 775 void fdt_fixup_esdhc(void *blob, bd_t *bd) 776 { 777 const char *compat = "fsl,esdhc"; 778 779 #ifdef CONFIG_FSL_ESDHC_PIN_MUX 780 if (!hwconfig("esdhc")) { 781 do_fixup_by_compat(blob, compat, "status", "disabled", 782 8 + 1, 1); 783 return; 784 } 785 #endif 786 787 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK 788 do_fixup_by_compat_u32(blob, compat, "peripheral-frequency", 789 gd->arch.sdhc_clk, 1); 790 #else 791 do_fixup_by_compat_u32(blob, compat, "clock-frequency", 792 gd->arch.sdhc_clk, 1); 793 #endif 794 #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT 795 do_fixup_by_compat_u32(blob, compat, "adapter-type", 796 (u32)(gd->arch.sdhc_adapter), 1); 797 #endif 798 do_fixup_by_compat(blob, compat, "status", "okay", 799 4 + 1, 1); 800 } 801 #endif 802