1 /* 2 * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc 3 * Andy Fleming 4 * 5 * Based vaguely on the pxa mmc code: 6 * (C) Copyright 2003 7 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net 8 * 9 * SPDX-License-Identifier: GPL-2.0+ 10 */ 11 12 #include <config.h> 13 #include <common.h> 14 #include <command.h> 15 #include <errno.h> 16 #include <hwconfig.h> 17 #include <mmc.h> 18 #include <part.h> 19 #include <power/regulator.h> 20 #include <malloc.h> 21 #include <fsl_esdhc.h> 22 #include <fdt_support.h> 23 #include <asm/io.h> 24 #include <dm.h> 25 #include <asm-generic/gpio.h> 26 27 DECLARE_GLOBAL_DATA_PTR; 28 29 #define SDHCI_IRQ_EN_BITS (IRQSTATEN_CC | IRQSTATEN_TC | \ 30 IRQSTATEN_CINT | \ 31 IRQSTATEN_CTOE | IRQSTATEN_CCE | IRQSTATEN_CEBE | \ 32 IRQSTATEN_CIE | IRQSTATEN_DTOE | IRQSTATEN_DCE | \ 33 IRQSTATEN_DEBE | IRQSTATEN_BRR | IRQSTATEN_BWR | \ 34 IRQSTATEN_DINT) 35 36 struct fsl_esdhc { 37 uint dsaddr; /* SDMA system address register */ 38 uint blkattr; /* Block attributes register */ 39 uint cmdarg; /* Command argument register */ 40 uint xfertyp; /* Transfer type register */ 41 uint cmdrsp0; /* Command response 0 register */ 42 uint cmdrsp1; /* Command response 1 register */ 43 uint cmdrsp2; /* Command response 2 register */ 44 uint cmdrsp3; /* Command response 3 register */ 45 uint datport; /* Buffer data port register */ 46 uint prsstat; /* Present state register */ 47 uint proctl; /* Protocol control register */ 48 uint sysctl; /* System Control Register */ 49 uint irqstat; /* Interrupt status register */ 50 uint irqstaten; /* Interrupt status enable register */ 51 uint irqsigen; /* Interrupt signal enable register */ 52 uint autoc12err; /* Auto CMD error status register */ 53 uint hostcapblt; /* Host controller capabilities register */ 54 uint wml; /* Watermark level register */ 55 uint mixctrl; /* For USDHC */ 56 char reserved1[4]; /* reserved */ 57 uint fevt; /* Force event register */ 58 uint admaes; /* ADMA error status register */ 59 uint adsaddr; /* ADMA system address register */ 60 char reserved2[4]; 61 uint dllctrl; 62 uint dllstat; 63 uint clktunectrlstatus; 64 char reserved3[84]; 65 uint vendorspec; 66 uint mmcboot; 67 uint vendorspec2; 68 char reserved4[48]; 69 uint hostver; /* Host controller version register */ 70 char reserved5[4]; /* reserved */ 71 uint dmaerraddr; /* DMA error address register */ 72 char reserved6[4]; /* reserved */ 73 uint dmaerrattr; /* DMA error attribute register */ 74 char reserved7[4]; /* reserved */ 75 uint hostcapblt2; /* Host controller capabilities register 2 */ 76 char reserved8[8]; /* reserved */ 77 uint tcr; /* Tuning control register */ 78 char reserved9[28]; /* reserved */ 79 uint sddirctl; /* SD direction control register */ 80 char reserved10[712];/* reserved */ 81 uint scr; /* eSDHC control register */ 82 }; 83 84 /** 85 * struct fsl_esdhc_priv 86 * 87 * @esdhc_regs: registers of the sdhc controller 88 * @sdhc_clk: Current clk of the sdhc controller 89 * @bus_width: bus width, 1bit, 4bit or 8bit 90 * @cfg: mmc config 91 * @mmc: mmc 92 * Following is used when Driver Model is enabled for MMC 93 * @dev: pointer for the device 94 * @non_removable: 0: removable; 1: non-removable 95 * @wp_enable: 1: enable checking wp; 0: no check 96 * @vs18_enable: 1: use 1.8V voltage; 0: use 3.3V 97 * @cd_gpio: gpio for card detection 98 * @wp_gpio: gpio for write protection 99 */ 100 struct fsl_esdhc_priv { 101 struct fsl_esdhc *esdhc_regs; 102 unsigned int sdhc_clk; 103 unsigned int bus_width; 104 struct mmc_config cfg; 105 struct mmc *mmc; 106 struct udevice *dev; 107 int non_removable; 108 int wp_enable; 109 int vs18_enable; 110 #ifdef CONFIG_DM_GPIO 111 struct gpio_desc cd_gpio; 112 struct gpio_desc wp_gpio; 113 #endif 114 }; 115 116 /* Return the XFERTYP flags for a given command and data packet */ 117 static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data) 118 { 119 uint xfertyp = 0; 120 121 if (data) { 122 xfertyp |= XFERTYP_DPSEL; 123 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO 124 xfertyp |= XFERTYP_DMAEN; 125 #endif 126 if (data->blocks > 1) { 127 xfertyp |= XFERTYP_MSBSEL; 128 xfertyp |= XFERTYP_BCEN; 129 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111 130 xfertyp |= XFERTYP_AC12EN; 131 #endif 132 } 133 134 if (data->flags & MMC_DATA_READ) 135 xfertyp |= XFERTYP_DTDSEL; 136 } 137 138 if (cmd->resp_type & MMC_RSP_CRC) 139 xfertyp |= XFERTYP_CCCEN; 140 if (cmd->resp_type & MMC_RSP_OPCODE) 141 xfertyp |= XFERTYP_CICEN; 142 if (cmd->resp_type & MMC_RSP_136) 143 xfertyp |= XFERTYP_RSPTYP_136; 144 else if (cmd->resp_type & MMC_RSP_BUSY) 145 xfertyp |= XFERTYP_RSPTYP_48_BUSY; 146 else if (cmd->resp_type & MMC_RSP_PRESENT) 147 xfertyp |= XFERTYP_RSPTYP_48; 148 149 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) 150 xfertyp |= XFERTYP_CMDTYP_ABORT; 151 152 return XFERTYP_CMD(cmd->cmdidx) | xfertyp; 153 } 154 155 #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO 156 /* 157 * PIO Read/Write Mode reduce the performace as DMA is not used in this mode. 158 */ 159 static void esdhc_pio_read_write(struct fsl_esdhc_priv *priv, 160 struct mmc_data *data) 161 { 162 struct fsl_esdhc *regs = priv->esdhc_regs; 163 uint blocks; 164 char *buffer; 165 uint databuf; 166 uint size; 167 uint irqstat; 168 uint timeout; 169 170 if (data->flags & MMC_DATA_READ) { 171 blocks = data->blocks; 172 buffer = data->dest; 173 while (blocks) { 174 timeout = PIO_TIMEOUT; 175 size = data->blocksize; 176 irqstat = esdhc_read32(®s->irqstat); 177 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BREN) 178 && --timeout); 179 if (timeout <= 0) { 180 printf("\nData Read Failed in PIO Mode."); 181 return; 182 } 183 while (size && (!(irqstat & IRQSTAT_TC))) { 184 udelay(100); /* Wait before last byte transfer complete */ 185 irqstat = esdhc_read32(®s->irqstat); 186 databuf = in_le32(®s->datport); 187 *((uint *)buffer) = databuf; 188 buffer += 4; 189 size -= 4; 190 } 191 blocks--; 192 } 193 } else { 194 blocks = data->blocks; 195 buffer = (char *)data->src; 196 while (blocks) { 197 timeout = PIO_TIMEOUT; 198 size = data->blocksize; 199 irqstat = esdhc_read32(®s->irqstat); 200 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BWEN) 201 && --timeout); 202 if (timeout <= 0) { 203 printf("\nData Write Failed in PIO Mode."); 204 return; 205 } 206 while (size && (!(irqstat & IRQSTAT_TC))) { 207 udelay(100); /* Wait before last byte transfer complete */ 208 databuf = *((uint *)buffer); 209 buffer += 4; 210 size -= 4; 211 irqstat = esdhc_read32(®s->irqstat); 212 out_le32(®s->datport, databuf); 213 } 214 blocks--; 215 } 216 } 217 } 218 #endif 219 220 static int esdhc_setup_data(struct fsl_esdhc_priv *priv, struct mmc *mmc, 221 struct mmc_data *data) 222 { 223 int timeout; 224 struct fsl_esdhc *regs = priv->esdhc_regs; 225 #if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) 226 dma_addr_t addr; 227 #endif 228 uint wml_value; 229 230 wml_value = data->blocksize/4; 231 232 if (data->flags & MMC_DATA_READ) { 233 if (wml_value > WML_RD_WML_MAX) 234 wml_value = WML_RD_WML_MAX_VAL; 235 236 esdhc_clrsetbits32(®s->wml, WML_RD_WML_MASK, wml_value); 237 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO 238 #if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) 239 addr = virt_to_phys((void *)(data->dest)); 240 if (upper_32_bits(addr)) 241 printf("Error found for upper 32 bits\n"); 242 else 243 esdhc_write32(®s->dsaddr, lower_32_bits(addr)); 244 #else 245 esdhc_write32(®s->dsaddr, (u32)data->dest); 246 #endif 247 #endif 248 } else { 249 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO 250 flush_dcache_range((ulong)data->src, 251 (ulong)data->src+data->blocks 252 *data->blocksize); 253 #endif 254 if (wml_value > WML_WR_WML_MAX) 255 wml_value = WML_WR_WML_MAX_VAL; 256 if (priv->wp_enable) { 257 if ((esdhc_read32(®s->prsstat) & 258 PRSSTAT_WPSPL) == 0) { 259 printf("\nThe SD card is locked. Can not write to a locked card.\n\n"); 260 return -ETIMEDOUT; 261 } 262 } 263 264 esdhc_clrsetbits32(®s->wml, WML_WR_WML_MASK, 265 wml_value << 16); 266 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO 267 #if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) 268 addr = virt_to_phys((void *)(data->src)); 269 if (upper_32_bits(addr)) 270 printf("Error found for upper 32 bits\n"); 271 else 272 esdhc_write32(®s->dsaddr, lower_32_bits(addr)); 273 #else 274 esdhc_write32(®s->dsaddr, (u32)data->src); 275 #endif 276 #endif 277 } 278 279 esdhc_write32(®s->blkattr, data->blocks << 16 | data->blocksize); 280 281 /* Calculate the timeout period for data transactions */ 282 /* 283 * 1)Timeout period = (2^(timeout+13)) SD Clock cycles 284 * 2)Timeout period should be minimum 0.250sec as per SD Card spec 285 * So, Number of SD Clock cycles for 0.25sec should be minimum 286 * (SD Clock/sec * 0.25 sec) SD Clock cycles 287 * = (mmc->clock * 1/4) SD Clock cycles 288 * As 1) >= 2) 289 * => (2^(timeout+13)) >= mmc->clock * 1/4 290 * Taking log2 both the sides 291 * => timeout + 13 >= log2(mmc->clock/4) 292 * Rounding up to next power of 2 293 * => timeout + 13 = log2(mmc->clock/4) + 1 294 * => timeout + 13 = fls(mmc->clock/4) 295 * 296 * However, the MMC spec "It is strongly recommended for hosts to 297 * implement more than 500ms timeout value even if the card 298 * indicates the 250ms maximum busy length." Even the previous 299 * value of 300ms is known to be insufficient for some cards. 300 * So, we use 301 * => timeout + 13 = fls(mmc->clock/2) 302 */ 303 timeout = fls(mmc->clock/2); 304 timeout -= 13; 305 306 if (timeout > 14) 307 timeout = 14; 308 309 if (timeout < 0) 310 timeout = 0; 311 312 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC_A001 313 if ((timeout == 4) || (timeout == 8) || (timeout == 12)) 314 timeout++; 315 #endif 316 317 #ifdef ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE 318 timeout = 0xE; 319 #endif 320 esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16); 321 322 return 0; 323 } 324 325 static void check_and_invalidate_dcache_range 326 (struct mmc_cmd *cmd, 327 struct mmc_data *data) { 328 unsigned start = 0; 329 unsigned end = 0; 330 unsigned size = roundup(ARCH_DMA_MINALIGN, 331 data->blocks*data->blocksize); 332 #if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) 333 dma_addr_t addr; 334 335 addr = virt_to_phys((void *)(data->dest)); 336 if (upper_32_bits(addr)) 337 printf("Error found for upper 32 bits\n"); 338 else 339 start = lower_32_bits(addr); 340 #else 341 start = (unsigned)data->dest; 342 #endif 343 end = start + size; 344 invalidate_dcache_range(start, end); 345 } 346 347 /* 348 * Sends a command out on the bus. Takes the mmc pointer, 349 * a command pointer, and an optional data pointer. 350 */ 351 static int esdhc_send_cmd_common(struct fsl_esdhc_priv *priv, struct mmc *mmc, 352 struct mmc_cmd *cmd, struct mmc_data *data) 353 { 354 int err = 0; 355 uint xfertyp; 356 uint irqstat; 357 struct fsl_esdhc *regs = priv->esdhc_regs; 358 359 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111 360 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) 361 return 0; 362 #endif 363 364 esdhc_write32(®s->irqstat, -1); 365 366 sync(); 367 368 /* Wait for the bus to be idle */ 369 while ((esdhc_read32(®s->prsstat) & PRSSTAT_CICHB) || 370 (esdhc_read32(®s->prsstat) & PRSSTAT_CIDHB)) 371 ; 372 373 while (esdhc_read32(®s->prsstat) & PRSSTAT_DLA) 374 ; 375 376 /* Wait at least 8 SD clock cycles before the next command */ 377 /* 378 * Note: This is way more than 8 cycles, but 1ms seems to 379 * resolve timing issues with some cards 380 */ 381 udelay(1000); 382 383 /* Set up for a data transfer if we have one */ 384 if (data) { 385 err = esdhc_setup_data(priv, mmc, data); 386 if(err) 387 return err; 388 389 if (data->flags & MMC_DATA_READ) 390 check_and_invalidate_dcache_range(cmd, data); 391 } 392 393 /* Figure out the transfer arguments */ 394 xfertyp = esdhc_xfertyp(cmd, data); 395 396 /* Mask all irqs */ 397 esdhc_write32(®s->irqsigen, 0); 398 399 /* Send the command */ 400 esdhc_write32(®s->cmdarg, cmd->cmdarg); 401 #if defined(CONFIG_FSL_USDHC) 402 esdhc_write32(®s->mixctrl, 403 (esdhc_read32(®s->mixctrl) & 0xFFFFFF80) | (xfertyp & 0x7F) 404 | (mmc->ddr_mode ? XFERTYP_DDREN : 0)); 405 esdhc_write32(®s->xfertyp, xfertyp & 0xFFFF0000); 406 #else 407 esdhc_write32(®s->xfertyp, xfertyp); 408 #endif 409 410 /* Wait for the command to complete */ 411 while (!(esdhc_read32(®s->irqstat) & (IRQSTAT_CC | IRQSTAT_CTOE))) 412 ; 413 414 irqstat = esdhc_read32(®s->irqstat); 415 416 if (irqstat & CMD_ERR) { 417 err = -ECOMM; 418 goto out; 419 } 420 421 if (irqstat & IRQSTAT_CTOE) { 422 err = -ETIMEDOUT; 423 goto out; 424 } 425 426 /* Switch voltage to 1.8V if CMD11 succeeded */ 427 if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V) { 428 esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT); 429 430 printf("Run CMD11 1.8V switch\n"); 431 /* Sleep for 5 ms - max time for card to switch to 1.8V */ 432 udelay(5000); 433 } 434 435 /* Workaround for ESDHC errata ENGcm03648 */ 436 if (!data && (cmd->resp_type & MMC_RSP_BUSY)) { 437 int timeout = 6000; 438 439 /* Poll on DATA0 line for cmd with busy signal for 600 ms */ 440 while (timeout > 0 && !(esdhc_read32(®s->prsstat) & 441 PRSSTAT_DAT0)) { 442 udelay(100); 443 timeout--; 444 } 445 446 if (timeout <= 0) { 447 printf("Timeout waiting for DAT0 to go high!\n"); 448 err = -ETIMEDOUT; 449 goto out; 450 } 451 } 452 453 /* Copy the response to the response buffer */ 454 if (cmd->resp_type & MMC_RSP_136) { 455 u32 cmdrsp3, cmdrsp2, cmdrsp1, cmdrsp0; 456 457 cmdrsp3 = esdhc_read32(®s->cmdrsp3); 458 cmdrsp2 = esdhc_read32(®s->cmdrsp2); 459 cmdrsp1 = esdhc_read32(®s->cmdrsp1); 460 cmdrsp0 = esdhc_read32(®s->cmdrsp0); 461 cmd->response[0] = (cmdrsp3 << 8) | (cmdrsp2 >> 24); 462 cmd->response[1] = (cmdrsp2 << 8) | (cmdrsp1 >> 24); 463 cmd->response[2] = (cmdrsp1 << 8) | (cmdrsp0 >> 24); 464 cmd->response[3] = (cmdrsp0 << 8); 465 } else 466 cmd->response[0] = esdhc_read32(®s->cmdrsp0); 467 468 /* Wait until all of the blocks are transferred */ 469 if (data) { 470 #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO 471 esdhc_pio_read_write(priv, data); 472 #else 473 do { 474 irqstat = esdhc_read32(®s->irqstat); 475 476 if (irqstat & IRQSTAT_DTOE) { 477 err = -ETIMEDOUT; 478 goto out; 479 } 480 481 if (irqstat & DATA_ERR) { 482 err = -ECOMM; 483 goto out; 484 } 485 } while ((irqstat & DATA_COMPLETE) != DATA_COMPLETE); 486 487 /* 488 * Need invalidate the dcache here again to avoid any 489 * cache-fill during the DMA operations such as the 490 * speculative pre-fetching etc. 491 */ 492 if (data->flags & MMC_DATA_READ) 493 check_and_invalidate_dcache_range(cmd, data); 494 #endif 495 } 496 497 out: 498 /* Reset CMD and DATA portions on error */ 499 if (err) { 500 esdhc_write32(®s->sysctl, esdhc_read32(®s->sysctl) | 501 SYSCTL_RSTC); 502 while (esdhc_read32(®s->sysctl) & SYSCTL_RSTC) 503 ; 504 505 if (data) { 506 esdhc_write32(®s->sysctl, 507 esdhc_read32(®s->sysctl) | 508 SYSCTL_RSTD); 509 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTD)) 510 ; 511 } 512 513 /* If this was CMD11, then notify that power cycle is needed */ 514 if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V) 515 printf("CMD11 to switch to 1.8V mode failed, card requires power cycle.\n"); 516 } 517 518 esdhc_write32(®s->irqstat, -1); 519 520 return err; 521 } 522 523 static void set_sysctl(struct fsl_esdhc_priv *priv, struct mmc *mmc, uint clock) 524 { 525 int div = 1; 526 #ifdef ARCH_MXC 527 int pre_div = 1; 528 #else 529 int pre_div = 2; 530 #endif 531 int ddr_pre_div = mmc->ddr_mode ? 2 : 1; 532 struct fsl_esdhc *regs = priv->esdhc_regs; 533 int sdhc_clk = priv->sdhc_clk; 534 uint clk; 535 536 if (clock < mmc->cfg->f_min) 537 clock = mmc->cfg->f_min; 538 539 while (sdhc_clk / (16 * pre_div * ddr_pre_div) > clock && pre_div < 256) 540 pre_div *= 2; 541 542 while (sdhc_clk / (div * pre_div * ddr_pre_div) > clock && div < 16) 543 div++; 544 545 pre_div >>= 1; 546 div -= 1; 547 548 clk = (pre_div << 8) | (div << 4); 549 550 #ifdef CONFIG_FSL_USDHC 551 esdhc_clrbits32(®s->vendorspec, VENDORSPEC_CKEN); 552 #else 553 esdhc_clrbits32(®s->sysctl, SYSCTL_CKEN); 554 #endif 555 556 esdhc_clrsetbits32(®s->sysctl, SYSCTL_CLOCK_MASK, clk); 557 558 udelay(10000); 559 560 #ifdef CONFIG_FSL_USDHC 561 esdhc_setbits32(®s->vendorspec, VENDORSPEC_PEREN | VENDORSPEC_CKEN); 562 #else 563 esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_CKEN); 564 #endif 565 566 } 567 568 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK 569 static void esdhc_clock_control(struct fsl_esdhc_priv *priv, bool enable) 570 { 571 struct fsl_esdhc *regs = priv->esdhc_regs; 572 u32 value; 573 u32 time_out; 574 575 value = esdhc_read32(®s->sysctl); 576 577 if (enable) 578 value |= SYSCTL_CKEN; 579 else 580 value &= ~SYSCTL_CKEN; 581 582 esdhc_write32(®s->sysctl, value); 583 584 time_out = 20; 585 value = PRSSTAT_SDSTB; 586 while (!(esdhc_read32(®s->prsstat) & value)) { 587 if (time_out == 0) { 588 printf("fsl_esdhc: Internal clock never stabilised.\n"); 589 break; 590 } 591 time_out--; 592 mdelay(1); 593 } 594 } 595 #endif 596 597 static int esdhc_set_ios_common(struct fsl_esdhc_priv *priv, struct mmc *mmc) 598 { 599 struct fsl_esdhc *regs = priv->esdhc_regs; 600 601 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK 602 /* Select to use peripheral clock */ 603 esdhc_clock_control(priv, false); 604 esdhc_setbits32(®s->scr, ESDHCCTL_PCS); 605 esdhc_clock_control(priv, true); 606 #endif 607 /* Set the clock speed */ 608 set_sysctl(priv, mmc, mmc->clock); 609 610 /* Set the bus width */ 611 esdhc_clrbits32(®s->proctl, PROCTL_DTW_4 | PROCTL_DTW_8); 612 613 if (mmc->bus_width == 4) 614 esdhc_setbits32(®s->proctl, PROCTL_DTW_4); 615 else if (mmc->bus_width == 8) 616 esdhc_setbits32(®s->proctl, PROCTL_DTW_8); 617 618 return 0; 619 } 620 621 static int esdhc_init_common(struct fsl_esdhc_priv *priv, struct mmc *mmc) 622 { 623 struct fsl_esdhc *regs = priv->esdhc_regs; 624 int timeout = 1000; 625 626 /* Reset the entire host controller */ 627 esdhc_setbits32(®s->sysctl, SYSCTL_RSTA); 628 629 /* Wait until the controller is available */ 630 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA) && --timeout) 631 udelay(1000); 632 633 #if defined(CONFIG_FSL_USDHC) 634 /* RSTA doesn't reset MMC_BOOT register, so manually reset it */ 635 esdhc_write32(®s->mmcboot, 0x0); 636 /* Reset MIX_CTRL and CLK_TUNE_CTRL_STATUS regs to 0 */ 637 esdhc_write32(®s->mixctrl, 0x0); 638 esdhc_write32(®s->clktunectrlstatus, 0x0); 639 640 /* Put VEND_SPEC to default value */ 641 esdhc_write32(®s->vendorspec, VENDORSPEC_INIT); 642 643 /* Disable DLL_CTRL delay line */ 644 esdhc_write32(®s->dllctrl, 0x0); 645 #endif 646 647 #ifndef ARCH_MXC 648 /* Enable cache snooping */ 649 esdhc_write32(®s->scr, 0x00000040); 650 #endif 651 652 #ifndef CONFIG_FSL_USDHC 653 esdhc_setbits32(®s->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN); 654 #else 655 esdhc_setbits32(®s->vendorspec, VENDORSPEC_HCKEN | VENDORSPEC_IPGEN); 656 #endif 657 658 /* Set the initial clock speed */ 659 mmc_set_clock(mmc, 400000); 660 661 /* Disable the BRR and BWR bits in IRQSTAT */ 662 esdhc_clrbits32(®s->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR); 663 664 /* Put the PROCTL reg back to the default */ 665 esdhc_write32(®s->proctl, PROCTL_INIT); 666 667 /* Set timout to the maximum value */ 668 esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16); 669 670 if (priv->vs18_enable) 671 esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT); 672 673 return 0; 674 } 675 676 static int esdhc_getcd_common(struct fsl_esdhc_priv *priv) 677 { 678 struct fsl_esdhc *regs = priv->esdhc_regs; 679 int timeout = 1000; 680 681 #ifdef CONFIG_ESDHC_DETECT_QUIRK 682 if (CONFIG_ESDHC_DETECT_QUIRK) 683 return 1; 684 #endif 685 686 #ifdef CONFIG_DM_MMC 687 if (priv->non_removable) 688 return 1; 689 #ifdef CONFIG_DM_GPIO 690 if (dm_gpio_is_valid(&priv->cd_gpio)) 691 return dm_gpio_get_value(&priv->cd_gpio); 692 #endif 693 #endif 694 695 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_CINS) && --timeout) 696 udelay(1000); 697 698 return timeout > 0; 699 } 700 701 static int esdhc_reset(struct fsl_esdhc *regs) 702 { 703 ulong start; 704 705 /* reset the controller */ 706 esdhc_setbits32(®s->sysctl, SYSCTL_RSTA); 707 708 /* hardware clears the bit when it is done */ 709 start = get_timer(0); 710 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA)) { 711 if (get_timer(start) > 100) { 712 printf("MMC/SD: Reset never completed.\n"); 713 return -ETIMEDOUT; 714 } 715 } 716 717 return 0; 718 } 719 720 static int esdhc_getcd(struct mmc *mmc) 721 { 722 struct fsl_esdhc_priv *priv = mmc->priv; 723 724 return esdhc_getcd_common(priv); 725 } 726 727 static int esdhc_init(struct mmc *mmc) 728 { 729 struct fsl_esdhc_priv *priv = mmc->priv; 730 731 return esdhc_init_common(priv, mmc); 732 } 733 734 static int esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, 735 struct mmc_data *data) 736 { 737 struct fsl_esdhc_priv *priv = mmc->priv; 738 739 return esdhc_send_cmd_common(priv, mmc, cmd, data); 740 } 741 742 static int esdhc_set_ios(struct mmc *mmc) 743 { 744 struct fsl_esdhc_priv *priv = mmc->priv; 745 746 return esdhc_set_ios_common(priv, mmc); 747 } 748 749 static const struct mmc_ops esdhc_ops = { 750 .getcd = esdhc_getcd, 751 .init = esdhc_init, 752 .send_cmd = esdhc_send_cmd, 753 .set_ios = esdhc_set_ios, 754 }; 755 756 static int fsl_esdhc_init(struct fsl_esdhc_priv *priv) 757 { 758 struct fsl_esdhc *regs; 759 struct mmc *mmc; 760 u32 caps, voltage_caps; 761 int ret; 762 763 if (!priv) 764 return -EINVAL; 765 766 regs = priv->esdhc_regs; 767 768 /* First reset the eSDHC controller */ 769 ret = esdhc_reset(regs); 770 if (ret) 771 return ret; 772 773 #ifndef CONFIG_FSL_USDHC 774 esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_HCKEN 775 | SYSCTL_IPGEN | SYSCTL_CKEN); 776 #else 777 esdhc_setbits32(®s->vendorspec, VENDORSPEC_PEREN | 778 VENDORSPEC_HCKEN | VENDORSPEC_IPGEN | VENDORSPEC_CKEN); 779 #endif 780 781 if (priv->vs18_enable) 782 esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT); 783 784 writel(SDHCI_IRQ_EN_BITS, ®s->irqstaten); 785 memset(&priv->cfg, 0, sizeof(priv->cfg)); 786 787 voltage_caps = 0; 788 caps = esdhc_read32(®s->hostcapblt); 789 790 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC135 791 caps = caps & ~(ESDHC_HOSTCAPBLT_SRS | 792 ESDHC_HOSTCAPBLT_VS18 | ESDHC_HOSTCAPBLT_VS30); 793 #endif 794 795 /* T4240 host controller capabilities register should have VS33 bit */ 796 #ifdef CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 797 caps = caps | ESDHC_HOSTCAPBLT_VS33; 798 #endif 799 800 if (caps & ESDHC_HOSTCAPBLT_VS18) 801 voltage_caps |= MMC_VDD_165_195; 802 if (caps & ESDHC_HOSTCAPBLT_VS30) 803 voltage_caps |= MMC_VDD_29_30 | MMC_VDD_30_31; 804 if (caps & ESDHC_HOSTCAPBLT_VS33) 805 voltage_caps |= MMC_VDD_32_33 | MMC_VDD_33_34; 806 807 priv->cfg.name = "FSL_SDHC"; 808 priv->cfg.ops = &esdhc_ops; 809 #ifdef CONFIG_SYS_SD_VOLTAGE 810 priv->cfg.voltages = CONFIG_SYS_SD_VOLTAGE; 811 #else 812 priv->cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34; 813 #endif 814 if ((priv->cfg.voltages & voltage_caps) == 0) { 815 printf("voltage not supported by controller\n"); 816 return -1; 817 } 818 819 if (priv->bus_width == 8) 820 priv->cfg.host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT; 821 else if (priv->bus_width == 4) 822 priv->cfg.host_caps = MMC_MODE_4BIT; 823 824 priv->cfg.host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT; 825 #ifdef CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE 826 priv->cfg.host_caps |= MMC_MODE_DDR_52MHz; 827 #endif 828 829 if (priv->bus_width > 0) { 830 if (priv->bus_width < 8) 831 priv->cfg.host_caps &= ~MMC_MODE_8BIT; 832 if (priv->bus_width < 4) 833 priv->cfg.host_caps &= ~MMC_MODE_4BIT; 834 } 835 836 if (caps & ESDHC_HOSTCAPBLT_HSS) 837 priv->cfg.host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS; 838 839 #ifdef CONFIG_ESDHC_DETECT_8_BIT_QUIRK 840 if (CONFIG_ESDHC_DETECT_8_BIT_QUIRK) 841 priv->cfg.host_caps &= ~MMC_MODE_8BIT; 842 #endif 843 844 priv->cfg.f_min = 400000; 845 priv->cfg.f_max = min(priv->sdhc_clk, (u32)52000000); 846 847 priv->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; 848 849 mmc = mmc_create(&priv->cfg, priv); 850 if (mmc == NULL) 851 return -1; 852 853 priv->mmc = mmc; 854 855 return 0; 856 } 857 858 #ifndef CONFIG_DM_MMC 859 static int fsl_esdhc_cfg_to_priv(struct fsl_esdhc_cfg *cfg, 860 struct fsl_esdhc_priv *priv) 861 { 862 if (!cfg || !priv) 863 return -EINVAL; 864 865 priv->esdhc_regs = (struct fsl_esdhc *)(unsigned long)(cfg->esdhc_base); 866 priv->bus_width = cfg->max_bus_width; 867 priv->sdhc_clk = cfg->sdhc_clk; 868 priv->wp_enable = cfg->wp_enable; 869 priv->vs18_enable = cfg->vs18_enable; 870 871 return 0; 872 }; 873 874 int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg) 875 { 876 struct fsl_esdhc_priv *priv; 877 int ret; 878 879 if (!cfg) 880 return -EINVAL; 881 882 priv = calloc(sizeof(struct fsl_esdhc_priv), 1); 883 if (!priv) 884 return -ENOMEM; 885 886 ret = fsl_esdhc_cfg_to_priv(cfg, priv); 887 if (ret) { 888 debug("%s xlate failure\n", __func__); 889 free(priv); 890 return ret; 891 } 892 893 ret = fsl_esdhc_init(priv); 894 if (ret) { 895 debug("%s init failure\n", __func__); 896 free(priv); 897 return ret; 898 } 899 900 return 0; 901 } 902 903 int fsl_esdhc_mmc_init(bd_t *bis) 904 { 905 struct fsl_esdhc_cfg *cfg; 906 907 cfg = calloc(sizeof(struct fsl_esdhc_cfg), 1); 908 cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR; 909 cfg->sdhc_clk = gd->arch.sdhc_clk; 910 return fsl_esdhc_initialize(bis, cfg); 911 } 912 #endif 913 914 #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT 915 void mmc_adapter_card_type_ident(void) 916 { 917 u8 card_id; 918 u8 value; 919 920 card_id = QIXIS_READ(present) & QIXIS_SDID_MASK; 921 gd->arch.sdhc_adapter = card_id; 922 923 switch (card_id) { 924 case QIXIS_ESDHC_ADAPTER_TYPE_EMMC45: 925 value = QIXIS_READ(brdcfg[5]); 926 value |= (QIXIS_DAT4 | QIXIS_DAT5_6_7); 927 QIXIS_WRITE(brdcfg[5], value); 928 break; 929 case QIXIS_ESDHC_ADAPTER_TYPE_SDMMC_LEGACY: 930 value = QIXIS_READ(pwr_ctl[1]); 931 value |= QIXIS_EVDD_BY_SDHC_VS; 932 QIXIS_WRITE(pwr_ctl[1], value); 933 break; 934 case QIXIS_ESDHC_ADAPTER_TYPE_EMMC44: 935 value = QIXIS_READ(brdcfg[5]); 936 value |= (QIXIS_SDCLKIN | QIXIS_SDCLKOUT); 937 QIXIS_WRITE(brdcfg[5], value); 938 break; 939 case QIXIS_ESDHC_ADAPTER_TYPE_RSV: 940 break; 941 case QIXIS_ESDHC_ADAPTER_TYPE_MMC: 942 break; 943 case QIXIS_ESDHC_ADAPTER_TYPE_SD: 944 break; 945 case QIXIS_ESDHC_NO_ADAPTER: 946 break; 947 default: 948 break; 949 } 950 } 951 #endif 952 953 #ifdef CONFIG_OF_LIBFDT 954 __weak int esdhc_status_fixup(void *blob, const char *compat) 955 { 956 #ifdef CONFIG_FSL_ESDHC_PIN_MUX 957 if (!hwconfig("esdhc")) { 958 do_fixup_by_compat(blob, compat, "status", "disabled", 959 sizeof("disabled"), 1); 960 return 1; 961 } 962 #endif 963 return 0; 964 } 965 966 void fdt_fixup_esdhc(void *blob, bd_t *bd) 967 { 968 const char *compat = "fsl,esdhc"; 969 970 if (esdhc_status_fixup(blob, compat)) 971 return; 972 973 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK 974 do_fixup_by_compat_u32(blob, compat, "peripheral-frequency", 975 gd->arch.sdhc_clk, 1); 976 #else 977 do_fixup_by_compat_u32(blob, compat, "clock-frequency", 978 gd->arch.sdhc_clk, 1); 979 #endif 980 #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT 981 do_fixup_by_compat_u32(blob, compat, "adapter-type", 982 (u32)(gd->arch.sdhc_adapter), 1); 983 #endif 984 } 985 #endif 986 987 #ifdef CONFIG_DM_MMC 988 #include <asm/arch/clock.h> 989 __weak void init_clk_usdhc(u32 index) 990 { 991 } 992 993 static int fsl_esdhc_probe(struct udevice *dev) 994 { 995 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); 996 struct fsl_esdhc_priv *priv = dev_get_priv(dev); 997 const void *fdt = gd->fdt_blob; 998 int node = dev_of_offset(dev); 999 #ifdef CONFIG_DM_REGULATOR 1000 struct udevice *vqmmc_dev; 1001 #endif 1002 fdt_addr_t addr; 1003 unsigned int val; 1004 int ret; 1005 1006 addr = devfdt_get_addr(dev); 1007 if (addr == FDT_ADDR_T_NONE) 1008 return -EINVAL; 1009 1010 priv->esdhc_regs = (struct fsl_esdhc *)addr; 1011 priv->dev = dev; 1012 1013 val = fdtdec_get_int(fdt, node, "bus-width", -1); 1014 if (val == 8) 1015 priv->bus_width = 8; 1016 else if (val == 4) 1017 priv->bus_width = 4; 1018 else 1019 priv->bus_width = 1; 1020 1021 if (fdt_get_property(fdt, node, "non-removable", NULL)) { 1022 priv->non_removable = 1; 1023 } else { 1024 priv->non_removable = 0; 1025 #ifdef CONFIG_DM_GPIO 1026 gpio_request_by_name_nodev(offset_to_ofnode(node), "cd-gpios", 1027 0, &priv->cd_gpio, GPIOD_IS_IN); 1028 #endif 1029 } 1030 1031 priv->wp_enable = 1; 1032 1033 #ifdef CONFIG_DM_GPIO 1034 ret = gpio_request_by_name_nodev(offset_to_ofnode(node), "wp-gpios", 0, 1035 &priv->wp_gpio, GPIOD_IS_IN); 1036 if (ret) 1037 priv->wp_enable = 0; 1038 #endif 1039 1040 priv->vs18_enable = 0; 1041 1042 #ifdef CONFIG_DM_REGULATOR 1043 /* 1044 * If emmc I/O has a fixed voltage at 1.8V, this must be provided, 1045 * otherwise, emmc will work abnormally. 1046 */ 1047 ret = device_get_supply_regulator(dev, "vqmmc-supply", &vqmmc_dev); 1048 if (ret) { 1049 dev_dbg(dev, "no vqmmc-supply\n"); 1050 } else { 1051 ret = regulator_set_enable(vqmmc_dev, true); 1052 if (ret) { 1053 dev_err(dev, "fail to enable vqmmc-supply\n"); 1054 return ret; 1055 } 1056 1057 if (regulator_get_value(vqmmc_dev) == 1800000) 1058 priv->vs18_enable = 1; 1059 } 1060 #endif 1061 1062 /* 1063 * TODO: 1064 * Because lack of clk driver, if SDHC clk is not enabled, 1065 * need to enable it first before this driver is invoked. 1066 * 1067 * we use MXC_ESDHC_CLK to get clk freq. 1068 * If one would like to make this function work, 1069 * the aliases should be provided in dts as this: 1070 * 1071 * aliases { 1072 * mmc0 = &usdhc1; 1073 * mmc1 = &usdhc2; 1074 * mmc2 = &usdhc3; 1075 * mmc3 = &usdhc4; 1076 * }; 1077 * Then if your board only supports mmc2 and mmc3, but we can 1078 * correctly get the seq as 2 and 3, then let mxc_get_clock 1079 * work as expected. 1080 */ 1081 1082 init_clk_usdhc(dev->seq); 1083 1084 priv->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK + dev->seq); 1085 if (priv->sdhc_clk <= 0) { 1086 dev_err(dev, "Unable to get clk for %s\n", dev->name); 1087 return -EINVAL; 1088 } 1089 1090 ret = fsl_esdhc_init(priv); 1091 if (ret) { 1092 dev_err(dev, "fsl_esdhc_init failure\n"); 1093 return ret; 1094 } 1095 1096 upriv->mmc = priv->mmc; 1097 priv->mmc->dev = dev; 1098 1099 return 0; 1100 } 1101 1102 static const struct udevice_id fsl_esdhc_ids[] = { 1103 { .compatible = "fsl,imx6ul-usdhc", }, 1104 { .compatible = "fsl,imx6sx-usdhc", }, 1105 { .compatible = "fsl,imx6sl-usdhc", }, 1106 { .compatible = "fsl,imx6q-usdhc", }, 1107 { .compatible = "fsl,imx7d-usdhc", }, 1108 { .compatible = "fsl,imx7ulp-usdhc", }, 1109 { .compatible = "fsl,esdhc", }, 1110 { /* sentinel */ } 1111 }; 1112 1113 U_BOOT_DRIVER(fsl_esdhc) = { 1114 .name = "fsl-esdhc-mmc", 1115 .id = UCLASS_MMC, 1116 .of_match = fsl_esdhc_ids, 1117 .probe = fsl_esdhc_probe, 1118 .priv_auto_alloc_size = sizeof(struct fsl_esdhc_priv), 1119 }; 1120 #endif 1121