1 /* 2 * Copyright 2007, Freescale Semiconductor, Inc 3 * Andy Fleming 4 * 5 * Based vaguely on the pxa mmc code: 6 * (C) Copyright 2003 7 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net 8 * 9 * See file CREDITS for list of people who contributed to this 10 * project. 11 * 12 * This program is free software; you can redistribute it and/or 13 * modify it under the terms of the GNU General Public License as 14 * published by the Free Software Foundation; either version 2 of 15 * the License, or (at your option) any later version. 16 * 17 * This program is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 25 * MA 02111-1307 USA 26 */ 27 28 #include <config.h> 29 #include <common.h> 30 #include <command.h> 31 #include <hwconfig.h> 32 #include <mmc.h> 33 #include <part.h> 34 #include <malloc.h> 35 #include <mmc.h> 36 #include <fsl_esdhc.h> 37 #include <fdt_support.h> 38 #include <asm/io.h> 39 40 DECLARE_GLOBAL_DATA_PTR; 41 42 struct fsl_esdhc { 43 uint dsaddr; 44 uint blkattr; 45 uint cmdarg; 46 uint xfertyp; 47 uint cmdrsp0; 48 uint cmdrsp1; 49 uint cmdrsp2; 50 uint cmdrsp3; 51 uint datport; 52 uint prsstat; 53 uint proctl; 54 uint sysctl; 55 uint irqstat; 56 uint irqstaten; 57 uint irqsigen; 58 uint autoc12err; 59 uint hostcapblt; 60 uint wml; 61 char reserved1[8]; 62 uint fevt; 63 char reserved2[168]; 64 uint hostver; 65 char reserved3[780]; 66 uint scr; 67 }; 68 69 /* Return the XFERTYP flags for a given command and data packet */ 70 uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data) 71 { 72 uint xfertyp = 0; 73 74 if (data) { 75 xfertyp |= XFERTYP_DPSEL | XFERTYP_DMAEN; 76 77 if (data->blocks > 1) { 78 xfertyp |= XFERTYP_MSBSEL; 79 xfertyp |= XFERTYP_BCEN; 80 } 81 82 if (data->flags & MMC_DATA_READ) 83 xfertyp |= XFERTYP_DTDSEL; 84 } 85 86 if (cmd->resp_type & MMC_RSP_CRC) 87 xfertyp |= XFERTYP_CCCEN; 88 if (cmd->resp_type & MMC_RSP_OPCODE) 89 xfertyp |= XFERTYP_CICEN; 90 if (cmd->resp_type & MMC_RSP_136) 91 xfertyp |= XFERTYP_RSPTYP_136; 92 else if (cmd->resp_type & MMC_RSP_BUSY) 93 xfertyp |= XFERTYP_RSPTYP_48_BUSY; 94 else if (cmd->resp_type & MMC_RSP_PRESENT) 95 xfertyp |= XFERTYP_RSPTYP_48; 96 97 return XFERTYP_CMD(cmd->cmdidx) | xfertyp; 98 } 99 100 static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data) 101 { 102 uint wml_value; 103 int timeout; 104 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; 105 struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; 106 107 wml_value = data->blocksize/4; 108 109 if (data->flags & MMC_DATA_READ) { 110 if (wml_value > 0x10) 111 wml_value = 0x10; 112 113 wml_value = 0x100000 | wml_value; 114 115 esdhc_write32(®s->dsaddr, (u32)data->dest); 116 } else { 117 if (wml_value > 0x80) 118 wml_value = 0x80; 119 if ((esdhc_read32(®s->prsstat) & PRSSTAT_WPSPL) == 0) { 120 printf("\nThe SD card is locked. Can not write to a locked card.\n\n"); 121 return TIMEOUT; 122 } 123 wml_value = wml_value << 16 | 0x10; 124 esdhc_write32(®s->dsaddr, (u32)data->src); 125 } 126 127 esdhc_write32(®s->wml, wml_value); 128 129 esdhc_write32(®s->blkattr, data->blocks << 16 | data->blocksize); 130 131 /* Calculate the timeout period for data transactions */ 132 timeout = fls(mmc->tran_speed/10) - 1; 133 timeout -= 13; 134 135 if (timeout > 14) 136 timeout = 14; 137 138 if (timeout < 0) 139 timeout = 0; 140 141 esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16); 142 143 return 0; 144 } 145 146 147 /* 148 * Sends a command out on the bus. Takes the mmc pointer, 149 * a command pointer, and an optional data pointer. 150 */ 151 static int 152 esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) 153 { 154 uint xfertyp; 155 uint irqstat; 156 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; 157 volatile struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; 158 159 esdhc_write32(®s->irqstat, -1); 160 161 sync(); 162 163 /* Wait for the bus to be idle */ 164 while ((esdhc_read32(®s->prsstat) & PRSSTAT_CICHB) || 165 (esdhc_read32(®s->prsstat) & PRSSTAT_CIDHB)) 166 ; 167 168 while (esdhc_read32(®s->prsstat) & PRSSTAT_DLA) 169 ; 170 171 /* Wait at least 8 SD clock cycles before the next command */ 172 /* 173 * Note: This is way more than 8 cycles, but 1ms seems to 174 * resolve timing issues with some cards 175 */ 176 udelay(1000); 177 178 /* Set up for a data transfer if we have one */ 179 if (data) { 180 int err; 181 182 err = esdhc_setup_data(mmc, data); 183 if(err) 184 return err; 185 } 186 187 /* Figure out the transfer arguments */ 188 xfertyp = esdhc_xfertyp(cmd, data); 189 190 /* Send the command */ 191 esdhc_write32(®s->cmdarg, cmd->cmdarg); 192 esdhc_write32(®s->xfertyp, xfertyp); 193 194 /* Wait for the command to complete */ 195 while (!(esdhc_read32(®s->irqstat) & IRQSTAT_CC)) 196 ; 197 198 irqstat = esdhc_read32(®s->irqstat); 199 esdhc_write32(®s->irqstat, irqstat); 200 201 if (irqstat & CMD_ERR) 202 return COMM_ERR; 203 204 if (irqstat & IRQSTAT_CTOE) 205 return TIMEOUT; 206 207 /* Copy the response to the response buffer */ 208 if (cmd->resp_type & MMC_RSP_136) { 209 u32 cmdrsp3, cmdrsp2, cmdrsp1, cmdrsp0; 210 211 cmdrsp3 = esdhc_read32(®s->cmdrsp3); 212 cmdrsp2 = esdhc_read32(®s->cmdrsp2); 213 cmdrsp1 = esdhc_read32(®s->cmdrsp1); 214 cmdrsp0 = esdhc_read32(®s->cmdrsp0); 215 cmd->response[0] = (cmdrsp3 << 8) | (cmdrsp2 >> 24); 216 cmd->response[1] = (cmdrsp2 << 8) | (cmdrsp1 >> 24); 217 cmd->response[2] = (cmdrsp1 << 8) | (cmdrsp0 >> 24); 218 cmd->response[3] = (cmdrsp0 << 8); 219 } else 220 cmd->response[0] = esdhc_read32(®s->cmdrsp0); 221 222 /* Wait until all of the blocks are transferred */ 223 if (data) { 224 do { 225 irqstat = esdhc_read32(®s->irqstat); 226 227 if (irqstat & DATA_ERR) 228 return COMM_ERR; 229 230 if (irqstat & IRQSTAT_DTOE) 231 return TIMEOUT; 232 } while (!(irqstat & IRQSTAT_TC) && 233 (esdhc_read32(®s->prsstat) & PRSSTAT_DLA)); 234 } 235 236 esdhc_write32(®s->irqstat, -1); 237 238 return 0; 239 } 240 241 void set_sysctl(struct mmc *mmc, uint clock) 242 { 243 int sdhc_clk = gd->sdhc_clk; 244 int div, pre_div; 245 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; 246 volatile struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; 247 uint clk; 248 249 if (clock < mmc->f_min) 250 clock = mmc->f_min; 251 252 if (sdhc_clk / 16 > clock) { 253 for (pre_div = 2; pre_div < 256; pre_div *= 2) 254 if ((sdhc_clk / pre_div) <= (clock * 16)) 255 break; 256 } else 257 pre_div = 2; 258 259 for (div = 1; div <= 16; div++) 260 if ((sdhc_clk / (div * pre_div)) <= clock) 261 break; 262 263 pre_div >>= 1; 264 div -= 1; 265 266 clk = (pre_div << 8) | (div << 4); 267 268 /* On imx the clock must be stopped before changing frequency */ 269 if (cfg->clk_enable) 270 esdhc_clrbits32(®s->sysctl, SYSCTL_CKEN); 271 272 esdhc_clrsetbits32(®s->sysctl, SYSCTL_CLOCK_MASK, clk); 273 274 udelay(10000); 275 276 clk = SYSCTL_PEREN; 277 /* On imx systems the clock must be explicitely enabled */ 278 if (cfg->clk_enable) 279 clk |= SYSCTL_CKEN; 280 281 esdhc_setbits32(®s->sysctl, clk); 282 } 283 284 static void esdhc_set_ios(struct mmc *mmc) 285 { 286 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; 287 struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; 288 289 /* Set the clock speed */ 290 set_sysctl(mmc, mmc->clock); 291 292 /* Set the bus width */ 293 esdhc_clrbits32(®s->proctl, PROCTL_DTW_4 | PROCTL_DTW_8); 294 295 if (mmc->bus_width == 4) 296 esdhc_setbits32(®s->proctl, PROCTL_DTW_4); 297 else if (mmc->bus_width == 8) 298 esdhc_setbits32(®s->proctl, PROCTL_DTW_8); 299 300 } 301 302 static int esdhc_init(struct mmc *mmc) 303 { 304 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; 305 struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; 306 int timeout = 1000; 307 int ret = 0; 308 u8 card_absent; 309 310 /* Enable cache snooping */ 311 if (cfg && !cfg->no_snoop) 312 esdhc_write32(®s->scr, 0x00000040); 313 314 /* Reset the entire host controller */ 315 esdhc_write32(®s->sysctl, SYSCTL_RSTA); 316 317 /* Wait until the controller is available */ 318 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA) && --timeout) 319 udelay(1000); 320 321 esdhc_write32(®s->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN); 322 323 /* Set the initial clock speed */ 324 set_sysctl(mmc, 400000); 325 326 /* Disable the BRR and BWR bits in IRQSTAT */ 327 esdhc_clrbits32(®s->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR); 328 329 /* Put the PROCTL reg back to the default */ 330 esdhc_write32(®s->proctl, PROCTL_INIT); 331 332 /* Set timout to the maximum value */ 333 esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16); 334 335 /* Check if there is a callback for detecting the card */ 336 if (board_mmc_getcd(&card_absent, mmc)) { 337 timeout = 1000; 338 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_CINS) && 339 --timeout) 340 udelay(1000); 341 342 if (timeout <= 0) 343 ret = NO_CARD_ERR; 344 } else { 345 if (card_absent) 346 ret = NO_CARD_ERR; 347 } 348 349 return ret; 350 } 351 352 int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg) 353 { 354 struct fsl_esdhc *regs; 355 struct mmc *mmc; 356 u32 caps; 357 358 if (!cfg) 359 return -1; 360 361 mmc = malloc(sizeof(struct mmc)); 362 363 sprintf(mmc->name, "FSL_ESDHC"); 364 regs = (struct fsl_esdhc *)cfg->esdhc_base; 365 366 mmc->priv = cfg; 367 mmc->send_cmd = esdhc_send_cmd; 368 mmc->set_ios = esdhc_set_ios; 369 mmc->init = esdhc_init; 370 371 caps = regs->hostcapblt; 372 373 if (caps & ESDHC_HOSTCAPBLT_VS18) 374 mmc->voltages |= MMC_VDD_165_195; 375 if (caps & ESDHC_HOSTCAPBLT_VS30) 376 mmc->voltages |= MMC_VDD_29_30 | MMC_VDD_30_31; 377 if (caps & ESDHC_HOSTCAPBLT_VS33) 378 mmc->voltages |= MMC_VDD_32_33 | MMC_VDD_33_34; 379 380 mmc->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT; 381 382 if (caps & ESDHC_HOSTCAPBLT_HSS) 383 mmc->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS; 384 385 mmc->f_min = 400000; 386 mmc->f_max = MIN(gd->sdhc_clk, 50000000); 387 388 mmc_register(mmc); 389 390 return 0; 391 } 392 393 int fsl_esdhc_mmc_init(bd_t *bis) 394 { 395 struct fsl_esdhc_cfg *cfg; 396 397 cfg = malloc(sizeof(struct fsl_esdhc_cfg)); 398 memset(cfg, 0, sizeof(struct fsl_esdhc_cfg)); 399 cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR; 400 return fsl_esdhc_initialize(bis, cfg); 401 } 402 403 #ifdef CONFIG_OF_LIBFDT 404 void fdt_fixup_esdhc(void *blob, bd_t *bd) 405 { 406 const char *compat = "fsl,esdhc"; 407 const char *status = "okay"; 408 409 if (!hwconfig("esdhc")) { 410 status = "disabled"; 411 goto out; 412 } 413 414 do_fixup_by_compat_u32(blob, compat, "clock-frequency", 415 gd->sdhc_clk, 1); 416 out: 417 do_fixup_by_compat(blob, compat, "status", status, 418 strlen(status) + 1, 1); 419 } 420 #endif 421