1 /* 2 * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc 3 * Andy Fleming 4 * 5 * Based vaguely on the pxa mmc code: 6 * (C) Copyright 2003 7 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net 8 * 9 * SPDX-License-Identifier: GPL-2.0+ 10 */ 11 12 #include <config.h> 13 #include <common.h> 14 #include <command.h> 15 #include <errno.h> 16 #include <hwconfig.h> 17 #include <mmc.h> 18 #include <part.h> 19 #include <power/regulator.h> 20 #include <malloc.h> 21 #include <fsl_esdhc.h> 22 #include <fdt_support.h> 23 #include <asm/io.h> 24 #include <dm.h> 25 #include <asm-generic/gpio.h> 26 27 DECLARE_GLOBAL_DATA_PTR; 28 29 #define SDHCI_IRQ_EN_BITS (IRQSTATEN_CC | IRQSTATEN_TC | \ 30 IRQSTATEN_CINT | \ 31 IRQSTATEN_CTOE | IRQSTATEN_CCE | IRQSTATEN_CEBE | \ 32 IRQSTATEN_CIE | IRQSTATEN_DTOE | IRQSTATEN_DCE | \ 33 IRQSTATEN_DEBE | IRQSTATEN_BRR | IRQSTATEN_BWR | \ 34 IRQSTATEN_DINT) 35 36 struct fsl_esdhc { 37 uint dsaddr; /* SDMA system address register */ 38 uint blkattr; /* Block attributes register */ 39 uint cmdarg; /* Command argument register */ 40 uint xfertyp; /* Transfer type register */ 41 uint cmdrsp0; /* Command response 0 register */ 42 uint cmdrsp1; /* Command response 1 register */ 43 uint cmdrsp2; /* Command response 2 register */ 44 uint cmdrsp3; /* Command response 3 register */ 45 uint datport; /* Buffer data port register */ 46 uint prsstat; /* Present state register */ 47 uint proctl; /* Protocol control register */ 48 uint sysctl; /* System Control Register */ 49 uint irqstat; /* Interrupt status register */ 50 uint irqstaten; /* Interrupt status enable register */ 51 uint irqsigen; /* Interrupt signal enable register */ 52 uint autoc12err; /* Auto CMD error status register */ 53 uint hostcapblt; /* Host controller capabilities register */ 54 uint wml; /* Watermark level register */ 55 uint mixctrl; /* For USDHC */ 56 char reserved1[4]; /* reserved */ 57 uint fevt; /* Force event register */ 58 uint admaes; /* ADMA error status register */ 59 uint adsaddr; /* ADMA system address register */ 60 char reserved2[4]; 61 uint dllctrl; 62 uint dllstat; 63 uint clktunectrlstatus; 64 char reserved3[84]; 65 uint vendorspec; 66 uint mmcboot; 67 uint vendorspec2; 68 char reserved4[48]; 69 uint hostver; /* Host controller version register */ 70 char reserved5[4]; /* reserved */ 71 uint dmaerraddr; /* DMA error address register */ 72 char reserved6[4]; /* reserved */ 73 uint dmaerrattr; /* DMA error attribute register */ 74 char reserved7[4]; /* reserved */ 75 uint hostcapblt2; /* Host controller capabilities register 2 */ 76 char reserved8[8]; /* reserved */ 77 uint tcr; /* Tuning control register */ 78 char reserved9[28]; /* reserved */ 79 uint sddirctl; /* SD direction control register */ 80 char reserved10[712];/* reserved */ 81 uint scr; /* eSDHC control register */ 82 }; 83 84 /** 85 * struct fsl_esdhc_priv 86 * 87 * @esdhc_regs: registers of the sdhc controller 88 * @sdhc_clk: Current clk of the sdhc controller 89 * @bus_width: bus width, 1bit, 4bit or 8bit 90 * @cfg: mmc config 91 * @mmc: mmc 92 * Following is used when Driver Model is enabled for MMC 93 * @dev: pointer for the device 94 * @non_removable: 0: removable; 1: non-removable 95 * @wp_enable: 1: enable checking wp; 0: no check 96 * @vs18_enable: 1: use 1.8V voltage; 0: use 3.3V 97 * @cd_gpio: gpio for card detection 98 * @wp_gpio: gpio for write protection 99 */ 100 struct fsl_esdhc_priv { 101 struct fsl_esdhc *esdhc_regs; 102 unsigned int sdhc_clk; 103 unsigned int bus_width; 104 struct mmc_config cfg; 105 struct mmc *mmc; 106 struct udevice *dev; 107 int non_removable; 108 int wp_enable; 109 int vs18_enable; 110 #ifdef CONFIG_DM_GPIO 111 struct gpio_desc cd_gpio; 112 struct gpio_desc wp_gpio; 113 #endif 114 }; 115 116 /* Return the XFERTYP flags for a given command and data packet */ 117 static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data) 118 { 119 uint xfertyp = 0; 120 121 if (data) { 122 xfertyp |= XFERTYP_DPSEL; 123 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO 124 xfertyp |= XFERTYP_DMAEN; 125 #endif 126 if (data->blocks > 1) { 127 xfertyp |= XFERTYP_MSBSEL; 128 xfertyp |= XFERTYP_BCEN; 129 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111 130 xfertyp |= XFERTYP_AC12EN; 131 #endif 132 } 133 134 if (data->flags & MMC_DATA_READ) 135 xfertyp |= XFERTYP_DTDSEL; 136 } 137 138 if (cmd->resp_type & MMC_RSP_CRC) 139 xfertyp |= XFERTYP_CCCEN; 140 if (cmd->resp_type & MMC_RSP_OPCODE) 141 xfertyp |= XFERTYP_CICEN; 142 if (cmd->resp_type & MMC_RSP_136) 143 xfertyp |= XFERTYP_RSPTYP_136; 144 else if (cmd->resp_type & MMC_RSP_BUSY) 145 xfertyp |= XFERTYP_RSPTYP_48_BUSY; 146 else if (cmd->resp_type & MMC_RSP_PRESENT) 147 xfertyp |= XFERTYP_RSPTYP_48; 148 149 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) 150 xfertyp |= XFERTYP_CMDTYP_ABORT; 151 152 return XFERTYP_CMD(cmd->cmdidx) | xfertyp; 153 } 154 155 #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO 156 /* 157 * PIO Read/Write Mode reduce the performace as DMA is not used in this mode. 158 */ 159 static void esdhc_pio_read_write(struct fsl_esdhc_priv *priv, 160 struct mmc_data *data) 161 { 162 struct fsl_esdhc *regs = priv->esdhc_regs; 163 uint blocks; 164 char *buffer; 165 uint databuf; 166 uint size; 167 uint irqstat; 168 uint timeout; 169 170 if (data->flags & MMC_DATA_READ) { 171 blocks = data->blocks; 172 buffer = data->dest; 173 while (blocks) { 174 timeout = PIO_TIMEOUT; 175 size = data->blocksize; 176 irqstat = esdhc_read32(®s->irqstat); 177 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BREN) 178 && --timeout); 179 if (timeout <= 0) { 180 printf("\nData Read Failed in PIO Mode."); 181 return; 182 } 183 while (size && (!(irqstat & IRQSTAT_TC))) { 184 udelay(100); /* Wait before last byte transfer complete */ 185 irqstat = esdhc_read32(®s->irqstat); 186 databuf = in_le32(®s->datport); 187 *((uint *)buffer) = databuf; 188 buffer += 4; 189 size -= 4; 190 } 191 blocks--; 192 } 193 } else { 194 blocks = data->blocks; 195 buffer = (char *)data->src; 196 while (blocks) { 197 timeout = PIO_TIMEOUT; 198 size = data->blocksize; 199 irqstat = esdhc_read32(®s->irqstat); 200 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BWEN) 201 && --timeout); 202 if (timeout <= 0) { 203 printf("\nData Write Failed in PIO Mode."); 204 return; 205 } 206 while (size && (!(irqstat & IRQSTAT_TC))) { 207 udelay(100); /* Wait before last byte transfer complete */ 208 databuf = *((uint *)buffer); 209 buffer += 4; 210 size -= 4; 211 irqstat = esdhc_read32(®s->irqstat); 212 out_le32(®s->datport, databuf); 213 } 214 blocks--; 215 } 216 } 217 } 218 #endif 219 220 static int esdhc_setup_data(struct fsl_esdhc_priv *priv, struct mmc *mmc, 221 struct mmc_data *data) 222 { 223 int timeout; 224 struct fsl_esdhc *regs = priv->esdhc_regs; 225 #if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) 226 dma_addr_t addr; 227 #endif 228 uint wml_value; 229 230 wml_value = data->blocksize/4; 231 232 if (data->flags & MMC_DATA_READ) { 233 if (wml_value > WML_RD_WML_MAX) 234 wml_value = WML_RD_WML_MAX_VAL; 235 236 esdhc_clrsetbits32(®s->wml, WML_RD_WML_MASK, wml_value); 237 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO 238 #if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) 239 addr = virt_to_phys((void *)(data->dest)); 240 if (upper_32_bits(addr)) 241 printf("Error found for upper 32 bits\n"); 242 else 243 esdhc_write32(®s->dsaddr, lower_32_bits(addr)); 244 #else 245 esdhc_write32(®s->dsaddr, (u32)data->dest); 246 #endif 247 #endif 248 } else { 249 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO 250 flush_dcache_range((ulong)data->src, 251 (ulong)data->src+data->blocks 252 *data->blocksize); 253 #endif 254 if (wml_value > WML_WR_WML_MAX) 255 wml_value = WML_WR_WML_MAX_VAL; 256 if (priv->wp_enable) { 257 if ((esdhc_read32(®s->prsstat) & 258 PRSSTAT_WPSPL) == 0) { 259 printf("\nThe SD card is locked. Can not write to a locked card.\n\n"); 260 return -ETIMEDOUT; 261 } 262 } 263 264 esdhc_clrsetbits32(®s->wml, WML_WR_WML_MASK, 265 wml_value << 16); 266 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO 267 #if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) 268 addr = virt_to_phys((void *)(data->src)); 269 if (upper_32_bits(addr)) 270 printf("Error found for upper 32 bits\n"); 271 else 272 esdhc_write32(®s->dsaddr, lower_32_bits(addr)); 273 #else 274 esdhc_write32(®s->dsaddr, (u32)data->src); 275 #endif 276 #endif 277 } 278 279 esdhc_write32(®s->blkattr, data->blocks << 16 | data->blocksize); 280 281 /* Calculate the timeout period for data transactions */ 282 /* 283 * 1)Timeout period = (2^(timeout+13)) SD Clock cycles 284 * 2)Timeout period should be minimum 0.250sec as per SD Card spec 285 * So, Number of SD Clock cycles for 0.25sec should be minimum 286 * (SD Clock/sec * 0.25 sec) SD Clock cycles 287 * = (mmc->clock * 1/4) SD Clock cycles 288 * As 1) >= 2) 289 * => (2^(timeout+13)) >= mmc->clock * 1/4 290 * Taking log2 both the sides 291 * => timeout + 13 >= log2(mmc->clock/4) 292 * Rounding up to next power of 2 293 * => timeout + 13 = log2(mmc->clock/4) + 1 294 * => timeout + 13 = fls(mmc->clock/4) 295 * 296 * However, the MMC spec "It is strongly recommended for hosts to 297 * implement more than 500ms timeout value even if the card 298 * indicates the 250ms maximum busy length." Even the previous 299 * value of 300ms is known to be insufficient for some cards. 300 * So, we use 301 * => timeout + 13 = fls(mmc->clock/2) 302 */ 303 timeout = fls(mmc->clock/2); 304 timeout -= 13; 305 306 if (timeout > 14) 307 timeout = 14; 308 309 if (timeout < 0) 310 timeout = 0; 311 312 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC_A001 313 if ((timeout == 4) || (timeout == 8) || (timeout == 12)) 314 timeout++; 315 #endif 316 317 #ifdef ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE 318 timeout = 0xE; 319 #endif 320 esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16); 321 322 return 0; 323 } 324 325 static void check_and_invalidate_dcache_range 326 (struct mmc_cmd *cmd, 327 struct mmc_data *data) { 328 unsigned start = 0; 329 unsigned end = 0; 330 unsigned size = roundup(ARCH_DMA_MINALIGN, 331 data->blocks*data->blocksize); 332 #if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) 333 dma_addr_t addr; 334 335 addr = virt_to_phys((void *)(data->dest)); 336 if (upper_32_bits(addr)) 337 printf("Error found for upper 32 bits\n"); 338 else 339 start = lower_32_bits(addr); 340 #else 341 start = (unsigned)data->dest; 342 #endif 343 end = start + size; 344 invalidate_dcache_range(start, end); 345 } 346 347 /* 348 * Sends a command out on the bus. Takes the mmc pointer, 349 * a command pointer, and an optional data pointer. 350 */ 351 static int 352 esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) 353 { 354 int err = 0; 355 uint xfertyp; 356 uint irqstat; 357 struct fsl_esdhc_priv *priv = mmc->priv; 358 struct fsl_esdhc *regs = priv->esdhc_regs; 359 360 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111 361 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) 362 return 0; 363 #endif 364 365 esdhc_write32(®s->irqstat, -1); 366 367 sync(); 368 369 /* Wait for the bus to be idle */ 370 while ((esdhc_read32(®s->prsstat) & PRSSTAT_CICHB) || 371 (esdhc_read32(®s->prsstat) & PRSSTAT_CIDHB)) 372 ; 373 374 while (esdhc_read32(®s->prsstat) & PRSSTAT_DLA) 375 ; 376 377 /* Wait at least 8 SD clock cycles before the next command */ 378 /* 379 * Note: This is way more than 8 cycles, but 1ms seems to 380 * resolve timing issues with some cards 381 */ 382 udelay(1000); 383 384 /* Set up for a data transfer if we have one */ 385 if (data) { 386 err = esdhc_setup_data(priv, mmc, data); 387 if(err) 388 return err; 389 390 if (data->flags & MMC_DATA_READ) 391 check_and_invalidate_dcache_range(cmd, data); 392 } 393 394 /* Figure out the transfer arguments */ 395 xfertyp = esdhc_xfertyp(cmd, data); 396 397 /* Mask all irqs */ 398 esdhc_write32(®s->irqsigen, 0); 399 400 /* Send the command */ 401 esdhc_write32(®s->cmdarg, cmd->cmdarg); 402 #if defined(CONFIG_FSL_USDHC) 403 esdhc_write32(®s->mixctrl, 404 (esdhc_read32(®s->mixctrl) & 0xFFFFFF80) | (xfertyp & 0x7F) 405 | (mmc->ddr_mode ? XFERTYP_DDREN : 0)); 406 esdhc_write32(®s->xfertyp, xfertyp & 0xFFFF0000); 407 #else 408 esdhc_write32(®s->xfertyp, xfertyp); 409 #endif 410 411 /* Wait for the command to complete */ 412 while (!(esdhc_read32(®s->irqstat) & (IRQSTAT_CC | IRQSTAT_CTOE))) 413 ; 414 415 irqstat = esdhc_read32(®s->irqstat); 416 417 if (irqstat & CMD_ERR) { 418 err = -ECOMM; 419 goto out; 420 } 421 422 if (irqstat & IRQSTAT_CTOE) { 423 err = -ETIMEDOUT; 424 goto out; 425 } 426 427 /* Switch voltage to 1.8V if CMD11 succeeded */ 428 if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V) { 429 esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT); 430 431 printf("Run CMD11 1.8V switch\n"); 432 /* Sleep for 5 ms - max time for card to switch to 1.8V */ 433 udelay(5000); 434 } 435 436 /* Workaround for ESDHC errata ENGcm03648 */ 437 if (!data && (cmd->resp_type & MMC_RSP_BUSY)) { 438 int timeout = 6000; 439 440 /* Poll on DATA0 line for cmd with busy signal for 600 ms */ 441 while (timeout > 0 && !(esdhc_read32(®s->prsstat) & 442 PRSSTAT_DAT0)) { 443 udelay(100); 444 timeout--; 445 } 446 447 if (timeout <= 0) { 448 printf("Timeout waiting for DAT0 to go high!\n"); 449 err = -ETIMEDOUT; 450 goto out; 451 } 452 } 453 454 /* Copy the response to the response buffer */ 455 if (cmd->resp_type & MMC_RSP_136) { 456 u32 cmdrsp3, cmdrsp2, cmdrsp1, cmdrsp0; 457 458 cmdrsp3 = esdhc_read32(®s->cmdrsp3); 459 cmdrsp2 = esdhc_read32(®s->cmdrsp2); 460 cmdrsp1 = esdhc_read32(®s->cmdrsp1); 461 cmdrsp0 = esdhc_read32(®s->cmdrsp0); 462 cmd->response[0] = (cmdrsp3 << 8) | (cmdrsp2 >> 24); 463 cmd->response[1] = (cmdrsp2 << 8) | (cmdrsp1 >> 24); 464 cmd->response[2] = (cmdrsp1 << 8) | (cmdrsp0 >> 24); 465 cmd->response[3] = (cmdrsp0 << 8); 466 } else 467 cmd->response[0] = esdhc_read32(®s->cmdrsp0); 468 469 /* Wait until all of the blocks are transferred */ 470 if (data) { 471 #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO 472 esdhc_pio_read_write(priv, data); 473 #else 474 do { 475 irqstat = esdhc_read32(®s->irqstat); 476 477 if (irqstat & IRQSTAT_DTOE) { 478 err = -ETIMEDOUT; 479 goto out; 480 } 481 482 if (irqstat & DATA_ERR) { 483 err = -ECOMM; 484 goto out; 485 } 486 } while ((irqstat & DATA_COMPLETE) != DATA_COMPLETE); 487 488 /* 489 * Need invalidate the dcache here again to avoid any 490 * cache-fill during the DMA operations such as the 491 * speculative pre-fetching etc. 492 */ 493 if (data->flags & MMC_DATA_READ) 494 check_and_invalidate_dcache_range(cmd, data); 495 #endif 496 } 497 498 out: 499 /* Reset CMD and DATA portions on error */ 500 if (err) { 501 esdhc_write32(®s->sysctl, esdhc_read32(®s->sysctl) | 502 SYSCTL_RSTC); 503 while (esdhc_read32(®s->sysctl) & SYSCTL_RSTC) 504 ; 505 506 if (data) { 507 esdhc_write32(®s->sysctl, 508 esdhc_read32(®s->sysctl) | 509 SYSCTL_RSTD); 510 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTD)) 511 ; 512 } 513 514 /* If this was CMD11, then notify that power cycle is needed */ 515 if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V) 516 printf("CMD11 to switch to 1.8V mode failed, card requires power cycle.\n"); 517 } 518 519 esdhc_write32(®s->irqstat, -1); 520 521 return err; 522 } 523 524 static void set_sysctl(struct fsl_esdhc_priv *priv, struct mmc *mmc, uint clock) 525 { 526 int div = 1; 527 #ifdef ARCH_MXC 528 int pre_div = 1; 529 #else 530 int pre_div = 2; 531 #endif 532 int ddr_pre_div = mmc->ddr_mode ? 2 : 1; 533 struct fsl_esdhc *regs = priv->esdhc_regs; 534 int sdhc_clk = priv->sdhc_clk; 535 uint clk; 536 537 if (clock < mmc->cfg->f_min) 538 clock = mmc->cfg->f_min; 539 540 while (sdhc_clk / (16 * pre_div * ddr_pre_div) > clock && pre_div < 256) 541 pre_div *= 2; 542 543 while (sdhc_clk / (div * pre_div * ddr_pre_div) > clock && div < 16) 544 div++; 545 546 pre_div >>= 1; 547 div -= 1; 548 549 clk = (pre_div << 8) | (div << 4); 550 551 #ifdef CONFIG_FSL_USDHC 552 esdhc_clrbits32(®s->vendorspec, VENDORSPEC_CKEN); 553 #else 554 esdhc_clrbits32(®s->sysctl, SYSCTL_CKEN); 555 #endif 556 557 esdhc_clrsetbits32(®s->sysctl, SYSCTL_CLOCK_MASK, clk); 558 559 udelay(10000); 560 561 #ifdef CONFIG_FSL_USDHC 562 esdhc_setbits32(®s->vendorspec, VENDORSPEC_PEREN | VENDORSPEC_CKEN); 563 #else 564 esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_CKEN); 565 #endif 566 567 } 568 569 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK 570 static void esdhc_clock_control(struct fsl_esdhc_priv *priv, bool enable) 571 { 572 struct fsl_esdhc *regs = priv->esdhc_regs; 573 u32 value; 574 u32 time_out; 575 576 value = esdhc_read32(®s->sysctl); 577 578 if (enable) 579 value |= SYSCTL_CKEN; 580 else 581 value &= ~SYSCTL_CKEN; 582 583 esdhc_write32(®s->sysctl, value); 584 585 time_out = 20; 586 value = PRSSTAT_SDSTB; 587 while (!(esdhc_read32(®s->prsstat) & value)) { 588 if (time_out == 0) { 589 printf("fsl_esdhc: Internal clock never stabilised.\n"); 590 break; 591 } 592 time_out--; 593 mdelay(1); 594 } 595 } 596 #endif 597 598 static int esdhc_set_ios(struct mmc *mmc) 599 { 600 struct fsl_esdhc_priv *priv = mmc->priv; 601 struct fsl_esdhc *regs = priv->esdhc_regs; 602 603 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK 604 /* Select to use peripheral clock */ 605 esdhc_clock_control(priv, false); 606 esdhc_setbits32(®s->scr, ESDHCCTL_PCS); 607 esdhc_clock_control(priv, true); 608 #endif 609 /* Set the clock speed */ 610 set_sysctl(priv, mmc, mmc->clock); 611 612 /* Set the bus width */ 613 esdhc_clrbits32(®s->proctl, PROCTL_DTW_4 | PROCTL_DTW_8); 614 615 if (mmc->bus_width == 4) 616 esdhc_setbits32(®s->proctl, PROCTL_DTW_4); 617 else if (mmc->bus_width == 8) 618 esdhc_setbits32(®s->proctl, PROCTL_DTW_8); 619 620 return 0; 621 } 622 623 static int esdhc_init(struct mmc *mmc) 624 { 625 struct fsl_esdhc_priv *priv = mmc->priv; 626 struct fsl_esdhc *regs = priv->esdhc_regs; 627 int timeout = 1000; 628 629 /* Reset the entire host controller */ 630 esdhc_setbits32(®s->sysctl, SYSCTL_RSTA); 631 632 /* Wait until the controller is available */ 633 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA) && --timeout) 634 udelay(1000); 635 636 #if defined(CONFIG_FSL_USDHC) 637 /* RSTA doesn't reset MMC_BOOT register, so manually reset it */ 638 esdhc_write32(®s->mmcboot, 0x0); 639 /* Reset MIX_CTRL and CLK_TUNE_CTRL_STATUS regs to 0 */ 640 esdhc_write32(®s->mixctrl, 0x0); 641 esdhc_write32(®s->clktunectrlstatus, 0x0); 642 643 /* Put VEND_SPEC to default value */ 644 esdhc_write32(®s->vendorspec, VENDORSPEC_INIT); 645 646 /* Disable DLL_CTRL delay line */ 647 esdhc_write32(®s->dllctrl, 0x0); 648 #endif 649 650 #ifndef ARCH_MXC 651 /* Enable cache snooping */ 652 esdhc_write32(®s->scr, 0x00000040); 653 #endif 654 655 #ifndef CONFIG_FSL_USDHC 656 esdhc_setbits32(®s->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN); 657 #else 658 esdhc_setbits32(®s->vendorspec, VENDORSPEC_HCKEN | VENDORSPEC_IPGEN); 659 #endif 660 661 /* Set the initial clock speed */ 662 mmc_set_clock(mmc, 400000); 663 664 /* Disable the BRR and BWR bits in IRQSTAT */ 665 esdhc_clrbits32(®s->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR); 666 667 /* Put the PROCTL reg back to the default */ 668 esdhc_write32(®s->proctl, PROCTL_INIT); 669 670 /* Set timout to the maximum value */ 671 esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16); 672 673 if (priv->vs18_enable) 674 esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT); 675 676 return 0; 677 } 678 679 static int esdhc_getcd(struct mmc *mmc) 680 { 681 struct fsl_esdhc_priv *priv = mmc->priv; 682 struct fsl_esdhc *regs = priv->esdhc_regs; 683 int timeout = 1000; 684 685 #ifdef CONFIG_ESDHC_DETECT_QUIRK 686 if (CONFIG_ESDHC_DETECT_QUIRK) 687 return 1; 688 #endif 689 690 #ifdef CONFIG_DM_MMC 691 if (priv->non_removable) 692 return 1; 693 #ifdef CONFIG_DM_GPIO 694 if (dm_gpio_is_valid(&priv->cd_gpio)) 695 return dm_gpio_get_value(&priv->cd_gpio); 696 #endif 697 #endif 698 699 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_CINS) && --timeout) 700 udelay(1000); 701 702 return timeout > 0; 703 } 704 705 static void esdhc_reset(struct fsl_esdhc *regs) 706 { 707 unsigned long timeout = 100; /* wait max 100 ms */ 708 709 /* reset the controller */ 710 esdhc_setbits32(®s->sysctl, SYSCTL_RSTA); 711 712 /* hardware clears the bit when it is done */ 713 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA) && --timeout) 714 udelay(1000); 715 if (!timeout) 716 printf("MMC/SD: Reset never completed.\n"); 717 } 718 719 static const struct mmc_ops esdhc_ops = { 720 .send_cmd = esdhc_send_cmd, 721 .set_ios = esdhc_set_ios, 722 .init = esdhc_init, 723 .getcd = esdhc_getcd, 724 }; 725 726 static int fsl_esdhc_init(struct fsl_esdhc_priv *priv) 727 { 728 struct fsl_esdhc *regs; 729 struct mmc *mmc; 730 u32 caps, voltage_caps; 731 732 if (!priv) 733 return -EINVAL; 734 735 regs = priv->esdhc_regs; 736 737 /* First reset the eSDHC controller */ 738 esdhc_reset(regs); 739 740 #ifndef CONFIG_FSL_USDHC 741 esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_HCKEN 742 | SYSCTL_IPGEN | SYSCTL_CKEN); 743 #else 744 esdhc_setbits32(®s->vendorspec, VENDORSPEC_PEREN | 745 VENDORSPEC_HCKEN | VENDORSPEC_IPGEN | VENDORSPEC_CKEN); 746 #endif 747 748 if (priv->vs18_enable) 749 esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT); 750 751 writel(SDHCI_IRQ_EN_BITS, ®s->irqstaten); 752 memset(&priv->cfg, 0, sizeof(priv->cfg)); 753 754 voltage_caps = 0; 755 caps = esdhc_read32(®s->hostcapblt); 756 757 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC135 758 caps = caps & ~(ESDHC_HOSTCAPBLT_SRS | 759 ESDHC_HOSTCAPBLT_VS18 | ESDHC_HOSTCAPBLT_VS30); 760 #endif 761 762 /* T4240 host controller capabilities register should have VS33 bit */ 763 #ifdef CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 764 caps = caps | ESDHC_HOSTCAPBLT_VS33; 765 #endif 766 767 if (caps & ESDHC_HOSTCAPBLT_VS18) 768 voltage_caps |= MMC_VDD_165_195; 769 if (caps & ESDHC_HOSTCAPBLT_VS30) 770 voltage_caps |= MMC_VDD_29_30 | MMC_VDD_30_31; 771 if (caps & ESDHC_HOSTCAPBLT_VS33) 772 voltage_caps |= MMC_VDD_32_33 | MMC_VDD_33_34; 773 774 priv->cfg.name = "FSL_SDHC"; 775 priv->cfg.ops = &esdhc_ops; 776 #ifdef CONFIG_SYS_SD_VOLTAGE 777 priv->cfg.voltages = CONFIG_SYS_SD_VOLTAGE; 778 #else 779 priv->cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34; 780 #endif 781 if ((priv->cfg.voltages & voltage_caps) == 0) { 782 printf("voltage not supported by controller\n"); 783 return -1; 784 } 785 786 if (priv->bus_width == 8) 787 priv->cfg.host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT; 788 else if (priv->bus_width == 4) 789 priv->cfg.host_caps = MMC_MODE_4BIT; 790 791 priv->cfg.host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT; 792 #ifdef CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE 793 priv->cfg.host_caps |= MMC_MODE_DDR_52MHz; 794 #endif 795 796 if (priv->bus_width > 0) { 797 if (priv->bus_width < 8) 798 priv->cfg.host_caps &= ~MMC_MODE_8BIT; 799 if (priv->bus_width < 4) 800 priv->cfg.host_caps &= ~MMC_MODE_4BIT; 801 } 802 803 if (caps & ESDHC_HOSTCAPBLT_HSS) 804 priv->cfg.host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS; 805 806 #ifdef CONFIG_ESDHC_DETECT_8_BIT_QUIRK 807 if (CONFIG_ESDHC_DETECT_8_BIT_QUIRK) 808 priv->cfg.host_caps &= ~MMC_MODE_8BIT; 809 #endif 810 811 priv->cfg.f_min = 400000; 812 priv->cfg.f_max = min(priv->sdhc_clk, (u32)52000000); 813 814 priv->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; 815 816 mmc = mmc_create(&priv->cfg, priv); 817 if (mmc == NULL) 818 return -1; 819 820 priv->mmc = mmc; 821 822 return 0; 823 } 824 825 #ifndef CONFIG_DM_MMC 826 static int fsl_esdhc_cfg_to_priv(struct fsl_esdhc_cfg *cfg, 827 struct fsl_esdhc_priv *priv) 828 { 829 if (!cfg || !priv) 830 return -EINVAL; 831 832 priv->esdhc_regs = (struct fsl_esdhc *)(unsigned long)(cfg->esdhc_base); 833 priv->bus_width = cfg->max_bus_width; 834 priv->sdhc_clk = cfg->sdhc_clk; 835 priv->wp_enable = cfg->wp_enable; 836 priv->vs18_enable = cfg->vs18_enable; 837 838 return 0; 839 }; 840 841 int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg) 842 { 843 struct fsl_esdhc_priv *priv; 844 int ret; 845 846 if (!cfg) 847 return -EINVAL; 848 849 priv = calloc(sizeof(struct fsl_esdhc_priv), 1); 850 if (!priv) 851 return -ENOMEM; 852 853 ret = fsl_esdhc_cfg_to_priv(cfg, priv); 854 if (ret) { 855 debug("%s xlate failure\n", __func__); 856 free(priv); 857 return ret; 858 } 859 860 ret = fsl_esdhc_init(priv); 861 if (ret) { 862 debug("%s init failure\n", __func__); 863 free(priv); 864 return ret; 865 } 866 867 return 0; 868 } 869 870 int fsl_esdhc_mmc_init(bd_t *bis) 871 { 872 struct fsl_esdhc_cfg *cfg; 873 874 cfg = calloc(sizeof(struct fsl_esdhc_cfg), 1); 875 cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR; 876 cfg->sdhc_clk = gd->arch.sdhc_clk; 877 return fsl_esdhc_initialize(bis, cfg); 878 } 879 #endif 880 881 #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT 882 void mmc_adapter_card_type_ident(void) 883 { 884 u8 card_id; 885 u8 value; 886 887 card_id = QIXIS_READ(present) & QIXIS_SDID_MASK; 888 gd->arch.sdhc_adapter = card_id; 889 890 switch (card_id) { 891 case QIXIS_ESDHC_ADAPTER_TYPE_EMMC45: 892 value = QIXIS_READ(brdcfg[5]); 893 value |= (QIXIS_DAT4 | QIXIS_DAT5_6_7); 894 QIXIS_WRITE(brdcfg[5], value); 895 break; 896 case QIXIS_ESDHC_ADAPTER_TYPE_SDMMC_LEGACY: 897 value = QIXIS_READ(pwr_ctl[1]); 898 value |= QIXIS_EVDD_BY_SDHC_VS; 899 QIXIS_WRITE(pwr_ctl[1], value); 900 break; 901 case QIXIS_ESDHC_ADAPTER_TYPE_EMMC44: 902 value = QIXIS_READ(brdcfg[5]); 903 value |= (QIXIS_SDCLKIN | QIXIS_SDCLKOUT); 904 QIXIS_WRITE(brdcfg[5], value); 905 break; 906 case QIXIS_ESDHC_ADAPTER_TYPE_RSV: 907 break; 908 case QIXIS_ESDHC_ADAPTER_TYPE_MMC: 909 break; 910 case QIXIS_ESDHC_ADAPTER_TYPE_SD: 911 break; 912 case QIXIS_ESDHC_NO_ADAPTER: 913 break; 914 default: 915 break; 916 } 917 } 918 #endif 919 920 #ifdef CONFIG_OF_LIBFDT 921 __weak int esdhc_status_fixup(void *blob, const char *compat) 922 { 923 #ifdef CONFIG_FSL_ESDHC_PIN_MUX 924 if (!hwconfig("esdhc")) { 925 do_fixup_by_compat(blob, compat, "status", "disabled", 926 sizeof("disabled"), 1); 927 return 1; 928 } 929 #endif 930 return 0; 931 } 932 933 void fdt_fixup_esdhc(void *blob, bd_t *bd) 934 { 935 const char *compat = "fsl,esdhc"; 936 937 if (esdhc_status_fixup(blob, compat)) 938 return; 939 940 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK 941 do_fixup_by_compat_u32(blob, compat, "peripheral-frequency", 942 gd->arch.sdhc_clk, 1); 943 #else 944 do_fixup_by_compat_u32(blob, compat, "clock-frequency", 945 gd->arch.sdhc_clk, 1); 946 #endif 947 #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT 948 do_fixup_by_compat_u32(blob, compat, "adapter-type", 949 (u32)(gd->arch.sdhc_adapter), 1); 950 #endif 951 } 952 #endif 953 954 #ifdef CONFIG_DM_MMC 955 #include <asm/arch/clock.h> 956 __weak void init_clk_usdhc(u32 index) 957 { 958 } 959 960 static int fsl_esdhc_probe(struct udevice *dev) 961 { 962 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); 963 struct fsl_esdhc_priv *priv = dev_get_priv(dev); 964 const void *fdt = gd->fdt_blob; 965 int node = dev_of_offset(dev); 966 #ifdef CONFIG_DM_REGULATOR 967 struct udevice *vqmmc_dev; 968 #endif 969 fdt_addr_t addr; 970 unsigned int val; 971 int ret; 972 973 addr = devfdt_get_addr(dev); 974 if (addr == FDT_ADDR_T_NONE) 975 return -EINVAL; 976 977 priv->esdhc_regs = (struct fsl_esdhc *)addr; 978 priv->dev = dev; 979 980 val = fdtdec_get_int(fdt, node, "bus-width", -1); 981 if (val == 8) 982 priv->bus_width = 8; 983 else if (val == 4) 984 priv->bus_width = 4; 985 else 986 priv->bus_width = 1; 987 988 if (fdt_get_property(fdt, node, "non-removable", NULL)) { 989 priv->non_removable = 1; 990 } else { 991 priv->non_removable = 0; 992 #ifdef CONFIG_DM_GPIO 993 gpio_request_by_name_nodev(offset_to_ofnode(node), "cd-gpios", 994 0, &priv->cd_gpio, GPIOD_IS_IN); 995 #endif 996 } 997 998 priv->wp_enable = 1; 999 1000 #ifdef CONFIG_DM_GPIO 1001 ret = gpio_request_by_name_nodev(offset_to_ofnode(node), "wp-gpios", 0, 1002 &priv->wp_gpio, GPIOD_IS_IN); 1003 if (ret) 1004 priv->wp_enable = 0; 1005 #endif 1006 1007 priv->vs18_enable = 0; 1008 1009 #ifdef CONFIG_DM_REGULATOR 1010 /* 1011 * If emmc I/O has a fixed voltage at 1.8V, this must be provided, 1012 * otherwise, emmc will work abnormally. 1013 */ 1014 ret = device_get_supply_regulator(dev, "vqmmc-supply", &vqmmc_dev); 1015 if (ret) { 1016 dev_dbg(dev, "no vqmmc-supply\n"); 1017 } else { 1018 ret = regulator_set_enable(vqmmc_dev, true); 1019 if (ret) { 1020 dev_err(dev, "fail to enable vqmmc-supply\n"); 1021 return ret; 1022 } 1023 1024 if (regulator_get_value(vqmmc_dev) == 1800000) 1025 priv->vs18_enable = 1; 1026 } 1027 #endif 1028 1029 /* 1030 * TODO: 1031 * Because lack of clk driver, if SDHC clk is not enabled, 1032 * need to enable it first before this driver is invoked. 1033 * 1034 * we use MXC_ESDHC_CLK to get clk freq. 1035 * If one would like to make this function work, 1036 * the aliases should be provided in dts as this: 1037 * 1038 * aliases { 1039 * mmc0 = &usdhc1; 1040 * mmc1 = &usdhc2; 1041 * mmc2 = &usdhc3; 1042 * mmc3 = &usdhc4; 1043 * }; 1044 * Then if your board only supports mmc2 and mmc3, but we can 1045 * correctly get the seq as 2 and 3, then let mxc_get_clock 1046 * work as expected. 1047 */ 1048 1049 init_clk_usdhc(dev->seq); 1050 1051 priv->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK + dev->seq); 1052 if (priv->sdhc_clk <= 0) { 1053 dev_err(dev, "Unable to get clk for %s\n", dev->name); 1054 return -EINVAL; 1055 } 1056 1057 ret = fsl_esdhc_init(priv); 1058 if (ret) { 1059 dev_err(dev, "fsl_esdhc_init failure\n"); 1060 return ret; 1061 } 1062 1063 upriv->mmc = priv->mmc; 1064 priv->mmc->dev = dev; 1065 1066 return 0; 1067 } 1068 1069 static const struct udevice_id fsl_esdhc_ids[] = { 1070 { .compatible = "fsl,imx6ul-usdhc", }, 1071 { .compatible = "fsl,imx6sx-usdhc", }, 1072 { .compatible = "fsl,imx6sl-usdhc", }, 1073 { .compatible = "fsl,imx6q-usdhc", }, 1074 { .compatible = "fsl,imx7d-usdhc", }, 1075 { .compatible = "fsl,imx7ulp-usdhc", }, 1076 { .compatible = "fsl,esdhc", }, 1077 { /* sentinel */ } 1078 }; 1079 1080 U_BOOT_DRIVER(fsl_esdhc) = { 1081 .name = "fsl-esdhc-mmc", 1082 .id = UCLASS_MMC, 1083 .of_match = fsl_esdhc_ids, 1084 .probe = fsl_esdhc_probe, 1085 .priv_auto_alloc_size = sizeof(struct fsl_esdhc_priv), 1086 }; 1087 #endif 1088