1 /* 2 * (C) Copyright 2012 SAMSUNG Electronics 3 * Jaehoon Chung <jh80.chung@samsung.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <dwmmc.h> 10 #include <fdtdec.h> 11 #include <libfdt.h> 12 #include <malloc.h> 13 #include <asm/arch/dwmmc.h> 14 #include <asm/arch/clk.h> 15 #include <asm/arch/pinmux.h> 16 #include <asm/arch/power.h> 17 #include <asm/gpio.h> 18 #include <asm-generic/errno.h> 19 20 #define DWMMC_MAX_CH_NUM 4 21 #define DWMMC_MAX_FREQ 52000000 22 #define DWMMC_MIN_FREQ 400000 23 #define DWMMC_MMC0_SDR_TIMING_VAL 0x03030001 24 #define DWMMC_MMC2_SDR_TIMING_VAL 0x03020001 25 26 /* Exynos implmentation specific drver private data */ 27 struct dwmci_exynos_priv_data { 28 u32 sdr_timing; 29 }; 30 31 /* 32 * Function used as callback function to initialise the 33 * CLKSEL register for every mmc channel. 34 */ 35 static void exynos_dwmci_clksel(struct dwmci_host *host) 36 { 37 struct dwmci_exynos_priv_data *priv = host->priv; 38 39 dwmci_writel(host, DWMCI_CLKSEL, priv->sdr_timing); 40 } 41 42 unsigned int exynos_dwmci_get_clk(struct dwmci_host *host, uint freq) 43 { 44 unsigned long sclk; 45 int8_t clk_div; 46 47 /* 48 * Since SDCLKIN is divided inside controller by the DIVRATIO 49 * value set in the CLKSEL register, we need to use the same output 50 * clock value to calculate the CLKDIV value. 51 * as per user manual:cclk_in = SDCLKIN / (DIVRATIO + 1) 52 */ 53 clk_div = ((dwmci_readl(host, DWMCI_CLKSEL) >> DWMCI_DIVRATIO_BIT) 54 & DWMCI_DIVRATIO_MASK) + 1; 55 sclk = get_mmc_clk(host->dev_index); 56 57 /* 58 * Assume to know divider value. 59 * When clock unit is broken, need to set "host->div" 60 */ 61 return sclk / clk_div / (host->div + 1); 62 } 63 64 static void exynos_dwmci_board_init(struct dwmci_host *host) 65 { 66 struct dwmci_exynos_priv_data *priv = host->priv; 67 68 if (host->quirks & DWMCI_QUIRK_DISABLE_SMU) { 69 dwmci_writel(host, EMMCP_MPSBEGIN0, 0); 70 dwmci_writel(host, EMMCP_SEND0, 0); 71 dwmci_writel(host, EMMCP_CTRL0, 72 MPSCTRL_SECURE_READ_BIT | 73 MPSCTRL_SECURE_WRITE_BIT | 74 MPSCTRL_NON_SECURE_READ_BIT | 75 MPSCTRL_NON_SECURE_WRITE_BIT | MPSCTRL_VALID); 76 } 77 78 /* Set to timing value at initial time */ 79 if (priv->sdr_timing) 80 exynos_dwmci_clksel(host); 81 } 82 83 static int exynos_dwmci_core_init(struct dwmci_host *host) 84 { 85 unsigned int div; 86 unsigned long freq, sclk; 87 88 if (host->bus_hz) 89 freq = host->bus_hz; 90 else 91 freq = DWMMC_MAX_FREQ; 92 93 /* request mmc clock vlaue of 52MHz. */ 94 sclk = get_mmc_clk(host->dev_index); 95 div = DIV_ROUND_UP(sclk, freq); 96 /* set the clock divisor for mmc */ 97 set_mmc_clk(host->dev_index, div); 98 99 host->name = "EXYNOS DWMMC"; 100 #ifdef CONFIG_EXYNOS5420 101 host->quirks = DWMCI_QUIRK_DISABLE_SMU; 102 #endif 103 host->board_init = exynos_dwmci_board_init; 104 105 host->caps = MMC_MODE_DDR_52MHz; 106 host->clksel = exynos_dwmci_clksel; 107 host->get_mmc_clk = exynos_dwmci_get_clk; 108 /* Add the mmc channel to be registered with mmc core */ 109 if (add_dwmci(host, DWMMC_MAX_FREQ, DWMMC_MIN_FREQ)) { 110 printf("DWMMC%d registration failed\n", host->dev_index); 111 return -1; 112 } 113 return 0; 114 } 115 116 static struct dwmci_host dwmci_host[DWMMC_MAX_CH_NUM]; 117 118 static int do_dwmci_init(struct dwmci_host *host) 119 { 120 int flag, err; 121 122 flag = host->buswidth == 8 ? PINMUX_FLAG_8BIT_MODE : PINMUX_FLAG_NONE; 123 err = exynos_pinmux_config(host->dev_id, flag); 124 if (err) { 125 printf("DWMMC%d not configure\n", host->dev_index); 126 return err; 127 } 128 129 return exynos_dwmci_core_init(host); 130 } 131 132 static int exynos_dwmci_get_config(const void *blob, int node, 133 struct dwmci_host *host) 134 { 135 int err = 0; 136 u32 base, timing[3]; 137 struct dwmci_exynos_priv_data *priv; 138 139 priv = malloc(sizeof(struct dwmci_exynos_priv_data)); 140 if (!priv) { 141 error("dwmci_exynos_priv_data malloc fail!\n"); 142 return -ENOMEM; 143 } 144 145 /* Extract device id for each mmc channel */ 146 host->dev_id = pinmux_decode_periph_id(blob, node); 147 148 host->dev_index = fdtdec_get_int(blob, node, "index", host->dev_id); 149 if (host->dev_index == host->dev_id) 150 host->dev_index = host->dev_id - PERIPH_ID_SDMMC0; 151 152 if (host->dev_index > 4) { 153 printf("DWMMC%d: Can't get the dev index\n", host->dev_index); 154 return -EINVAL; 155 } 156 157 /* Get the bus width from the device node (Default is 4bit buswidth) */ 158 host->buswidth = fdtdec_get_int(blob, node, "samsung,bus-width", 4); 159 160 /* Set the base address from the device node */ 161 base = fdtdec_get_addr(blob, node, "reg"); 162 if (!base) { 163 printf("DWMMC%d: Can't get base address\n", host->dev_index); 164 return -EINVAL; 165 } 166 host->ioaddr = (void *)base; 167 168 /* Extract the timing info from the node */ 169 err = fdtdec_get_int_array(blob, node, "samsung,timing", timing, 3); 170 if (err) { 171 printf("DWMMC%d: Can't get sdr-timings for devider\n", 172 host->dev_index); 173 return -EINVAL; 174 } 175 176 priv->sdr_timing = (DWMCI_SET_SAMPLE_CLK(timing[0]) | 177 DWMCI_SET_DRV_CLK(timing[1]) | 178 DWMCI_SET_DIV_RATIO(timing[2])); 179 180 /* sdr_timing didn't assigned anything, use the default value */ 181 if (!priv->sdr_timing) { 182 if (host->dev_index == 0) 183 priv->sdr_timing = DWMMC_MMC0_SDR_TIMING_VAL; 184 else if (host->dev_index == 2) 185 priv->sdr_timing = DWMMC_MMC2_SDR_TIMING_VAL; 186 } 187 188 host->fifoth_val = fdtdec_get_int(blob, node, "fifoth_val", 0); 189 host->bus_hz = fdtdec_get_int(blob, node, "bus_hz", 0); 190 host->div = fdtdec_get_int(blob, node, "div", 0); 191 192 host->priv = priv; 193 194 return 0; 195 } 196 197 static int exynos_dwmci_process_node(const void *blob, 198 int node_list[], int count) 199 { 200 struct dwmci_host *host; 201 int i, node, err; 202 203 for (i = 0; i < count; i++) { 204 node = node_list[i]; 205 if (node <= 0) 206 continue; 207 host = &dwmci_host[i]; 208 err = exynos_dwmci_get_config(blob, node, host); 209 if (err) { 210 printf("%s: failed to decode dev %d\n", __func__, i); 211 return err; 212 } 213 214 do_dwmci_init(host); 215 } 216 return 0; 217 } 218 219 int exynos_dwmmc_init(const void *blob) 220 { 221 int node_list[DWMMC_MAX_CH_NUM]; 222 int boot_dev_node; 223 int err = 0, count; 224 225 count = fdtdec_find_aliases_for_id(blob, "mmc", 226 COMPAT_SAMSUNG_EXYNOS_DWMMC, node_list, 227 DWMMC_MAX_CH_NUM); 228 229 /* For DWMMC always set boot device as mmc 0 */ 230 if (count >= 3 && get_boot_mode() == BOOT_MODE_SD) { 231 boot_dev_node = node_list[2]; 232 node_list[2] = node_list[0]; 233 node_list[0] = boot_dev_node; 234 } 235 236 err = exynos_dwmci_process_node(blob, node_list, count); 237 238 return err; 239 } 240