1 /* 2 * (C) Copyright 2012 SAMSUNG Electronics 3 * Jaehoon Chung <jh80.chung@samsung.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <dwmmc.h> 10 #include <fdtdec.h> 11 #include <libfdt.h> 12 #include <malloc.h> 13 #include <asm/arch/dwmmc.h> 14 #include <asm/arch/clk.h> 15 #include <asm/arch/pinmux.h> 16 #include <asm/gpio.h> 17 #include <asm-generic/errno.h> 18 19 #define DWMMC_MAX_CH_NUM 4 20 #define DWMMC_MAX_FREQ 52000000 21 #define DWMMC_MIN_FREQ 400000 22 #define DWMMC_MMC0_SDR_TIMING_VAL 0x03030001 23 #define DWMMC_MMC2_SDR_TIMING_VAL 0x03020001 24 25 /* Exynos implmentation specific drver private data */ 26 struct dwmci_exynos_priv_data { 27 u32 sdr_timing; 28 }; 29 30 /* 31 * Function used as callback function to initialise the 32 * CLKSEL register for every mmc channel. 33 */ 34 static void exynos_dwmci_clksel(struct dwmci_host *host) 35 { 36 struct dwmci_exynos_priv_data *priv = host->priv; 37 38 dwmci_writel(host, DWMCI_CLKSEL, priv->sdr_timing); 39 } 40 41 unsigned int exynos_dwmci_get_clk(struct dwmci_host *host) 42 { 43 unsigned long sclk; 44 int8_t clk_div; 45 46 /* 47 * Since SDCLKIN is divided inside controller by the DIVRATIO 48 * value set in the CLKSEL register, we need to use the same output 49 * clock value to calculate the CLKDIV value. 50 * as per user manual:cclk_in = SDCLKIN / (DIVRATIO + 1) 51 */ 52 clk_div = ((dwmci_readl(host, DWMCI_CLKSEL) >> DWMCI_DIVRATIO_BIT) 53 & DWMCI_DIVRATIO_MASK) + 1; 54 sclk = get_mmc_clk(host->dev_index); 55 56 /* 57 * Assume to know divider value. 58 * When clock unit is broken, need to set "host->div" 59 */ 60 return sclk / clk_div / (host->div + 1); 61 } 62 63 static void exynos_dwmci_board_init(struct dwmci_host *host) 64 { 65 struct dwmci_exynos_priv_data *priv = host->priv; 66 67 if (host->quirks & DWMCI_QUIRK_DISABLE_SMU) { 68 dwmci_writel(host, EMMCP_MPSBEGIN0, 0); 69 dwmci_writel(host, EMMCP_SEND0, 0); 70 dwmci_writel(host, EMMCP_CTRL0, 71 MPSCTRL_SECURE_READ_BIT | 72 MPSCTRL_SECURE_WRITE_BIT | 73 MPSCTRL_NON_SECURE_READ_BIT | 74 MPSCTRL_NON_SECURE_WRITE_BIT | MPSCTRL_VALID); 75 } 76 77 /* Set to timing value at initial time */ 78 if (priv->sdr_timing) 79 exynos_dwmci_clksel(host); 80 } 81 82 static int exynos_dwmci_core_init(struct dwmci_host *host, int index) 83 { 84 unsigned int div; 85 unsigned long freq, sclk; 86 struct dwmci_exynos_priv_data *priv = host->priv; 87 88 if (host->bus_hz) 89 freq = host->bus_hz; 90 else 91 freq = DWMMC_MAX_FREQ; 92 93 /* request mmc clock vlaue of 52MHz. */ 94 sclk = get_mmc_clk(index); 95 div = DIV_ROUND_UP(sclk, freq); 96 /* set the clock divisor for mmc */ 97 set_mmc_clk(index, div); 98 99 host->name = "EXYNOS DWMMC"; 100 #ifdef CONFIG_EXYNOS5420 101 host->quirks = DWMCI_QUIRK_DISABLE_SMU; 102 #endif 103 host->board_init = exynos_dwmci_board_init; 104 105 if (!priv->sdr_timing) { 106 if (index == 0) 107 priv->sdr_timing = DWMMC_MMC0_SDR_TIMING_VAL; 108 else if (index == 2) 109 priv->sdr_timing = DWMMC_MMC2_SDR_TIMING_VAL; 110 } 111 112 host->caps = MMC_MODE_DDR_52MHz; 113 host->clksel = exynos_dwmci_clksel; 114 host->dev_index = index; 115 host->get_mmc_clk = exynos_dwmci_get_clk; 116 /* Add the mmc channel to be registered with mmc core */ 117 if (add_dwmci(host, DWMMC_MAX_FREQ, DWMMC_MIN_FREQ)) { 118 printf("DWMMC%d registration failed\n", index); 119 return -1; 120 } 121 return 0; 122 } 123 124 /* 125 * This function adds the mmc channel to be registered with mmc core. 126 * index - mmc channel number. 127 * regbase - register base address of mmc channel specified in 'index'. 128 * bus_width - operating bus width of mmc channel specified in 'index'. 129 * clksel - value to be written into CLKSEL register in case of FDT. 130 * NULL in case od non-FDT. 131 */ 132 int exynos_dwmci_add_port(int index, u32 regbase, int bus_width, u32 clksel) 133 { 134 struct dwmci_host *host = NULL; 135 struct dwmci_exynos_priv_data *priv; 136 137 host = malloc(sizeof(struct dwmci_host)); 138 if (!host) { 139 error("dwmci_host malloc fail!\n"); 140 return -ENOMEM; 141 } 142 143 priv = malloc(sizeof(struct dwmci_exynos_priv_data)); 144 if (!priv) { 145 error("dwmci_exynos_priv_data malloc fail!\n"); 146 return -ENOMEM; 147 } 148 149 host->ioaddr = (void *)regbase; 150 host->buswidth = bus_width; 151 152 if (clksel) 153 priv->sdr_timing = clksel; 154 155 host->priv = priv; 156 157 return exynos_dwmci_core_init(host, index); 158 } 159 160 #ifdef CONFIG_OF_CONTROL 161 static struct dwmci_host dwmci_host[DWMMC_MAX_CH_NUM]; 162 163 static int do_dwmci_init(struct dwmci_host *host) 164 { 165 int index, flag, err; 166 167 index = host->dev_index; 168 169 flag = host->buswidth == 8 ? PINMUX_FLAG_8BIT_MODE : PINMUX_FLAG_NONE; 170 err = exynos_pinmux_config(host->dev_id, flag); 171 if (err) { 172 printf("DWMMC%d not configure\n", index); 173 return err; 174 } 175 176 return exynos_dwmci_core_init(host, index); 177 } 178 179 static int exynos_dwmci_get_config(const void *blob, int node, 180 struct dwmci_host *host) 181 { 182 int err = 0; 183 u32 base, timing[3]; 184 struct dwmci_exynos_priv_data *priv; 185 186 priv = malloc(sizeof(struct dwmci_exynos_priv_data)); 187 if (!priv) { 188 error("dwmci_exynos_priv_data malloc fail!\n"); 189 return -ENOMEM; 190 } 191 192 /* Extract device id for each mmc channel */ 193 host->dev_id = pinmux_decode_periph_id(blob, node); 194 195 host->dev_index = fdtdec_get_int(blob, node, "index", host->dev_id); 196 if (host->dev_index == host->dev_id) 197 host->dev_index = host->dev_id - PERIPH_ID_SDMMC0; 198 199 200 /* Get the bus width from the device node */ 201 host->buswidth = fdtdec_get_int(blob, node, "samsung,bus-width", 0); 202 if (host->buswidth <= 0) { 203 printf("DWMMC%d: Can't get bus-width\n", host->dev_index); 204 return -EINVAL; 205 } 206 207 /* Set the base address from the device node */ 208 base = fdtdec_get_addr(blob, node, "reg"); 209 if (!base) { 210 printf("DWMMC%d: Can't get base address\n", host->dev_index); 211 return -EINVAL; 212 } 213 host->ioaddr = (void *)base; 214 215 /* Extract the timing info from the node */ 216 err = fdtdec_get_int_array(blob, node, "samsung,timing", timing, 3); 217 if (err) { 218 printf("DWMMC%d: Can't get sdr-timings for devider\n", 219 host->dev_index); 220 return -EINVAL; 221 } 222 223 priv->sdr_timing = (DWMCI_SET_SAMPLE_CLK(timing[0]) | 224 DWMCI_SET_DRV_CLK(timing[1]) | 225 DWMCI_SET_DIV_RATIO(timing[2])); 226 227 /* sdr_timing didn't assigned anything, use the default value */ 228 if (!priv->sdr_timing) { 229 if (host->dev_index == 0) 230 priv->sdr_timing = DWMMC_MMC0_SDR_TIMING_VAL; 231 else if (host->dev_index == 2) 232 priv->sdr_timing = DWMMC_MMC2_SDR_TIMING_VAL; 233 } 234 235 host->fifoth_val = fdtdec_get_int(blob, node, "fifoth_val", 0); 236 host->bus_hz = fdtdec_get_int(blob, node, "bus_hz", 0); 237 host->div = fdtdec_get_int(blob, node, "div", 0); 238 239 host->priv = priv; 240 241 return 0; 242 } 243 244 static int exynos_dwmci_process_node(const void *blob, 245 int node_list[], int count) 246 { 247 struct dwmci_host *host; 248 int i, node, err; 249 250 for (i = 0; i < count; i++) { 251 node = node_list[i]; 252 if (node <= 0) 253 continue; 254 host = &dwmci_host[i]; 255 err = exynos_dwmci_get_config(blob, node, host); 256 if (err) { 257 printf("%s: failed to decode dev %d\n", __func__, i); 258 return err; 259 } 260 261 do_dwmci_init(host); 262 } 263 return 0; 264 } 265 266 int exynos_dwmmc_init(const void *blob) 267 { 268 int compat_id; 269 int node_list[DWMMC_MAX_CH_NUM]; 270 int err = 0, count; 271 272 compat_id = COMPAT_SAMSUNG_EXYNOS_DWMMC; 273 274 count = fdtdec_find_aliases_for_id(blob, "mmc", 275 compat_id, node_list, DWMMC_MAX_CH_NUM); 276 err = exynos_dwmci_process_node(blob, node_list, count); 277 278 return err; 279 } 280 #endif 281