1 /* 2 * This code was extracted from: 3 * git://github.com/gonzoua/u-boot-pi.git master 4 * and hence presumably (C) 2012 Oleksandr Tymoshenko 5 * 6 * Tweaks for U-Boot upstreaming 7 * (C) 2012 Stephen Warren 8 * 9 * Portions (e.g. read/write macros, concepts for back-to-back register write 10 * timing workarounds) obviously extracted from the Linux kernel at: 11 * https://github.com/raspberrypi/linux.git rpi-3.6.y 12 * 13 * The Linux kernel code has the following (c) and license, which is hence 14 * propagated to Oleksandr's tree and here: 15 * 16 * Support for SDHCI device on 2835 17 * Based on sdhci-bcm2708.c (c) 2010 Broadcom 18 * 19 * This program is free software; you can redistribute it and/or modify 20 * it under the terms of the GNU General Public License version 2 as 21 * published by the Free Software Foundation. 22 * 23 * This program is distributed in the hope that it will be useful, 24 * but WITHOUT ANY WARRANTY; without even the implied warranty of 25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 26 * GNU General Public License for more details. 27 * 28 * You should have received a copy of the GNU General Public License 29 * along with this program; if not, write to the Free Software 30 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 31 */ 32 33 /* Supports: 34 * SDHCI platform device - Arasan SD controller in BCM2708 35 * 36 * Inspired by sdhci-pci.c, by Pierre Ossman 37 */ 38 39 #include <common.h> 40 #include <dm.h> 41 #include <malloc.h> 42 #include <memalign.h> 43 #include <sdhci.h> 44 #include <asm/arch/msg.h> 45 #include <asm/arch/mbox.h> 46 #include <mach/sdhci.h> 47 #include <mach/timer.h> 48 49 /* 400KHz is max freq for card ID etc. Use that as min */ 50 #define MIN_FREQ 400000 51 #define SDHCI_BUFFER 0x20 52 53 struct bcm2835_sdhci_host { 54 struct sdhci_host host; 55 uint twoticks_delay; 56 ulong last_write; 57 }; 58 59 static inline struct bcm2835_sdhci_host *to_bcm(struct sdhci_host *host) 60 { 61 return (struct bcm2835_sdhci_host *)host; 62 } 63 64 static inline void bcm2835_sdhci_raw_writel(struct sdhci_host *host, u32 val, 65 int reg) 66 { 67 struct bcm2835_sdhci_host *bcm_host = to_bcm(host); 68 69 /* 70 * The Arasan has a bugette whereby it may lose the content of 71 * successive writes to registers that are within two SD-card clock 72 * cycles of each other (a clock domain crossing problem). 73 * It seems, however, that the data register does not have this problem. 74 * (Which is just as well - otherwise we'd have to nobble the DMA engine 75 * too) 76 */ 77 if (reg != SDHCI_BUFFER) { 78 while (timer_get_us() - bcm_host->last_write < bcm_host->twoticks_delay) 79 ; 80 } 81 82 writel(val, host->ioaddr + reg); 83 bcm_host->last_write = timer_get_us(); 84 } 85 86 static inline u32 bcm2835_sdhci_raw_readl(struct sdhci_host *host, int reg) 87 { 88 return readl(host->ioaddr + reg); 89 } 90 91 static void bcm2835_sdhci_writel(struct sdhci_host *host, u32 val, int reg) 92 { 93 bcm2835_sdhci_raw_writel(host, val, reg); 94 } 95 96 static void bcm2835_sdhci_writew(struct sdhci_host *host, u16 val, int reg) 97 { 98 static u32 shadow; 99 u32 oldval = (reg == SDHCI_COMMAND) ? shadow : 100 bcm2835_sdhci_raw_readl(host, reg & ~3); 101 u32 word_num = (reg >> 1) & 1; 102 u32 word_shift = word_num * 16; 103 u32 mask = 0xffff << word_shift; 104 u32 newval = (oldval & ~mask) | (val << word_shift); 105 106 if (reg == SDHCI_TRANSFER_MODE) 107 shadow = newval; 108 else 109 bcm2835_sdhci_raw_writel(host, newval, reg & ~3); 110 } 111 112 static void bcm2835_sdhci_writeb(struct sdhci_host *host, u8 val, int reg) 113 { 114 u32 oldval = bcm2835_sdhci_raw_readl(host, reg & ~3); 115 u32 byte_num = reg & 3; 116 u32 byte_shift = byte_num * 8; 117 u32 mask = 0xff << byte_shift; 118 u32 newval = (oldval & ~mask) | (val << byte_shift); 119 120 bcm2835_sdhci_raw_writel(host, newval, reg & ~3); 121 } 122 123 static u32 bcm2835_sdhci_readl(struct sdhci_host *host, int reg) 124 { 125 u32 val = bcm2835_sdhci_raw_readl(host, reg); 126 127 return val; 128 } 129 130 static u16 bcm2835_sdhci_readw(struct sdhci_host *host, int reg) 131 { 132 u32 val = bcm2835_sdhci_raw_readl(host, (reg & ~3)); 133 u32 word_num = (reg >> 1) & 1; 134 u32 word_shift = word_num * 16; 135 u32 word = (val >> word_shift) & 0xffff; 136 137 return word; 138 } 139 140 static u8 bcm2835_sdhci_readb(struct sdhci_host *host, int reg) 141 { 142 u32 val = bcm2835_sdhci_raw_readl(host, (reg & ~3)); 143 u32 byte_num = reg & 3; 144 u32 byte_shift = byte_num * 8; 145 u32 byte = (val >> byte_shift) & 0xff; 146 147 return byte; 148 } 149 150 static const struct sdhci_ops bcm2835_ops = { 151 .write_l = bcm2835_sdhci_writel, 152 .write_w = bcm2835_sdhci_writew, 153 .write_b = bcm2835_sdhci_writeb, 154 .read_l = bcm2835_sdhci_readl, 155 .read_w = bcm2835_sdhci_readw, 156 .read_b = bcm2835_sdhci_readb, 157 }; 158 159 static int bcm2835_sdhci_bind(struct udevice *dev) 160 { 161 struct bcm2835_sdhci_plat *plat = dev_get_platdata(dev); 162 163 return sdhci_bind(dev, &plat->mmc, &plat->cfg); 164 } 165 166 static int bcm2835_sdhci_probe(struct udevice *dev) 167 { 168 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); 169 struct bcm2835_sdhci_plat *plat = dev_get_platdata(dev); 170 struct bcm2835_sdhci_host *priv = dev_get_priv(dev); 171 struct sdhci_host *host = &priv->host; 172 fdt_addr_t base; 173 int emmc_freq; 174 int ret; 175 176 base = devfdt_get_addr(dev); 177 if (base == FDT_ADDR_T_NONE) 178 return -EINVAL; 179 180 ret = bcm2835_get_mmc_clock(); 181 if (ret < 0) { 182 debug("%s: Failed to set MMC clock (err=%d)\n", __func__, ret); 183 return ret; 184 } 185 emmc_freq = ret; 186 187 /* 188 * See the comments in bcm2835_sdhci_raw_writel(). 189 * 190 * This should probably be dynamically calculated based on the actual 191 * frequency. However, this is the longest we'll have to wait, and 192 * doesn't seem to slow access down too much, so the added complexity 193 * doesn't seem worth it for now. 194 * 195 * 1/MIN_FREQ is (max) time per tick of eMMC clock. 196 * 2/MIN_FREQ is time for two ticks. 197 * Multiply by 1000000 to get uS per two ticks. 198 * +1 for hack rounding. 199 */ 200 priv->twoticks_delay = ((2 * 1000000) / MIN_FREQ) + 1; 201 priv->last_write = 0; 202 203 host->name = dev->name; 204 host->ioaddr = (void *)base; 205 host->quirks = SDHCI_QUIRK_BROKEN_VOLTAGE | SDHCI_QUIRK_BROKEN_R1B | 206 SDHCI_QUIRK_WAIT_SEND_CMD | SDHCI_QUIRK_NO_HISPD_BIT; 207 host->max_clk = emmc_freq; 208 host->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; 209 host->ops = &bcm2835_ops; 210 211 ret = sdhci_setup_cfg(&plat->cfg, host, emmc_freq, MIN_FREQ); 212 if (ret) { 213 debug("%s: Failed to setup SDHCI (err=%d)\n", __func__, ret); 214 return ret; 215 } 216 217 upriv->mmc = &plat->mmc; 218 host->mmc = &plat->mmc; 219 host->mmc->priv = host; 220 221 return sdhci_probe(dev); 222 } 223 224 static const struct udevice_id bcm2835_sdhci_match[] = { 225 { .compatible = "brcm,bcm2835-sdhci" }, 226 { /* sentinel */ } 227 }; 228 229 U_BOOT_DRIVER(sdhci_cdns) = { 230 .name = "sdhci-bcm2835", 231 .id = UCLASS_MMC, 232 .of_match = bcm2835_sdhci_match, 233 .bind = bcm2835_sdhci_bind, 234 .probe = bcm2835_sdhci_probe, 235 .priv_auto_alloc_size = sizeof(struct bcm2835_sdhci_host), 236 .platdata_auto_alloc_size = sizeof(struct bcm2835_sdhci_plat), 237 .ops = &sdhci_ops, 238 }; 239