1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) 2019 Rockchip Electronics Co., Ltd 4 */ 5 #include <common.h> 6 #include <asm/io.h> 7 #include <clk.h> 8 #include <dm.h> 9 #include <linux/bitops.h> 10 #include <misc.h> 11 #include <irq-generic.h> 12 #include <reset.h> 13 14 DECLARE_GLOBAL_DATA_PTR; 15 16 #define DECOM_CTRL 0x0 17 #define DECOM_ENR 0x4 18 #define DECOM_RADDR 0x8 19 #define DECOM_WADDR 0xc 20 #define DECOM_UDDSL 0x10 21 #define DECOM_UDDSH 0x14 22 #define DECOM_TXTHR 0x18 23 #define DECOM_RXTHR 0x1c 24 #define DECOM_SLEN 0x20 25 #define DECOM_STAT 0x24 26 #define DECOM_ISR 0x28 27 #define DECOM_IEN 0x2c 28 #define DECOM_AXI_STAT 0x30 29 #define DECOM_TSIZEL 0x34 30 #define DECOM_TSIZEH 0x38 31 #define DECOM_MGNUM 0x3c 32 #define DECOM_FRAME 0x40 33 #define DECOM_DICTID 0x44 34 #define DECOM_CSL 0x48 35 #define DECOM_CSH 0x4c 36 #define DECOM_LMTSL 0x50 37 #define DECOM_LMTSH 0x54 38 39 #define LZ4_HEAD_CSUM_CHECK_EN BIT(1) 40 #define LZ4_BLOCK_CSUM_CHECK_EN BIT(2) 41 #define LZ4_CONT_CSUM_CHECK_EN BIT(3) 42 43 #define DSOLIEN BIT(19) 44 #define ZDICTEIEN BIT(18) 45 #define GCMEIEN BIT(17) 46 #define GIDEIEN BIT(16) 47 #define CCCEIEN BIT(15) 48 #define BCCEIEN BIT(14) 49 #define HCCEIEN BIT(13) 50 #define CSEIEN BIT(12) 51 #define DICTEIEN BIT(11) 52 #define VNEIEN BIT(10) 53 #define WNEIEN BIT(9) 54 #define RDCEIEN BIT(8) 55 #define WRCEIEN BIT(7) 56 #define DISEIEN BIT(6) 57 #define LENEIEN BIT(5) 58 #define LITEIEN BIT(4) 59 #define SQMEIEN BIT(3) 60 #define SLCIEN BIT(2) 61 #define HDEIEN BIT(1) 62 #define DSIEN BIT(0) 63 64 #define DECOM_STOP BIT(0) 65 #define DECOM_COMPLETE BIT(0) 66 #define DECOM_GZIP_MODE BIT(4) 67 #define DECOM_ZLIB_MODE BIT(5) 68 #define DECOM_DEFLATE_MODE BIT(0) 69 #define DECOM_AXI_IDLE BIT(4) 70 #define DECOM_LZ4_MODE 0 71 72 #define DECOM_ENABLE 0x1 73 #define DECOM_DISABLE 0x0 74 75 #define DECOM_IRQ 0xffff /* fixme */ 76 77 #define DECOM_INT_MASK \ 78 (DSOLIEN | ZDICTEIEN | GCMEIEN | GIDEIEN | \ 79 CCCEIEN | BCCEIEN | HCCEIEN | CSEIEN | \ 80 DICTEIEN | VNEIEN | WNEIEN | RDCEIEN | WRCEIEN | \ 81 DISEIEN | LENEIEN | LITEIEN | SQMEIEN | SLCIEN | \ 82 HDEIEN | DSIEN) 83 84 #define DCLK_DECOM 400 * 1000 * 1000 85 86 struct rockchip_decom_priv { 87 struct reset_ctl rst; 88 void __iomem *base; 89 bool idle_check_once; 90 bool done; 91 struct clk dclk; 92 int cached; /* 1: access the data through dcache; 0: no dcache */ 93 }; 94 95 static int rockchip_decom_start(struct udevice *dev, void *buf) 96 { 97 struct rockchip_decom_priv *priv = dev_get_priv(dev); 98 struct decom_param *param = (struct decom_param *)buf; 99 unsigned int limit_lo = param->size_dst & 0xffffffff; 100 unsigned int limit_hi = param->size_dst >> 32; 101 102 #if CONFIG_IS_ENABLED(DM_RESET) 103 reset_assert(&priv->rst); 104 udelay(10); 105 reset_deassert(&priv->rst); 106 #endif 107 /* 108 * Purpose: 109 * src: clean dcache to get the real compressed data from ddr. 110 * dst: invalidate dcache. 111 * 112 * flush_dcache_all() operating on set/way is faster than 113 * flush_cache() and invalidate_dcache_range() operating 114 * on virtual address. 115 */ 116 if (!priv->cached) 117 flush_dcache_all(); 118 119 priv->done = false; 120 121 if (param->mode == DECOM_LZ4) 122 writel(LZ4_CONT_CSUM_CHECK_EN | 123 LZ4_HEAD_CSUM_CHECK_EN | 124 LZ4_BLOCK_CSUM_CHECK_EN | 125 DECOM_LZ4_MODE, 126 priv->base + DECOM_CTRL); 127 else if (param->mode == DECOM_GZIP) 128 writel(DECOM_DEFLATE_MODE | DECOM_GZIP_MODE, 129 priv->base + DECOM_CTRL); 130 else if (param->mode == DECOM_ZLIB) 131 writel(DECOM_DEFLATE_MODE | DECOM_ZLIB_MODE, 132 priv->base + DECOM_CTRL); 133 134 writel(param->addr_src, priv->base + DECOM_RADDR); 135 writel(param->addr_dst, priv->base + DECOM_WADDR); 136 137 writel(limit_lo, priv->base + DECOM_LMTSL); 138 writel(limit_hi, priv->base + DECOM_LMTSH); 139 140 #if defined(CONFIG_SPL_BUILD) 141 writel(DECOM_INT_MASK, priv->base + DECOM_IEN); 142 #endif 143 writel(DECOM_ENABLE, priv->base + DECOM_ENR); 144 145 priv->idle_check_once = true; 146 147 return 0; 148 } 149 150 static int rockchip_decom_stop(struct udevice *dev) 151 { 152 struct rockchip_decom_priv *priv = dev_get_priv(dev); 153 154 writel(DECOM_DISABLE, priv->base + DECOM_ENR); 155 156 return 0; 157 } 158 159 /* Caller must call this function to check if decompress done */ 160 static int rockchip_decom_done_poll(struct udevice *dev) 161 { 162 struct rockchip_decom_priv *priv = dev_get_priv(dev); 163 164 /* 165 * Test the decom is idle first time. 166 */ 167 if (!priv->idle_check_once) 168 return !(readl(priv->base + DECOM_AXI_STAT) & DECOM_AXI_IDLE); 169 170 return !(readl(priv->base + DECOM_STAT) & DECOM_COMPLETE); 171 } 172 173 static int rockchip_decom_capability(u32 *buf) 174 { 175 *buf = DECOM_GZIP; 176 177 return 0; 178 } 179 180 static int rockchip_decom_data_size(struct udevice *dev, u64 *buf) 181 { 182 struct rockchip_decom_priv *priv = dev_get_priv(dev); 183 struct decom_param *param = (struct decom_param *)buf; 184 u32 sizel, sizeh; 185 186 sizel = readl(priv->base + DECOM_TSIZEL); 187 sizeh = readl(priv->base + DECOM_TSIZEH); 188 param->size_dst = sizel | ((u64)sizeh << 32); 189 190 return 0; 191 } 192 193 /* Caller must fill in param @buf which represent struct decom_param */ 194 static int rockchip_decom_ioctl(struct udevice *dev, unsigned long request, 195 void *buf) 196 { 197 int ret = -EINVAL; 198 199 switch (request) { 200 case IOCTL_REQ_START: 201 ret = rockchip_decom_start(dev, buf); 202 break; 203 case IOCTL_REQ_POLL: 204 ret = rockchip_decom_done_poll(dev); 205 break; 206 case IOCTL_REQ_STOP: 207 ret = rockchip_decom_stop(dev); 208 break; 209 case IOCTL_REQ_CAPABILITY: 210 ret = rockchip_decom_capability(buf); 211 break; 212 case IOCTL_REQ_DATA_SIZE: 213 ret = rockchip_decom_data_size(dev, buf); 214 break; 215 default: 216 printf("Unsupported ioctl: %ld\n", (ulong)request); 217 break; 218 } 219 220 return ret; 221 } 222 223 static const struct misc_ops rockchip_decom_ops = { 224 .ioctl = rockchip_decom_ioctl, 225 }; 226 227 static int rockchip_decom_ofdata_to_platdata(struct udevice *dev) 228 { 229 struct rockchip_decom_priv *priv = dev_get_priv(dev); 230 231 priv->base = dev_read_addr_ptr(dev); 232 if (!priv->base) 233 return -ENOENT; 234 235 priv->cached = dev_read_u32_default(dev, "data-cached", 0); 236 237 return 0; 238 } 239 240 static int rockchip_decom_probe(struct udevice *dev) 241 { 242 #if CONFIG_IS_ENABLED(DM_RESET) 243 struct rockchip_decom_priv *priv = dev_get_priv(dev); 244 int ret; 245 246 ret = reset_get_by_name(dev, "dresetn", &priv->rst); 247 if (ret) { 248 debug("reset_get_by_name() failed: %d\n", ret); 249 return ret; 250 } 251 #endif 252 253 ret = clk_get_by_name(dev, "dclk", &priv->dclk); 254 if (ret < 0) 255 return ret; 256 257 ret = clk_set_rate(&priv->dclk, DCLK_DECOM); 258 if (ret < 0) 259 return ret; 260 261 return 0; 262 } 263 264 static const struct udevice_id rockchip_decom_ids[] = { 265 { .compatible = "rockchip,hw-decompress" }, 266 {} 267 }; 268 269 U_BOOT_DRIVER(rockchip_hw_decompress) = { 270 .name = "rockchip_hw_decompress", 271 .id = UCLASS_MISC, 272 .of_match = rockchip_decom_ids, 273 .probe = rockchip_decom_probe, 274 .ofdata_to_platdata = rockchip_decom_ofdata_to_platdata, 275 .priv_auto_alloc_size = sizeof(struct rockchip_decom_priv), 276 .ops = &rockchip_decom_ops, 277 }; 278