1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) 2019 Rockchip Electronics Co., Ltd 4 */ 5 #include <common.h> 6 #include <asm/io.h> 7 #include <clk.h> 8 #include <dm.h> 9 #include <linux/bitops.h> 10 #include <misc.h> 11 #include <irq-generic.h> 12 #include <reset.h> 13 14 DECLARE_GLOBAL_DATA_PTR; 15 16 #define DECOM_CTRL 0x0 17 #define DECOM_ENR 0x4 18 #define DECOM_RADDR 0x8 19 #define DECOM_WADDR 0xc 20 #define DECOM_UDDSL 0x10 21 #define DECOM_UDDSH 0x14 22 #define DECOM_TXTHR 0x18 23 #define DECOM_RXTHR 0x1c 24 #define DECOM_SLEN 0x20 25 #define DECOM_STAT 0x24 26 #define DECOM_ISR 0x28 27 #define DECOM_IEN 0x2c 28 #define DECOM_AXI_STAT 0x30 29 #define DECOM_TSIZEL 0x34 30 #define DECOM_TSIZEH 0x38 31 #define DECOM_MGNUM 0x3c 32 #define DECOM_FRAME 0x40 33 #define DECOM_DICTID 0x44 34 #define DECOM_CSL 0x48 35 #define DECOM_CSH 0x4c 36 #define DECOM_LMTSL 0x50 37 #define DECOM_LMTSH 0x54 38 39 #define LZ4_HEAD_CSUM_CHECK_EN BIT(1) 40 #define LZ4_BLOCK_CSUM_CHECK_EN BIT(2) 41 #define LZ4_CONT_CSUM_CHECK_EN BIT(3) 42 43 #define DSOLIEN BIT(19) 44 #define ZDICTEIEN BIT(18) 45 #define GCMEIEN BIT(17) 46 #define GIDEIEN BIT(16) 47 #define CCCEIEN BIT(15) 48 #define BCCEIEN BIT(14) 49 #define HCCEIEN BIT(13) 50 #define CSEIEN BIT(12) 51 #define DICTEIEN BIT(11) 52 #define VNEIEN BIT(10) 53 #define WNEIEN BIT(9) 54 #define RDCEIEN BIT(8) 55 #define WRCEIEN BIT(7) 56 #define DISEIEN BIT(6) 57 #define LENEIEN BIT(5) 58 #define LITEIEN BIT(4) 59 #define SQMEIEN BIT(3) 60 #define SLCIEN BIT(2) 61 #define HDEIEN BIT(1) 62 #define DSIEN BIT(0) 63 64 #define DECOM_STOP BIT(0) 65 #define DECOM_COMPLETE BIT(0) 66 #define DECOM_GZIP_MODE BIT(4) 67 #define DECOM_ZLIB_MODE BIT(5) 68 #define DECOM_DEFLATE_MODE BIT(0) 69 #define DECOM_AXI_IDLE BIT(4) 70 #define DECOM_LZ4_MODE 0 71 72 #define DECOM_ENABLE 0x1 73 #define DECOM_DISABLE 0x0 74 75 #define DECOM_IRQ 0xffff /* fixme */ 76 77 #define DECOM_INT_MASK \ 78 (DSOLIEN | ZDICTEIEN | GCMEIEN | GIDEIEN | \ 79 CCCEIEN | BCCEIEN | HCCEIEN | CSEIEN | \ 80 DICTEIEN | VNEIEN | WNEIEN | RDCEIEN | WRCEIEN | \ 81 DISEIEN | LENEIEN | LITEIEN | SQMEIEN | SLCIEN | \ 82 HDEIEN | DSIEN) 83 84 #define DCLK_DECOM 400 * 1000 * 1000 85 86 struct rockchip_decom_priv { 87 struct reset_ctl rst; 88 void __iomem *base; 89 bool idle_check_once; 90 bool done; 91 struct clk dclk; 92 int cached; /* 1: access the data through dcache; 0: no dcache */ 93 }; 94 95 static int rockchip_decom_start(struct udevice *dev, void *buf) 96 { 97 struct rockchip_decom_priv *priv = dev_get_priv(dev); 98 struct decom_param *param = (struct decom_param *)buf; 99 unsigned int limit_lo = param->size_dst & 0xffffffff; 100 unsigned int limit_hi = param->size_dst >> 32; 101 u32 irq_status; 102 103 #if CONFIG_IS_ENABLED(DM_RESET) 104 reset_assert(&priv->rst); 105 udelay(10); 106 reset_deassert(&priv->rst); 107 #endif 108 /* 109 * Purpose: 110 * src: clean dcache to get the real compressed data from ddr. 111 * dst: invalidate dcache. 112 * 113 * flush_dcache_all() operating on set/way is faster than 114 * flush_cache() and invalidate_dcache_range() operating 115 * on virtual address. 116 */ 117 if (!priv->cached) 118 flush_dcache_all(); 119 120 priv->done = false; 121 122 irq_status = readl(priv->base + DECOM_ISR); 123 /* clear interrupts */ 124 if (irq_status) 125 writel(irq_status, priv->base + DECOM_ISR); 126 127 if (param->mode == DECOM_LZ4) 128 writel(LZ4_CONT_CSUM_CHECK_EN | 129 LZ4_HEAD_CSUM_CHECK_EN | 130 LZ4_BLOCK_CSUM_CHECK_EN | 131 DECOM_LZ4_MODE, 132 priv->base + DECOM_CTRL); 133 else if (param->mode == DECOM_GZIP) 134 writel(DECOM_DEFLATE_MODE | DECOM_GZIP_MODE, 135 priv->base + DECOM_CTRL); 136 else if (param->mode == DECOM_ZLIB) 137 writel(DECOM_DEFLATE_MODE | DECOM_ZLIB_MODE, 138 priv->base + DECOM_CTRL); 139 140 writel(param->addr_src, priv->base + DECOM_RADDR); 141 writel(param->addr_dst, priv->base + DECOM_WADDR); 142 143 writel(limit_lo, priv->base + DECOM_LMTSL); 144 writel(limit_hi, priv->base + DECOM_LMTSH); 145 146 if (param->flags && DCOMP_FLG_IRQ_ONESHOT) 147 writel(DECOM_INT_MASK, priv->base + DECOM_IEN); 148 writel(DECOM_ENABLE, priv->base + DECOM_ENR); 149 150 priv->idle_check_once = true; 151 152 return 0; 153 } 154 155 static int rockchip_decom_stop(struct udevice *dev) 156 { 157 struct rockchip_decom_priv *priv = dev_get_priv(dev); 158 159 writel(DECOM_DISABLE, priv->base + DECOM_ENR); 160 161 return 0; 162 } 163 164 /* Caller must call this function to check if decompress done */ 165 static int rockchip_decom_done_poll(struct udevice *dev) 166 { 167 struct rockchip_decom_priv *priv = dev_get_priv(dev); 168 169 /* 170 * Test the decom is idle first time. 171 */ 172 if (!priv->idle_check_once) 173 return !(readl(priv->base + DECOM_AXI_STAT) & DECOM_AXI_IDLE); 174 175 return !(readl(priv->base + DECOM_STAT) & DECOM_COMPLETE); 176 } 177 178 static int rockchip_decom_capability(u32 *buf) 179 { 180 *buf = DECOM_GZIP; 181 #if defined(CONFIG_ROCKCHIP_RK3576) && defined(CONFIG_ROCKCHIP_RV1103B) 182 *buf |= DECOM_LZ4; 183 #endif 184 return 0; 185 } 186 187 static int rockchip_decom_data_size(struct udevice *dev, u64 *buf) 188 { 189 struct rockchip_decom_priv *priv = dev_get_priv(dev); 190 struct decom_param *param = (struct decom_param *)buf; 191 u32 sizel, sizeh; 192 193 sizel = readl(priv->base + DECOM_TSIZEL); 194 sizeh = readl(priv->base + DECOM_TSIZEH); 195 param->size_dst = sizel | ((u64)sizeh << 32); 196 197 return 0; 198 } 199 200 /* Caller must fill in param @buf which represent struct decom_param */ 201 static int rockchip_decom_ioctl(struct udevice *dev, unsigned long request, 202 void *buf) 203 { 204 int ret = -EINVAL; 205 206 switch (request) { 207 case IOCTL_REQ_START: 208 ret = rockchip_decom_start(dev, buf); 209 break; 210 case IOCTL_REQ_POLL: 211 ret = rockchip_decom_done_poll(dev); 212 break; 213 case IOCTL_REQ_STOP: 214 ret = rockchip_decom_stop(dev); 215 break; 216 case IOCTL_REQ_CAPABILITY: 217 ret = rockchip_decom_capability(buf); 218 break; 219 case IOCTL_REQ_DATA_SIZE: 220 ret = rockchip_decom_data_size(dev, buf); 221 break; 222 default: 223 printf("Unsupported ioctl: %ld\n", (ulong)request); 224 break; 225 } 226 227 return ret; 228 } 229 230 static const struct misc_ops rockchip_decom_ops = { 231 .ioctl = rockchip_decom_ioctl, 232 }; 233 234 static int rockchip_decom_ofdata_to_platdata(struct udevice *dev) 235 { 236 struct rockchip_decom_priv *priv = dev_get_priv(dev); 237 238 priv->base = dev_read_addr_ptr(dev); 239 if (!priv->base) 240 return -ENOENT; 241 242 priv->cached = dev_read_u32_default(dev, "data-cached", 0); 243 244 return 0; 245 } 246 247 static int rockchip_decom_probe(struct udevice *dev) 248 { 249 struct rockchip_decom_priv *priv = dev_get_priv(dev); 250 int ret; 251 252 #if CONFIG_IS_ENABLED(DM_RESET) 253 ret = reset_get_by_name(dev, "dresetn", &priv->rst); 254 if (ret) { 255 debug("reset_get_by_name() failed: %d\n", ret); 256 return ret; 257 } 258 #endif 259 260 ret = clk_get_by_index(dev, 1, &priv->dclk); 261 if (ret < 0) 262 return ret; 263 264 ret = clk_set_rate(&priv->dclk, DCLK_DECOM); 265 if (ret < 0) 266 return ret; 267 268 return 0; 269 } 270 271 static const struct udevice_id rockchip_decom_ids[] = { 272 { .compatible = "rockchip,hw-decompress" }, 273 {} 274 }; 275 276 U_BOOT_DRIVER(rockchip_hw_decompress) = { 277 .name = "rockchip_hw_decompress", 278 .id = UCLASS_MISC, 279 .of_match = rockchip_decom_ids, 280 .probe = rockchip_decom_probe, 281 .ofdata_to_platdata = rockchip_decom_ofdata_to_platdata, 282 .priv_auto_alloc_size = sizeof(struct rockchip_decom_priv), 283 .ops = &rockchip_decom_ops, 284 }; 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