1*1136eb5eSSimon Glass /* 2*1136eb5eSSimon Glass * Copyright 2008 Extreme Engineering Solutions, Inc. 3*1136eb5eSSimon Glass * 4*1136eb5eSSimon Glass * SPDX-License-Identifier: GPL-2.0 5*1136eb5eSSimon Glass */ 6*1136eb5eSSimon Glass 7*1136eb5eSSimon Glass #ifndef __DS4510_H_ 8*1136eb5eSSimon Glass #define __DS4510_H_ 9*1136eb5eSSimon Glass 10*1136eb5eSSimon Glass /* General defines */ 11*1136eb5eSSimon Glass #define DS4510_NUM_IO 0x04 12*1136eb5eSSimon Glass #define DS4510_IO_MASK ((1 << DS4510_NUM_IO) - 1) 13*1136eb5eSSimon Glass #define DS4510_EEPROM_PAGE_WRITE_DELAY_MS 20 14*1136eb5eSSimon Glass 15*1136eb5eSSimon Glass /* EEPROM from 0x00 - 0x39 */ 16*1136eb5eSSimon Glass #define DS4510_EEPROM 0x00 17*1136eb5eSSimon Glass #define DS4510_EEPROM_SIZE 0x40 18*1136eb5eSSimon Glass #define DS4510_EEPROM_PAGE_SIZE 0x08 19*1136eb5eSSimon Glass #define DS4510_EEPROM_PAGE_OFFSET(x) ((x) & (DS4510_EEPROM_PAGE_SIZE - 1)) 20*1136eb5eSSimon Glass 21*1136eb5eSSimon Glass /* SEEPROM from 0xf0 - 0xf7 */ 22*1136eb5eSSimon Glass #define DS4510_SEEPROM 0xf0 23*1136eb5eSSimon Glass #define DS4510_SEEPROM_SIZE 0x08 24*1136eb5eSSimon Glass 25*1136eb5eSSimon Glass /* Registers overlapping SEEPROM from 0xf0 - 0xf7 */ 26*1136eb5eSSimon Glass #define DS4510_PULLUP 0xF0 27*1136eb5eSSimon Glass #define DS4510_PULLUP_DIS 0x00 28*1136eb5eSSimon Glass #define DS4510_PULLUP_EN 0x01 29*1136eb5eSSimon Glass #define DS4510_RSTDELAY 0xF1 30*1136eb5eSSimon Glass #define DS4510_RSTDELAY_MASK 0x03 31*1136eb5eSSimon Glass #define DS4510_RSTDELAY_125 0x00 32*1136eb5eSSimon Glass #define DS4510_RSTDELAY_250 0x01 33*1136eb5eSSimon Glass #define DS4510_RSTDELAY_500 0x02 34*1136eb5eSSimon Glass #define DS4510_RSTDELAY_1000 0x03 35*1136eb5eSSimon Glass #define DS4510_IO3 0xF4 36*1136eb5eSSimon Glass #define DS4510_IO2 0xF5 37*1136eb5eSSimon Glass #define DS4510_IO1 0xF6 38*1136eb5eSSimon Glass #define DS4510_IO0 0xF7 39*1136eb5eSSimon Glass 40*1136eb5eSSimon Glass /* Status configuration registers from 0xf8 - 0xf9*/ 41*1136eb5eSSimon Glass #define DS4510_IO_STATUS 0xF8 42*1136eb5eSSimon Glass #define DS4510_CFG 0xF9 43*1136eb5eSSimon Glass #define DS4510_CFG_READY 0x80 44*1136eb5eSSimon Glass #define DS4510_CFG_TRIP_POINT 0x40 45*1136eb5eSSimon Glass #define DS4510_CFG_RESET 0x20 46*1136eb5eSSimon Glass #define DS4510_CFG_SEE 0x10 47*1136eb5eSSimon Glass #define DS4510_CFG_SWRST 0x08 48*1136eb5eSSimon Glass 49*1136eb5eSSimon Glass /* SRAM from 0xfa - 0xff */ 50*1136eb5eSSimon Glass #define DS4510_SRAM 0xfa 51*1136eb5eSSimon Glass #define DS4510_SRAM_SIZE 0x06 52*1136eb5eSSimon Glass 53*1136eb5eSSimon Glass #endif /* __DS4510_H_ */ 54