1# 2# Multifunction miscellaneous devices 3# 4 5menu "Multifunction device drivers" 6 7config MISC 8 bool "Enable Driver Model for Misc drivers" 9 depends on DM 10 help 11 Enable driver model for miscellaneous devices. This class is 12 used only for those do not fit other more general classes. A 13 set of generic read, write and ioctl methods may be used to 14 access the device. 15 16config SPL_MISC 17 bool "Enable Driver Model for Misc drivers in SPL" 18 depends on SPL_DM 19 help 20 Enable driver model for miscellaneous devices. This class is 21 used only for those do not fit other more general classes. A 22 set of generic read, write and ioctl methods may be used to 23 access the device. 24 25config TPL_MISC 26 bool "Enable Driver Model for Misc drivers in TPL" 27 depends on TPL_DM 28 help 29 Enable driver model for miscellaneous devices. This class is 30 used only for those do not fit other more general classes. A 31 set of generic read, write and ioctl methods may be used to 32 access the device. 33 34config MISC_DECOMPRESS 35 bool "Enable misc decompress driver support" 36 depends on MISC 37 help 38 Enable misc decompress driver support. 39 40config SPL_MISC_DECOMPRESS 41 bool "Enable misc decompress driver support in SPL" 42 depends on SPL_MISC 43 help 44 Enable misc decompress driver support in spl. 45 46config ALTERA_SYSID 47 bool "Altera Sysid support" 48 depends on MISC 49 help 50 Select this to enable a sysid for Altera devices. Please find 51 details on the "Embedded Peripherals IP User Guide" of Altera. 52 53config ATSHA204A 54 bool "Support for Atmel ATSHA204A module" 55 depends on MISC 56 help 57 Enable support for I2C connected Atmel's ATSHA204A 58 CryptoAuthentication module found for example on the Turris Omnia 59 board. 60 61config ROCKCHIP_EFUSE 62 bool "Rockchip e-fuse support" 63 depends on MISC 64 help 65 Enable (read-only) access for the e-fuse block found in Rockchip 66 SoCs: accesses can either be made using byte addressing and a length 67 or through child-nodes that are generated based on the e-fuse map 68 retrieved from the DTS. 69 70 This driver currently supports the RK3399 only, but can easily be 71 extended (by porting the read function from the Linux kernel sources) 72 to support other recent Rockchip devices. 73 74config ROCKCHIP_OTP 75 bool "Rockchip OTP Support" 76 depends on MISC 77 help 78 This is a simple drive to dump specified values of Rockchip SoC 79 from otp, such as cpu-leakage. 80 81config ROCKCHIP_HW_DECOMPRESS 82 bool "Rockchip HardWare Decompress Support" 83 depends on MISC_DECOMPRESS 84 help 85 This driver support Decompress IP built-in Rockchip SoC, support 86 LZ4, GZIP, PNG, ZLIB. 87 88config ROCKCHIP_PM_CONFIG 89 bool "Rockchip PM Config Support" 90 depends on ARM_CPU_SUSPEND 91 help 92 This driver supports to configure parameters of system sleep. 93 94config SPL_ROCKCHIP_HW_DECOMPRESS 95 bool "Rockchip HardWare Decompress Support" 96 depends on SPL_MISC_DECOMPRESS 97 help 98 This driver support Decompress IP built-in Rockchip SoC, support 99 LZ4, GZIP, PNG, ZLIB. 100 101config ROCKCHIP_SECURE_OTP 102 bool "Rockchip Secure OTP Support" 103 depends on MISC && !OPTEE_CLIENT 104 help 105 Support read & write secure otp. 106 107config SPL_ROCKCHIP_SECURE_OTP 108 bool "Rockchip Secure OTP Support in spl" 109 depends on SPL_MISC 110 help 111 Support read & write secure otp in spl. 112 113config CMD_CROS_EC 114 bool "Enable crosec command" 115 depends on CROS_EC 116 help 117 Enable command-line access to the Chrome OS EC (Embedded 118 Controller). This provides the 'crosec' command which has 119 a number of sub-commands for performing EC tasks such as 120 updating its flash, accessing a small saved context area 121 and talking to the I2C bus behind the EC (if there is one). 122 123config CROS_EC 124 bool "Enable Chrome OS EC" 125 help 126 Enable access to the Chrome OS EC. This is a separate 127 microcontroller typically available on a SPI bus on Chromebooks. It 128 provides access to the keyboard, some internal storage and may 129 control access to the battery and main PMIC depending on the 130 device. You can use the 'crosec' command to access it. 131 132config CROS_EC_I2C 133 bool "Enable Chrome OS EC I2C driver" 134 depends on CROS_EC 135 help 136 Enable I2C access to the Chrome OS EC. This is used on older 137 ARM Chromebooks such as snow and spring before the standard bus 138 changed to SPI. The EC will accept commands across the I2C using 139 a special message protocol, and provide responses. 140 141config CROS_EC_LPC 142 bool "Enable Chrome OS EC LPC driver" 143 depends on CROS_EC 144 help 145 Enable I2C access to the Chrome OS EC. This is used on x86 146 Chromebooks such as link and falco. The keyboard is provided 147 through a legacy port interface, so on x86 machines the main 148 function of the EC is power and thermal management. 149 150config CROS_EC_SANDBOX 151 bool "Enable Chrome OS EC sandbox driver" 152 depends on CROS_EC && SANDBOX 153 help 154 Enable a sandbox emulation of the Chrome OS EC. This supports 155 keyboard (use the -l flag to enable the LCD), verified boot context, 156 EC flash read/write/erase support and a few other things. It is 157 enough to perform a Chrome OS verified boot on sandbox. 158 159config CROS_EC_SPI 160 bool "Enable Chrome OS EC SPI driver" 161 depends on CROS_EC 162 help 163 Enable SPI access to the Chrome OS EC. This is used on newer 164 ARM Chromebooks such as pit, pi and nyan-big. The SPI interface 165 provides a faster and more robust interface than I2C but the bugs 166 are less interesting. 167 168config DS4510 169 bool "Enable support for DS4510 CPU supervisor" 170 help 171 Enable support for the Maxim DS4510 CPU supervisor. It has an 172 integrated 64-byte EEPROM, four programmable non-volatile I/O pins 173 and a configurable timer for the supervisor function. The device is 174 connected over I2C. 175 176config FSL_SEC_MON 177 bool "Enable FSL SEC_MON Driver" 178 help 179 Freescale Security Monitor block is responsible for monitoring 180 system states. 181 Security Monitor can be transitioned on any security failures, 182 like software violations or hardware security violations. 183 184config MXC_OCOTP 185 bool "Enable MXC OCOTP Driver" 186 help 187 If you say Y here, you will get support for the One Time 188 Programmable memory pages that are stored on the some 189 Freescale i.MX processors. 190 191config NUVOTON_NCT6102D 192 bool "Enable Nuvoton NCT6102D Super I/O driver" 193 help 194 If you say Y here, you will get support for the Nuvoton 195 NCT6102D Super I/O driver. This can be used to enable or 196 disable the legacy UART, the watchdog or other devices 197 in the Nuvoton Super IO chips on X86 platforms. 198 199config PWRSEQ 200 bool "Enable power-sequencing drivers" 201 depends on DM 202 help 203 Power-sequencing drivers provide support for controlling power for 204 devices. They are typically referenced by a phandle from another 205 device. When the device is started up, its power sequence can be 206 initiated. 207 208config SPL_PWRSEQ 209 bool "Enable power-sequencing drivers for SPL" 210 depends on PWRSEQ 211 help 212 Power-sequencing drivers provide support for controlling power for 213 devices. They are typically referenced by a phandle from another 214 device. When the device is started up, its power sequence can be 215 initiated. 216 217config PCA9551_LED 218 bool "Enable PCA9551 LED driver" 219 help 220 Enable driver for PCA9551 LED controller. This controller 221 is connected via I2C. So I2C needs to be enabled. 222 223config PCA9551_I2C_ADDR 224 hex "I2C address of PCA9551 LED controller" 225 depends on PCA9551_LED 226 default 0x60 227 help 228 The I2C address of the PCA9551 LED controller. 229 230config TEGRA_CAR 231 bool "Enable support for the Tegra CAR driver" 232 depends on TEGRA_NO_BPMP 233 help 234 The Tegra CAR (Clock and Reset Controller) is a HW module that 235 controls almost all clocks and resets in a Tegra SoC. 236 237config TEGRA186_BPMP 238 bool "Enable support for the Tegra186 BPMP driver" 239 depends on TEGRA186 240 help 241 The Tegra BPMP (Boot and Power Management Processor) is a separate 242 auxiliary CPU embedded into Tegra to perform power management work, 243 and controls related features such as clocks, resets, power domains, 244 PMIC I2C bus, etc. This driver provides the core low-level 245 communication path by which feature-specific drivers (such as clock) 246 can make requests to the BPMP. This driver is similar to an MFD 247 driver in the Linux kernel. 248 249config WINBOND_W83627 250 bool "Enable Winbond Super I/O driver" 251 help 252 If you say Y here, you will get support for the Winbond 253 W83627 Super I/O driver. This can be used to enable the 254 legacy UART or other devices in the Winbond Super IO chips 255 on X86 platforms. 256 257config QFW 258 bool 259 help 260 Hidden option to enable QEMU fw_cfg interface. This will be selected by 261 either CONFIG_CMD_QFW or CONFIG_GENERATE_ACPI_TABLE. 262 263config I2C_EEPROM 264 bool "Enable driver for generic I2C-attached EEPROMs" 265 depends on MISC 266 help 267 Enable a generic driver for EEPROMs attached via I2C. 268 269if I2C_EEPROM 270 271config SYS_I2C_EEPROM_ADDR 272 hex "Chip address of the EEPROM device" 273 default 0 274 275config SYS_I2C_EEPROM_BUS 276 int "I2C bus of the EEPROM device." 277 default 0 278 279config SYS_EEPROM_SIZE 280 int "Size in bytes of the EEPROM device" 281 default 256 282 283config SYS_EEPROM_PAGE_WRITE_BITS 284 int "Number of bits used to address bytes in a single page" 285 default 0 286 help 287 The EEPROM page size is 2^SYS_EEPROM_PAGE_WRITE_BITS. 288 A 64 byte page, for example would require six bits. 289 290config SYS_EEPROM_PAGE_WRITE_DELAY_MS 291 int "Number of milliseconds to delay between page writes" 292 default 0 293 294config SYS_I2C_EEPROM_ADDR_LEN 295 int "Length in bytes of the EEPROM memory array address" 296 default 1 297 help 298 Note: This is NOT the chip address length! 299 300config SYS_I2C_EEPROM_ADDR_OVERFLOW 301 hex "EEPROM Address Overflow" 302 default 0 303 help 304 EEPROM chips that implement "address overflow" are ones 305 like Catalyst 24WC04/08/16 which has 9/10/11 bits of 306 address and the extra bits end up in the "chip address" bit 307 slots. This makes a 24WC08 (1Kbyte) chip look like four 256 308 byte chips. 309 310endif 311 312 313endmenu 314