1# 2# Multifunction miscellaneous devices 3# 4 5menu "Multifunction device drivers" 6 7config MISC 8 bool "Enable Driver Model for Misc drivers" 9 depends on DM 10 help 11 Enable driver model for miscellaneous devices. This class is 12 used only for those do not fit other more general classes. A 13 set of generic read, write and ioctl methods may be used to 14 access the device. 15 16config SPL_MISC 17 bool "Enable Driver Model for Misc drivers in SPL" 18 depends on SPL_DM 19 help 20 Enable driver model for miscellaneous devices. This class is 21 used only for those do not fit other more general classes. A 22 set of generic read, write and ioctl methods may be used to 23 access the device. 24 25config TPL_MISC 26 bool "Enable Driver Model for Misc drivers in TPL" 27 depends on TPL_DM 28 help 29 Enable driver model for miscellaneous devices. This class is 30 used only for those do not fit other more general classes. A 31 set of generic read, write and ioctl methods may be used to 32 access the device. 33 34config ALTERA_SYSID 35 bool "Altera Sysid support" 36 depends on MISC 37 help 38 Select this to enable a sysid for Altera devices. Please find 39 details on the "Embedded Peripherals IP User Guide" of Altera. 40 41config ATSHA204A 42 bool "Support for Atmel ATSHA204A module" 43 depends on MISC 44 help 45 Enable support for I2C connected Atmel's ATSHA204A 46 CryptoAuthentication module found for example on the Turris Omnia 47 board. 48 49config ROCKCHIP_EFUSE 50 bool "Rockchip e-fuse support" 51 depends on MISC 52 help 53 Enable (read-only) access for the e-fuse block found in Rockchip 54 SoCs: accesses can either be made using byte addressing and a length 55 or through child-nodes that are generated based on the e-fuse map 56 retrieved from the DTS. 57 58 This driver currently supports the RK3399 only, but can easily be 59 extended (by porting the read function from the Linux kernel sources) 60 to support other recent Rockchip devices. 61 62config ROCKCHIP_OTP 63 bool "Rockchip OTP Support" 64 depends on MISC 65 help 66 This is a simple drive to dump specified values of Rockchip SoC 67 from otp, such as cpu-leakage. 68 69config ROCKCHIP_HW_DECOMPRESS 70 bool "Rockchip HardWare Decompress Support" 71 depends on MISC && IRQ 72 help 73 This driver support Decompress IP built-in Rockchip SoC, support 74 LZ4, GZIP, PNG, ZLIB. 75 76config SPL_ROCKCHIP_HW_DECOMPRESS 77 bool "Rockchip HardWare Decompress Support" 78 depends on SPL_MISC 79 help 80 This driver support Decompress IP built-in Rockchip SoC, support 81 LZ4, GZIP, PNG, ZLIB. 82 83config SPL_ROCKCHIP_SECURE_OTP 84 bool "Rockchip Secure OTP Support in spl" 85 depends on SPL_MISC 86 help 87 Support read & write secure otp in spl. 88 89config CMD_CROS_EC 90 bool "Enable crosec command" 91 depends on CROS_EC 92 help 93 Enable command-line access to the Chrome OS EC (Embedded 94 Controller). This provides the 'crosec' command which has 95 a number of sub-commands for performing EC tasks such as 96 updating its flash, accessing a small saved context area 97 and talking to the I2C bus behind the EC (if there is one). 98 99config CROS_EC 100 bool "Enable Chrome OS EC" 101 help 102 Enable access to the Chrome OS EC. This is a separate 103 microcontroller typically available on a SPI bus on Chromebooks. It 104 provides access to the keyboard, some internal storage and may 105 control access to the battery and main PMIC depending on the 106 device. You can use the 'crosec' command to access it. 107 108config CROS_EC_I2C 109 bool "Enable Chrome OS EC I2C driver" 110 depends on CROS_EC 111 help 112 Enable I2C access to the Chrome OS EC. This is used on older 113 ARM Chromebooks such as snow and spring before the standard bus 114 changed to SPI. The EC will accept commands across the I2C using 115 a special message protocol, and provide responses. 116 117config CROS_EC_LPC 118 bool "Enable Chrome OS EC LPC driver" 119 depends on CROS_EC 120 help 121 Enable I2C access to the Chrome OS EC. This is used on x86 122 Chromebooks such as link and falco. The keyboard is provided 123 through a legacy port interface, so on x86 machines the main 124 function of the EC is power and thermal management. 125 126config CROS_EC_SANDBOX 127 bool "Enable Chrome OS EC sandbox driver" 128 depends on CROS_EC && SANDBOX 129 help 130 Enable a sandbox emulation of the Chrome OS EC. This supports 131 keyboard (use the -l flag to enable the LCD), verified boot context, 132 EC flash read/write/erase support and a few other things. It is 133 enough to perform a Chrome OS verified boot on sandbox. 134 135config CROS_EC_SPI 136 bool "Enable Chrome OS EC SPI driver" 137 depends on CROS_EC 138 help 139 Enable SPI access to the Chrome OS EC. This is used on newer 140 ARM Chromebooks such as pit, pi and nyan-big. The SPI interface 141 provides a faster and more robust interface than I2C but the bugs 142 are less interesting. 143 144config DS4510 145 bool "Enable support for DS4510 CPU supervisor" 146 help 147 Enable support for the Maxim DS4510 CPU supervisor. It has an 148 integrated 64-byte EEPROM, four programmable non-volatile I/O pins 149 and a configurable timer for the supervisor function. The device is 150 connected over I2C. 151 152config FSL_SEC_MON 153 bool "Enable FSL SEC_MON Driver" 154 help 155 Freescale Security Monitor block is responsible for monitoring 156 system states. 157 Security Monitor can be transitioned on any security failures, 158 like software violations or hardware security violations. 159 160config MXC_OCOTP 161 bool "Enable MXC OCOTP Driver" 162 help 163 If you say Y here, you will get support for the One Time 164 Programmable memory pages that are stored on the some 165 Freescale i.MX processors. 166 167config NUVOTON_NCT6102D 168 bool "Enable Nuvoton NCT6102D Super I/O driver" 169 help 170 If you say Y here, you will get support for the Nuvoton 171 NCT6102D Super I/O driver. This can be used to enable or 172 disable the legacy UART, the watchdog or other devices 173 in the Nuvoton Super IO chips on X86 platforms. 174 175config PWRSEQ 176 bool "Enable power-sequencing drivers" 177 depends on DM 178 help 179 Power-sequencing drivers provide support for controlling power for 180 devices. They are typically referenced by a phandle from another 181 device. When the device is started up, its power sequence can be 182 initiated. 183 184config SPL_PWRSEQ 185 bool "Enable power-sequencing drivers for SPL" 186 depends on PWRSEQ 187 help 188 Power-sequencing drivers provide support for controlling power for 189 devices. They are typically referenced by a phandle from another 190 device. When the device is started up, its power sequence can be 191 initiated. 192 193config PCA9551_LED 194 bool "Enable PCA9551 LED driver" 195 help 196 Enable driver for PCA9551 LED controller. This controller 197 is connected via I2C. So I2C needs to be enabled. 198 199config PCA9551_I2C_ADDR 200 hex "I2C address of PCA9551 LED controller" 201 depends on PCA9551_LED 202 default 0x60 203 help 204 The I2C address of the PCA9551 LED controller. 205 206config TEGRA_CAR 207 bool "Enable support for the Tegra CAR driver" 208 depends on TEGRA_NO_BPMP 209 help 210 The Tegra CAR (Clock and Reset Controller) is a HW module that 211 controls almost all clocks and resets in a Tegra SoC. 212 213config TEGRA186_BPMP 214 bool "Enable support for the Tegra186 BPMP driver" 215 depends on TEGRA186 216 help 217 The Tegra BPMP (Boot and Power Management Processor) is a separate 218 auxiliary CPU embedded into Tegra to perform power management work, 219 and controls related features such as clocks, resets, power domains, 220 PMIC I2C bus, etc. This driver provides the core low-level 221 communication path by which feature-specific drivers (such as clock) 222 can make requests to the BPMP. This driver is similar to an MFD 223 driver in the Linux kernel. 224 225config WINBOND_W83627 226 bool "Enable Winbond Super I/O driver" 227 help 228 If you say Y here, you will get support for the Winbond 229 W83627 Super I/O driver. This can be used to enable the 230 legacy UART or other devices in the Winbond Super IO chips 231 on X86 platforms. 232 233config QFW 234 bool 235 help 236 Hidden option to enable QEMU fw_cfg interface. This will be selected by 237 either CONFIG_CMD_QFW or CONFIG_GENERATE_ACPI_TABLE. 238 239config I2C_EEPROM 240 bool "Enable driver for generic I2C-attached EEPROMs" 241 depends on MISC 242 help 243 Enable a generic driver for EEPROMs attached via I2C. 244 245if I2C_EEPROM 246 247config SYS_I2C_EEPROM_ADDR 248 hex "Chip address of the EEPROM device" 249 default 0 250 251config SYS_I2C_EEPROM_BUS 252 int "I2C bus of the EEPROM device." 253 default 0 254 255config SYS_EEPROM_SIZE 256 int "Size in bytes of the EEPROM device" 257 default 256 258 259config SYS_EEPROM_PAGE_WRITE_BITS 260 int "Number of bits used to address bytes in a single page" 261 default 0 262 help 263 The EEPROM page size is 2^SYS_EEPROM_PAGE_WRITE_BITS. 264 A 64 byte page, for example would require six bits. 265 266config SYS_EEPROM_PAGE_WRITE_DELAY_MS 267 int "Number of milliseconds to delay between page writes" 268 default 0 269 270config SYS_I2C_EEPROM_ADDR_LEN 271 int "Length in bytes of the EEPROM memory array address" 272 default 1 273 help 274 Note: This is NOT the chip address length! 275 276config SYS_I2C_EEPROM_ADDR_OVERFLOW 277 hex "EEPROM Address Overflow" 278 default 0 279 help 280 EEPROM chips that implement "address overflow" are ones 281 like Catalyst 24WC04/08/16 which has 9/10/11 bits of 282 address and the extra bits end up in the "chip address" bit 283 slots. This makes a 24WC08 (1Kbyte) chip look like four 256 284 byte chips. 285 286endif 287 288 289endmenu 290