1# 2# Multifunction miscellaneous devices 3# 4 5menu "Multifunction device drivers" 6 7config MISC 8 bool "Enable Driver Model for Misc drivers" 9 depends on DM 10 help 11 Enable driver model for miscellaneous devices. This class is 12 used only for those do not fit other more general classes. A 13 set of generic read, write and ioctl methods may be used to 14 access the device. 15 16config SPL_MISC 17 bool "Enable Driver Model for Misc drivers in SPL" 18 depends on SPL_DM 19 help 20 Enable driver model for miscellaneous devices. This class is 21 used only for those do not fit other more general classes. A 22 set of generic read, write and ioctl methods may be used to 23 access the device. 24 25config TPL_MISC 26 bool "Enable Driver Model for Misc drivers in TPL" 27 depends on TPL_DM 28 help 29 Enable driver model for miscellaneous devices. This class is 30 used only for those do not fit other more general classes. A 31 set of generic read, write and ioctl methods may be used to 32 access the device. 33 34config ALTERA_SYSID 35 bool "Altera Sysid support" 36 depends on MISC 37 help 38 Select this to enable a sysid for Altera devices. Please find 39 details on the "Embedded Peripherals IP User Guide" of Altera. 40 41config ATSHA204A 42 bool "Support for Atmel ATSHA204A module" 43 depends on MISC 44 help 45 Enable support for I2C connected Atmel's ATSHA204A 46 CryptoAuthentication module found for example on the Turris Omnia 47 board. 48 49config ROCKCHIP_EFUSE 50 bool "Rockchip e-fuse support" 51 depends on MISC 52 help 53 Enable (read-only) access for the e-fuse block found in Rockchip 54 SoCs: accesses can either be made using byte addressing and a length 55 or through child-nodes that are generated based on the e-fuse map 56 retrieved from the DTS. 57 58 This driver currently supports the RK3399 only, but can easily be 59 extended (by porting the read function from the Linux kernel sources) 60 to support other recent Rockchip devices. 61 62config ROCKCHIP_OTP 63 bool "Rockchip OTP Support" 64 depends on MISC 65 help 66 This is a simple drive to dump specified values of Rockchip SoC 67 from otp, such as cpu-leakage. 68 69config ROCKCHIP_HW_DECOMPRESS 70 bool "Rockchip HardWare Decompress Support" 71 depends on MISC && IRQ 72 help 73 This driver support Decompress IP built-in Rockchip SoC, support 74 LZ4, GZIP, PNG, ZLIB. 75 76config SPL_ROCKCHIP_HW_DECOMPRESS 77 bool "Rockchip HardWare Decompress Support" 78 depends on SPL_MISC 79 help 80 This driver support Decompress IP built-in Rockchip SoC, support 81 LZ4, GZIP, PNG, ZLIB. 82 83config SPL_ROCKCHIP_SECURE_OTP 84 bool "Rockchip Secure OTP Support in spl" 85 depends on SPL_MISC 86 help 87 Support read & write secure otp in spl. 88 89config SPL_ROCKCHIP_SECURE_OTP_V2 90 bool "Rockchip Secure OTP Version 2 Support in spl" 91 depends on SPL_MISC 92 help 93 Support read & write secure otp in spl. Support platforms: rv1126. 94 95config CMD_CROS_EC 96 bool "Enable crosec command" 97 depends on CROS_EC 98 help 99 Enable command-line access to the Chrome OS EC (Embedded 100 Controller). This provides the 'crosec' command which has 101 a number of sub-commands for performing EC tasks such as 102 updating its flash, accessing a small saved context area 103 and talking to the I2C bus behind the EC (if there is one). 104 105config CROS_EC 106 bool "Enable Chrome OS EC" 107 help 108 Enable access to the Chrome OS EC. This is a separate 109 microcontroller typically available on a SPI bus on Chromebooks. It 110 provides access to the keyboard, some internal storage and may 111 control access to the battery and main PMIC depending on the 112 device. You can use the 'crosec' command to access it. 113 114config CROS_EC_I2C 115 bool "Enable Chrome OS EC I2C driver" 116 depends on CROS_EC 117 help 118 Enable I2C access to the Chrome OS EC. This is used on older 119 ARM Chromebooks such as snow and spring before the standard bus 120 changed to SPI. The EC will accept commands across the I2C using 121 a special message protocol, and provide responses. 122 123config CROS_EC_LPC 124 bool "Enable Chrome OS EC LPC driver" 125 depends on CROS_EC 126 help 127 Enable I2C access to the Chrome OS EC. This is used on x86 128 Chromebooks such as link and falco. The keyboard is provided 129 through a legacy port interface, so on x86 machines the main 130 function of the EC is power and thermal management. 131 132config CROS_EC_SANDBOX 133 bool "Enable Chrome OS EC sandbox driver" 134 depends on CROS_EC && SANDBOX 135 help 136 Enable a sandbox emulation of the Chrome OS EC. This supports 137 keyboard (use the -l flag to enable the LCD), verified boot context, 138 EC flash read/write/erase support and a few other things. It is 139 enough to perform a Chrome OS verified boot on sandbox. 140 141config CROS_EC_SPI 142 bool "Enable Chrome OS EC SPI driver" 143 depends on CROS_EC 144 help 145 Enable SPI access to the Chrome OS EC. This is used on newer 146 ARM Chromebooks such as pit, pi and nyan-big. The SPI interface 147 provides a faster and more robust interface than I2C but the bugs 148 are less interesting. 149 150config DS4510 151 bool "Enable support for DS4510 CPU supervisor" 152 help 153 Enable support for the Maxim DS4510 CPU supervisor. It has an 154 integrated 64-byte EEPROM, four programmable non-volatile I/O pins 155 and a configurable timer for the supervisor function. The device is 156 connected over I2C. 157 158config FSL_SEC_MON 159 bool "Enable FSL SEC_MON Driver" 160 help 161 Freescale Security Monitor block is responsible for monitoring 162 system states. 163 Security Monitor can be transitioned on any security failures, 164 like software violations or hardware security violations. 165 166config MXC_OCOTP 167 bool "Enable MXC OCOTP Driver" 168 help 169 If you say Y here, you will get support for the One Time 170 Programmable memory pages that are stored on the some 171 Freescale i.MX processors. 172 173config NUVOTON_NCT6102D 174 bool "Enable Nuvoton NCT6102D Super I/O driver" 175 help 176 If you say Y here, you will get support for the Nuvoton 177 NCT6102D Super I/O driver. This can be used to enable or 178 disable the legacy UART, the watchdog or other devices 179 in the Nuvoton Super IO chips on X86 platforms. 180 181config PWRSEQ 182 bool "Enable power-sequencing drivers" 183 depends on DM 184 help 185 Power-sequencing drivers provide support for controlling power for 186 devices. They are typically referenced by a phandle from another 187 device. When the device is started up, its power sequence can be 188 initiated. 189 190config SPL_PWRSEQ 191 bool "Enable power-sequencing drivers for SPL" 192 depends on PWRSEQ 193 help 194 Power-sequencing drivers provide support for controlling power for 195 devices. They are typically referenced by a phandle from another 196 device. When the device is started up, its power sequence can be 197 initiated. 198 199config PCA9551_LED 200 bool "Enable PCA9551 LED driver" 201 help 202 Enable driver for PCA9551 LED controller. This controller 203 is connected via I2C. So I2C needs to be enabled. 204 205config PCA9551_I2C_ADDR 206 hex "I2C address of PCA9551 LED controller" 207 depends on PCA9551_LED 208 default 0x60 209 help 210 The I2C address of the PCA9551 LED controller. 211 212config TEGRA_CAR 213 bool "Enable support for the Tegra CAR driver" 214 depends on TEGRA_NO_BPMP 215 help 216 The Tegra CAR (Clock and Reset Controller) is a HW module that 217 controls almost all clocks and resets in a Tegra SoC. 218 219config TEGRA186_BPMP 220 bool "Enable support for the Tegra186 BPMP driver" 221 depends on TEGRA186 222 help 223 The Tegra BPMP (Boot and Power Management Processor) is a separate 224 auxiliary CPU embedded into Tegra to perform power management work, 225 and controls related features such as clocks, resets, power domains, 226 PMIC I2C bus, etc. This driver provides the core low-level 227 communication path by which feature-specific drivers (such as clock) 228 can make requests to the BPMP. This driver is similar to an MFD 229 driver in the Linux kernel. 230 231config WINBOND_W83627 232 bool "Enable Winbond Super I/O driver" 233 help 234 If you say Y here, you will get support for the Winbond 235 W83627 Super I/O driver. This can be used to enable the 236 legacy UART or other devices in the Winbond Super IO chips 237 on X86 platforms. 238 239config QFW 240 bool 241 help 242 Hidden option to enable QEMU fw_cfg interface. This will be selected by 243 either CONFIG_CMD_QFW or CONFIG_GENERATE_ACPI_TABLE. 244 245config I2C_EEPROM 246 bool "Enable driver for generic I2C-attached EEPROMs" 247 depends on MISC 248 help 249 Enable a generic driver for EEPROMs attached via I2C. 250 251if I2C_EEPROM 252 253config SYS_I2C_EEPROM_ADDR 254 hex "Chip address of the EEPROM device" 255 default 0 256 257config SYS_I2C_EEPROM_BUS 258 int "I2C bus of the EEPROM device." 259 default 0 260 261config SYS_EEPROM_SIZE 262 int "Size in bytes of the EEPROM device" 263 default 256 264 265config SYS_EEPROM_PAGE_WRITE_BITS 266 int "Number of bits used to address bytes in a single page" 267 default 0 268 help 269 The EEPROM page size is 2^SYS_EEPROM_PAGE_WRITE_BITS. 270 A 64 byte page, for example would require six bits. 271 272config SYS_EEPROM_PAGE_WRITE_DELAY_MS 273 int "Number of milliseconds to delay between page writes" 274 default 0 275 276config SYS_I2C_EEPROM_ADDR_LEN 277 int "Length in bytes of the EEPROM memory array address" 278 default 1 279 help 280 Note: This is NOT the chip address length! 281 282config SYS_I2C_EEPROM_ADDR_OVERFLOW 283 hex "EEPROM Address Overflow" 284 default 0 285 help 286 EEPROM chips that implement "address overflow" are ones 287 like Catalyst 24WC04/08/16 which has 9/10/11 bits of 288 address and the extra bits end up in the "chip address" bit 289 slots. This makes a 24WC08 (1Kbyte) chip look like four 256 290 byte chips. 291 292endif 293 294 295endmenu 296