1# 2# Multifunction miscellaneous devices 3# 4 5menu "Multifunction device drivers" 6 7config MISC 8 bool "Enable Driver Model for Misc drivers" 9 depends on DM 10 help 11 Enable driver model for miscellaneous devices. This class is 12 used only for those do not fit other more general classes. A 13 set of generic read, write and ioctl methods may be used to 14 access the device. 15 16config SPL_MISC 17 bool "Enable Driver Model for Misc drivers in SPL" 18 depends on SPL_DM 19 help 20 Enable driver model for miscellaneous devices. This class is 21 used only for those do not fit other more general classes. A 22 set of generic read, write and ioctl methods may be used to 23 access the device. 24 25config TPL_MISC 26 bool "Enable Driver Model for Misc drivers in TPL" 27 depends on TPL_DM 28 help 29 Enable driver model for miscellaneous devices. This class is 30 used only for those do not fit other more general classes. A 31 set of generic read, write and ioctl methods may be used to 32 access the device. 33 34config ALTERA_SYSID 35 bool "Altera Sysid support" 36 depends on MISC 37 help 38 Select this to enable a sysid for Altera devices. Please find 39 details on the "Embedded Peripherals IP User Guide" of Altera. 40 41config ATSHA204A 42 bool "Support for Atmel ATSHA204A module" 43 depends on MISC 44 help 45 Enable support for I2C connected Atmel's ATSHA204A 46 CryptoAuthentication module found for example on the Turris Omnia 47 board. 48 49config ROCKCHIP_EFUSE 50 bool "Rockchip e-fuse support" 51 depends on MISC 52 help 53 Enable (read-only) access for the e-fuse block found in Rockchip 54 SoCs: accesses can either be made using byte addressing and a length 55 or through child-nodes that are generated based on the e-fuse map 56 retrieved from the DTS. 57 58 This driver currently supports the RK3399 only, but can easily be 59 extended (by porting the read function from the Linux kernel sources) 60 to support other recent Rockchip devices. 61 62config ROCKCHIP_OTP 63 bool "Rockchip OTP Support" 64 depends on MISC 65 help 66 This is a simple drive to dump specified values of Rockchip SoC 67 from otp, such as cpu-leakage. 68 69config CMD_CROS_EC 70 bool "Enable crosec command" 71 depends on CROS_EC 72 help 73 Enable command-line access to the Chrome OS EC (Embedded 74 Controller). This provides the 'crosec' command which has 75 a number of sub-commands for performing EC tasks such as 76 updating its flash, accessing a small saved context area 77 and talking to the I2C bus behind the EC (if there is one). 78 79config CROS_EC 80 bool "Enable Chrome OS EC" 81 help 82 Enable access to the Chrome OS EC. This is a separate 83 microcontroller typically available on a SPI bus on Chromebooks. It 84 provides access to the keyboard, some internal storage and may 85 control access to the battery and main PMIC depending on the 86 device. You can use the 'crosec' command to access it. 87 88config CROS_EC_I2C 89 bool "Enable Chrome OS EC I2C driver" 90 depends on CROS_EC 91 help 92 Enable I2C access to the Chrome OS EC. This is used on older 93 ARM Chromebooks such as snow and spring before the standard bus 94 changed to SPI. The EC will accept commands across the I2C using 95 a special message protocol, and provide responses. 96 97config CROS_EC_LPC 98 bool "Enable Chrome OS EC LPC driver" 99 depends on CROS_EC 100 help 101 Enable I2C access to the Chrome OS EC. This is used on x86 102 Chromebooks such as link and falco. The keyboard is provided 103 through a legacy port interface, so on x86 machines the main 104 function of the EC is power and thermal management. 105 106config CROS_EC_SANDBOX 107 bool "Enable Chrome OS EC sandbox driver" 108 depends on CROS_EC && SANDBOX 109 help 110 Enable a sandbox emulation of the Chrome OS EC. This supports 111 keyboard (use the -l flag to enable the LCD), verified boot context, 112 EC flash read/write/erase support and a few other things. It is 113 enough to perform a Chrome OS verified boot on sandbox. 114 115config CROS_EC_SPI 116 bool "Enable Chrome OS EC SPI driver" 117 depends on CROS_EC 118 help 119 Enable SPI access to the Chrome OS EC. This is used on newer 120 ARM Chromebooks such as pit, pi and nyan-big. The SPI interface 121 provides a faster and more robust interface than I2C but the bugs 122 are less interesting. 123 124config DS4510 125 bool "Enable support for DS4510 CPU supervisor" 126 help 127 Enable support for the Maxim DS4510 CPU supervisor. It has an 128 integrated 64-byte EEPROM, four programmable non-volatile I/O pins 129 and a configurable timer for the supervisor function. The device is 130 connected over I2C. 131 132config FSL_SEC_MON 133 bool "Enable FSL SEC_MON Driver" 134 help 135 Freescale Security Monitor block is responsible for monitoring 136 system states. 137 Security Monitor can be transitioned on any security failures, 138 like software violations or hardware security violations. 139 140config MXC_OCOTP 141 bool "Enable MXC OCOTP Driver" 142 help 143 If you say Y here, you will get support for the One Time 144 Programmable memory pages that are stored on the some 145 Freescale i.MX processors. 146 147config NUVOTON_NCT6102D 148 bool "Enable Nuvoton NCT6102D Super I/O driver" 149 help 150 If you say Y here, you will get support for the Nuvoton 151 NCT6102D Super I/O driver. This can be used to enable or 152 disable the legacy UART, the watchdog or other devices 153 in the Nuvoton Super IO chips on X86 platforms. 154 155config PWRSEQ 156 bool "Enable power-sequencing drivers" 157 depends on DM 158 help 159 Power-sequencing drivers provide support for controlling power for 160 devices. They are typically referenced by a phandle from another 161 device. When the device is started up, its power sequence can be 162 initiated. 163 164config SPL_PWRSEQ 165 bool "Enable power-sequencing drivers for SPL" 166 depends on PWRSEQ 167 help 168 Power-sequencing drivers provide support for controlling power for 169 devices. They are typically referenced by a phandle from another 170 device. When the device is started up, its power sequence can be 171 initiated. 172 173config PCA9551_LED 174 bool "Enable PCA9551 LED driver" 175 help 176 Enable driver for PCA9551 LED controller. This controller 177 is connected via I2C. So I2C needs to be enabled. 178 179config PCA9551_I2C_ADDR 180 hex "I2C address of PCA9551 LED controller" 181 depends on PCA9551_LED 182 default 0x60 183 help 184 The I2C address of the PCA9551 LED controller. 185 186config TEGRA_CAR 187 bool "Enable support for the Tegra CAR driver" 188 depends on TEGRA_NO_BPMP 189 help 190 The Tegra CAR (Clock and Reset Controller) is a HW module that 191 controls almost all clocks and resets in a Tegra SoC. 192 193config TEGRA186_BPMP 194 bool "Enable support for the Tegra186 BPMP driver" 195 depends on TEGRA186 196 help 197 The Tegra BPMP (Boot and Power Management Processor) is a separate 198 auxiliary CPU embedded into Tegra to perform power management work, 199 and controls related features such as clocks, resets, power domains, 200 PMIC I2C bus, etc. This driver provides the core low-level 201 communication path by which feature-specific drivers (such as clock) 202 can make requests to the BPMP. This driver is similar to an MFD 203 driver in the Linux kernel. 204 205config WINBOND_W83627 206 bool "Enable Winbond Super I/O driver" 207 help 208 If you say Y here, you will get support for the Winbond 209 W83627 Super I/O driver. This can be used to enable the 210 legacy UART or other devices in the Winbond Super IO chips 211 on X86 platforms. 212 213config QFW 214 bool 215 help 216 Hidden option to enable QEMU fw_cfg interface. This will be selected by 217 either CONFIG_CMD_QFW or CONFIG_GENERATE_ACPI_TABLE. 218 219config I2C_EEPROM 220 bool "Enable driver for generic I2C-attached EEPROMs" 221 depends on MISC 222 help 223 Enable a generic driver for EEPROMs attached via I2C. 224 225if I2C_EEPROM 226 227config SYS_I2C_EEPROM_ADDR 228 hex "Chip address of the EEPROM device" 229 default 0 230 231config SYS_I2C_EEPROM_BUS 232 int "I2C bus of the EEPROM device." 233 default 0 234 235config SYS_EEPROM_SIZE 236 int "Size in bytes of the EEPROM device" 237 default 256 238 239config SYS_EEPROM_PAGE_WRITE_BITS 240 int "Number of bits used to address bytes in a single page" 241 default 0 242 help 243 The EEPROM page size is 2^SYS_EEPROM_PAGE_WRITE_BITS. 244 A 64 byte page, for example would require six bits. 245 246config SYS_EEPROM_PAGE_WRITE_DELAY_MS 247 int "Number of milliseconds to delay between page writes" 248 default 0 249 250config SYS_I2C_EEPROM_ADDR_LEN 251 int "Length in bytes of the EEPROM memory array address" 252 default 1 253 help 254 Note: This is NOT the chip address length! 255 256config SYS_I2C_EEPROM_ADDR_OVERFLOW 257 hex "EEPROM Address Overflow" 258 default 0 259 help 260 EEPROM chips that implement "address overflow" are ones 261 like Catalyst 24WC04/08/16 which has 9/10/11 bits of 262 address and the extra bits end up in the "chip address" bit 263 slots. This makes a 24WC08 (1Kbyte) chip look like four 256 264 byte chips. 265 266endif 267 268 269endmenu 270