1# 2# Multifunction miscellaneous devices 3# 4 5menu "Multifunction device drivers" 6 7config MISC 8 bool "Enable Driver Model for Misc drivers" 9 depends on DM 10 help 11 Enable driver model for miscellaneous devices. This class is 12 used only for those do not fit other more general classes. A 13 set of generic read, write and ioctl methods may be used to 14 access the device. 15 16config SPL_MISC 17 bool "Enable Driver Model for Misc drivers in SPL" 18 depends on SPL_DM 19 help 20 Enable driver model for miscellaneous devices. This class is 21 used only for those do not fit other more general classes. A 22 set of generic read, write and ioctl methods may be used to 23 access the device. 24 25config TPL_MISC 26 bool "Enable Driver Model for Misc drivers in TPL" 27 depends on TPL_DM 28 help 29 Enable driver model for miscellaneous devices. This class is 30 used only for those do not fit other more general classes. A 31 set of generic read, write and ioctl methods may be used to 32 access the device. 33 34config ALTERA_SYSID 35 bool "Altera Sysid support" 36 depends on MISC 37 help 38 Select this to enable a sysid for Altera devices. Please find 39 details on the "Embedded Peripherals IP User Guide" of Altera. 40 41config ATSHA204A 42 bool "Support for Atmel ATSHA204A module" 43 depends on MISC 44 help 45 Enable support for I2C connected Atmel's ATSHA204A 46 CryptoAuthentication module found for example on the Turris Omnia 47 board. 48 49config ROCKCHIP_EFUSE 50 bool "Rockchip e-fuse support" 51 depends on MISC 52 help 53 Enable (read-only) access for the e-fuse block found in Rockchip 54 SoCs: accesses can either be made using byte addressing and a length 55 or through child-nodes that are generated based on the e-fuse map 56 retrieved from the DTS. 57 58 This driver currently supports the RK3399 only, but can easily be 59 extended (by porting the read function from the Linux kernel sources) 60 to support other recent Rockchip devices. 61 62config ROCKCHIP_OTP 63 bool "Rockchip OTP Support" 64 depends on MISC 65 help 66 This is a simple drive to dump specified values of Rockchip SoC 67 from otp, such as cpu-leakage. 68 69config SPL_ROCKCHIP_SECURE_OTP 70 bool "Rockchip Secure OTP Support in spl" 71 depends on SPL_MISC 72 help 73 Support read & write secure otp in spl. 74 75config CMD_CROS_EC 76 bool "Enable crosec command" 77 depends on CROS_EC 78 help 79 Enable command-line access to the Chrome OS EC (Embedded 80 Controller). This provides the 'crosec' command which has 81 a number of sub-commands for performing EC tasks such as 82 updating its flash, accessing a small saved context area 83 and talking to the I2C bus behind the EC (if there is one). 84 85config CROS_EC 86 bool "Enable Chrome OS EC" 87 help 88 Enable access to the Chrome OS EC. This is a separate 89 microcontroller typically available on a SPI bus on Chromebooks. It 90 provides access to the keyboard, some internal storage and may 91 control access to the battery and main PMIC depending on the 92 device. You can use the 'crosec' command to access it. 93 94config CROS_EC_I2C 95 bool "Enable Chrome OS EC I2C driver" 96 depends on CROS_EC 97 help 98 Enable I2C access to the Chrome OS EC. This is used on older 99 ARM Chromebooks such as snow and spring before the standard bus 100 changed to SPI. The EC will accept commands across the I2C using 101 a special message protocol, and provide responses. 102 103config CROS_EC_LPC 104 bool "Enable Chrome OS EC LPC driver" 105 depends on CROS_EC 106 help 107 Enable I2C access to the Chrome OS EC. This is used on x86 108 Chromebooks such as link and falco. The keyboard is provided 109 through a legacy port interface, so on x86 machines the main 110 function of the EC is power and thermal management. 111 112config CROS_EC_SANDBOX 113 bool "Enable Chrome OS EC sandbox driver" 114 depends on CROS_EC && SANDBOX 115 help 116 Enable a sandbox emulation of the Chrome OS EC. This supports 117 keyboard (use the -l flag to enable the LCD), verified boot context, 118 EC flash read/write/erase support and a few other things. It is 119 enough to perform a Chrome OS verified boot on sandbox. 120 121config CROS_EC_SPI 122 bool "Enable Chrome OS EC SPI driver" 123 depends on CROS_EC 124 help 125 Enable SPI access to the Chrome OS EC. This is used on newer 126 ARM Chromebooks such as pit, pi and nyan-big. The SPI interface 127 provides a faster and more robust interface than I2C but the bugs 128 are less interesting. 129 130config DS4510 131 bool "Enable support for DS4510 CPU supervisor" 132 help 133 Enable support for the Maxim DS4510 CPU supervisor. It has an 134 integrated 64-byte EEPROM, four programmable non-volatile I/O pins 135 and a configurable timer for the supervisor function. The device is 136 connected over I2C. 137 138config FSL_SEC_MON 139 bool "Enable FSL SEC_MON Driver" 140 help 141 Freescale Security Monitor block is responsible for monitoring 142 system states. 143 Security Monitor can be transitioned on any security failures, 144 like software violations or hardware security violations. 145 146config MXC_OCOTP 147 bool "Enable MXC OCOTP Driver" 148 help 149 If you say Y here, you will get support for the One Time 150 Programmable memory pages that are stored on the some 151 Freescale i.MX processors. 152 153config NUVOTON_NCT6102D 154 bool "Enable Nuvoton NCT6102D Super I/O driver" 155 help 156 If you say Y here, you will get support for the Nuvoton 157 NCT6102D Super I/O driver. This can be used to enable or 158 disable the legacy UART, the watchdog or other devices 159 in the Nuvoton Super IO chips on X86 platforms. 160 161config PWRSEQ 162 bool "Enable power-sequencing drivers" 163 depends on DM 164 help 165 Power-sequencing drivers provide support for controlling power for 166 devices. They are typically referenced by a phandle from another 167 device. When the device is started up, its power sequence can be 168 initiated. 169 170config SPL_PWRSEQ 171 bool "Enable power-sequencing drivers for SPL" 172 depends on PWRSEQ 173 help 174 Power-sequencing drivers provide support for controlling power for 175 devices. They are typically referenced by a phandle from another 176 device. When the device is started up, its power sequence can be 177 initiated. 178 179config PCA9551_LED 180 bool "Enable PCA9551 LED driver" 181 help 182 Enable driver for PCA9551 LED controller. This controller 183 is connected via I2C. So I2C needs to be enabled. 184 185config PCA9551_I2C_ADDR 186 hex "I2C address of PCA9551 LED controller" 187 depends on PCA9551_LED 188 default 0x60 189 help 190 The I2C address of the PCA9551 LED controller. 191 192config TEGRA_CAR 193 bool "Enable support for the Tegra CAR driver" 194 depends on TEGRA_NO_BPMP 195 help 196 The Tegra CAR (Clock and Reset Controller) is a HW module that 197 controls almost all clocks and resets in a Tegra SoC. 198 199config TEGRA186_BPMP 200 bool "Enable support for the Tegra186 BPMP driver" 201 depends on TEGRA186 202 help 203 The Tegra BPMP (Boot and Power Management Processor) is a separate 204 auxiliary CPU embedded into Tegra to perform power management work, 205 and controls related features such as clocks, resets, power domains, 206 PMIC I2C bus, etc. This driver provides the core low-level 207 communication path by which feature-specific drivers (such as clock) 208 can make requests to the BPMP. This driver is similar to an MFD 209 driver in the Linux kernel. 210 211config WINBOND_W83627 212 bool "Enable Winbond Super I/O driver" 213 help 214 If you say Y here, you will get support for the Winbond 215 W83627 Super I/O driver. This can be used to enable the 216 legacy UART or other devices in the Winbond Super IO chips 217 on X86 platforms. 218 219config QFW 220 bool 221 help 222 Hidden option to enable QEMU fw_cfg interface. This will be selected by 223 either CONFIG_CMD_QFW or CONFIG_GENERATE_ACPI_TABLE. 224 225config I2C_EEPROM 226 bool "Enable driver for generic I2C-attached EEPROMs" 227 depends on MISC 228 help 229 Enable a generic driver for EEPROMs attached via I2C. 230 231if I2C_EEPROM 232 233config SYS_I2C_EEPROM_ADDR 234 hex "Chip address of the EEPROM device" 235 default 0 236 237config SYS_I2C_EEPROM_BUS 238 int "I2C bus of the EEPROM device." 239 default 0 240 241config SYS_EEPROM_SIZE 242 int "Size in bytes of the EEPROM device" 243 default 256 244 245config SYS_EEPROM_PAGE_WRITE_BITS 246 int "Number of bits used to address bytes in a single page" 247 default 0 248 help 249 The EEPROM page size is 2^SYS_EEPROM_PAGE_WRITE_BITS. 250 A 64 byte page, for example would require six bits. 251 252config SYS_EEPROM_PAGE_WRITE_DELAY_MS 253 int "Number of milliseconds to delay between page writes" 254 default 0 255 256config SYS_I2C_EEPROM_ADDR_LEN 257 int "Length in bytes of the EEPROM memory array address" 258 default 1 259 help 260 Note: This is NOT the chip address length! 261 262config SYS_I2C_EEPROM_ADDR_OVERFLOW 263 hex "EEPROM Address Overflow" 264 default 0 265 help 266 EEPROM chips that implement "address overflow" are ones 267 like Catalyst 24WC04/08/16 which has 9/10/11 bits of 268 address and the extra bits end up in the "chip address" bit 269 slots. This makes a 24WC08 (1Kbyte) chip look like four 256 270 byte chips. 271 272endif 273 274 275endmenu 276