1# 2# Multifunction miscellaneous devices 3# 4 5menu "Multifunction device drivers" 6 7config MISC 8 bool "Enable Driver Model for Misc drivers" 9 depends on DM 10 help 11 Enable driver model for miscellaneous devices. This class is 12 used only for those do not fit other more general classes. A 13 set of generic read, write and ioctl methods may be used to 14 access the device. 15 16config SPL_MISC 17 bool "Enable Driver Model for Misc drivers in SPL" 18 depends on SPL_DM 19 help 20 Enable driver model for miscellaneous devices. This class is 21 used only for those do not fit other more general classes. A 22 set of generic read, write and ioctl methods may be used to 23 access the device. 24 25config TPL_MISC 26 bool "Enable Driver Model for Misc drivers in TPL" 27 depends on TPL_DM 28 help 29 Enable driver model for miscellaneous devices. This class is 30 used only for those do not fit other more general classes. A 31 set of generic read, write and ioctl methods may be used to 32 access the device. 33 34config MISC_DECOMPRESS 35 bool "Enable misc decompress driver support" 36 depends on MISC 37 help 38 Enable misc decompress driver support. 39 40config SPL_MISC_DECOMPRESS 41 bool "Enable misc decompress driver support in SPL" 42 depends on SPL_MISC 43 help 44 Enable misc decompress driver support in spl. 45 46config ALTERA_SYSID 47 bool "Altera Sysid support" 48 depends on MISC 49 help 50 Select this to enable a sysid for Altera devices. Please find 51 details on the "Embedded Peripherals IP User Guide" of Altera. 52 53config ATSHA204A 54 bool "Support for Atmel ATSHA204A module" 55 depends on MISC 56 help 57 Enable support for I2C connected Atmel's ATSHA204A 58 CryptoAuthentication module found for example on the Turris Omnia 59 board. 60 61config ROCKCHIP_EFUSE 62 bool "Rockchip e-fuse support" 63 depends on MISC 64 help 65 Enable (read-only) access for the e-fuse block found in Rockchip 66 SoCs: accesses can either be made using byte addressing and a length 67 or through child-nodes that are generated based on the e-fuse map 68 retrieved from the DTS. 69 70 This driver currently supports the RK3399 only, but can easily be 71 extended (by porting the read function from the Linux kernel sources) 72 to support other recent Rockchip devices. 73 74config ROCKCHIP_OTP 75 bool "Rockchip OTP Support" 76 depends on MISC 77 help 78 This is a simple drive to dump specified values of Rockchip SoC 79 from otp, such as cpu-leakage. 80 81config ROCKCHIP_HW_DECOMPRESS 82 bool "Rockchip HardWare Decompress Support" 83 depends on MISC_DECOMPRESS 84 help 85 This driver support Decompress IP built-in Rockchip SoC, support 86 LZ4, GZIP, PNG, ZLIB. 87 88config ROCKCHIP_PM_CONFIG 89 bool "Rockchip PM Config Support" 90 depends on ARM_CPU_SUSPEND 91 help 92 This driver supports to configure parameters of system sleep. 93 94config SPL_ROCKCHIP_HW_DECOMPRESS 95 bool "Rockchip HardWare Decompress Support" 96 depends on SPL_MISC_DECOMPRESS 97 help 98 This driver support Decompress IP built-in Rockchip SoC, support 99 LZ4, GZIP, PNG, ZLIB. 100 101config ROCKCHIP_SECURE_OTP 102 bool "Rockchip Secure OTP Support" 103 depends on MISC && !OPTEE_CLIENT 104 help 105 Support read & write secure otp. 106 107config SPL_ROCKCHIP_SECURE_OTP 108 bool "Rockchip Secure OTP Support in spl" 109 depends on SPL_MISC 110 help 111 Support read & write secure otp in spl. 112 113config SPL_OTP_DISABLE_SD 114 bool "Rockchip disable sd upgrade Support" 115 depends on SPL_ROCKCHIP_SECURE_OTP 116 default n 117 help 118 Support write otp to disable sd upgrade. 119 120config SPL_OTP_DISABLE_USB 121 bool "Rockchip disable usb upgrade Support" 122 depends on SPL_ROCKCHIP_SECURE_OTP 123 default n 124 help 125 Support write otp to disable usb upgrade. 126 127config SPL_OTP_DISABLE_UART 128 bool "Rockchip disable uart upgrade Support" 129 depends on SPL_ROCKCHIP_SECURE_OTP 130 default n 131 help 132 Support write otp to disable uart upgrade. 133 134config SPL_OTP_DISABLE_SPI2APB 135 bool "Rockchip disable spi2apb upgrade Support" 136 depends on SPL_ROCKCHIP_SECURE_OTP 137 default n 138 help 139 Support write otp to disable spi2apb upgrade. 140 141config CMD_CROS_EC 142 bool "Enable crosec command" 143 depends on CROS_EC 144 help 145 Enable command-line access to the Chrome OS EC (Embedded 146 Controller). This provides the 'crosec' command which has 147 a number of sub-commands for performing EC tasks such as 148 updating its flash, accessing a small saved context area 149 and talking to the I2C bus behind the EC (if there is one). 150 151config CROS_EC 152 bool "Enable Chrome OS EC" 153 help 154 Enable access to the Chrome OS EC. This is a separate 155 microcontroller typically available on a SPI bus on Chromebooks. It 156 provides access to the keyboard, some internal storage and may 157 control access to the battery and main PMIC depending on the 158 device. You can use the 'crosec' command to access it. 159 160config CROS_EC_I2C 161 bool "Enable Chrome OS EC I2C driver" 162 depends on CROS_EC 163 help 164 Enable I2C access to the Chrome OS EC. This is used on older 165 ARM Chromebooks such as snow and spring before the standard bus 166 changed to SPI. The EC will accept commands across the I2C using 167 a special message protocol, and provide responses. 168 169config CROS_EC_LPC 170 bool "Enable Chrome OS EC LPC driver" 171 depends on CROS_EC 172 help 173 Enable I2C access to the Chrome OS EC. This is used on x86 174 Chromebooks such as link and falco. The keyboard is provided 175 through a legacy port interface, so on x86 machines the main 176 function of the EC is power and thermal management. 177 178config CROS_EC_SANDBOX 179 bool "Enable Chrome OS EC sandbox driver" 180 depends on CROS_EC && SANDBOX 181 help 182 Enable a sandbox emulation of the Chrome OS EC. This supports 183 keyboard (use the -l flag to enable the LCD), verified boot context, 184 EC flash read/write/erase support and a few other things. It is 185 enough to perform a Chrome OS verified boot on sandbox. 186 187config CROS_EC_SPI 188 bool "Enable Chrome OS EC SPI driver" 189 depends on CROS_EC 190 help 191 Enable SPI access to the Chrome OS EC. This is used on newer 192 ARM Chromebooks such as pit, pi and nyan-big. The SPI interface 193 provides a faster and more robust interface than I2C but the bugs 194 are less interesting. 195 196config DS4510 197 bool "Enable support for DS4510 CPU supervisor" 198 help 199 Enable support for the Maxim DS4510 CPU supervisor. It has an 200 integrated 64-byte EEPROM, four programmable non-volatile I/O pins 201 and a configurable timer for the supervisor function. The device is 202 connected over I2C. 203 204config FSL_SEC_MON 205 bool "Enable FSL SEC_MON Driver" 206 help 207 Freescale Security Monitor block is responsible for monitoring 208 system states. 209 Security Monitor can be transitioned on any security failures, 210 like software violations or hardware security violations. 211 212config MXC_OCOTP 213 bool "Enable MXC OCOTP Driver" 214 help 215 If you say Y here, you will get support for the One Time 216 Programmable memory pages that are stored on the some 217 Freescale i.MX processors. 218 219config NUVOTON_NCT6102D 220 bool "Enable Nuvoton NCT6102D Super I/O driver" 221 help 222 If you say Y here, you will get support for the Nuvoton 223 NCT6102D Super I/O driver. This can be used to enable or 224 disable the legacy UART, the watchdog or other devices 225 in the Nuvoton Super IO chips on X86 platforms. 226 227config PWRSEQ 228 bool "Enable power-sequencing drivers" 229 depends on DM 230 help 231 Power-sequencing drivers provide support for controlling power for 232 devices. They are typically referenced by a phandle from another 233 device. When the device is started up, its power sequence can be 234 initiated. 235 236config SPL_PWRSEQ 237 bool "Enable power-sequencing drivers for SPL" 238 depends on PWRSEQ 239 help 240 Power-sequencing drivers provide support for controlling power for 241 devices. They are typically referenced by a phandle from another 242 device. When the device is started up, its power sequence can be 243 initiated. 244 245config PCA9551_LED 246 bool "Enable PCA9551 LED driver" 247 help 248 Enable driver for PCA9551 LED controller. This controller 249 is connected via I2C. So I2C needs to be enabled. 250 251config PCA9551_I2C_ADDR 252 hex "I2C address of PCA9551 LED controller" 253 depends on PCA9551_LED 254 default 0x60 255 help 256 The I2C address of the PCA9551 LED controller. 257 258config TEGRA_CAR 259 bool "Enable support for the Tegra CAR driver" 260 depends on TEGRA_NO_BPMP 261 help 262 The Tegra CAR (Clock and Reset Controller) is a HW module that 263 controls almost all clocks and resets in a Tegra SoC. 264 265config TEGRA186_BPMP 266 bool "Enable support for the Tegra186 BPMP driver" 267 depends on TEGRA186 268 help 269 The Tegra BPMP (Boot and Power Management Processor) is a separate 270 auxiliary CPU embedded into Tegra to perform power management work, 271 and controls related features such as clocks, resets, power domains, 272 PMIC I2C bus, etc. This driver provides the core low-level 273 communication path by which feature-specific drivers (such as clock) 274 can make requests to the BPMP. This driver is similar to an MFD 275 driver in the Linux kernel. 276 277config WINBOND_W83627 278 bool "Enable Winbond Super I/O driver" 279 help 280 If you say Y here, you will get support for the Winbond 281 W83627 Super I/O driver. This can be used to enable the 282 legacy UART or other devices in the Winbond Super IO chips 283 on X86 platforms. 284 285config QFW 286 bool 287 help 288 Hidden option to enable QEMU fw_cfg interface. This will be selected by 289 either CONFIG_CMD_QFW or CONFIG_GENERATE_ACPI_TABLE. 290 291config I2C_EEPROM 292 bool "Enable driver for generic I2C-attached EEPROMs" 293 depends on MISC 294 help 295 Enable a generic driver for EEPROMs attached via I2C. 296 297if I2C_EEPROM 298 299config SYS_I2C_EEPROM_ADDR 300 hex "Chip address of the EEPROM device" 301 default 0 302 303config SYS_I2C_EEPROM_BUS 304 int "I2C bus of the EEPROM device." 305 default 0 306 307config SYS_EEPROM_SIZE 308 int "Size in bytes of the EEPROM device" 309 default 256 310 311config SYS_EEPROM_PAGE_WRITE_BITS 312 int "Number of bits used to address bytes in a single page" 313 default 0 314 help 315 The EEPROM page size is 2^SYS_EEPROM_PAGE_WRITE_BITS. 316 A 64 byte page, for example would require six bits. 317 318config SYS_EEPROM_PAGE_WRITE_DELAY_MS 319 int "Number of milliseconds to delay between page writes" 320 default 0 321 322config SYS_I2C_EEPROM_ADDR_LEN 323 int "Length in bytes of the EEPROM memory array address" 324 default 1 325 help 326 Note: This is NOT the chip address length! 327 328config SYS_I2C_EEPROM_ADDR_OVERFLOW 329 hex "EEPROM Address Overflow" 330 default 0 331 help 332 EEPROM chips that implement "address overflow" are ones 333 like Catalyst 24WC04/08/16 which has 9/10/11 bits of 334 address and the extra bits end up in the "chip address" bit 335 slots. This makes a 24WC08 (1Kbyte) chip look like four 256 336 byte chips. 337 338endif 339 340 341endmenu 342