1# 2# Multifunction miscellaneous devices 3# 4 5menu "Multifunction device drivers" 6 7config MISC 8 bool "Enable Driver Model for Misc drivers" 9 depends on DM 10 help 11 Enable driver model for miscellaneous devices. This class is 12 used only for those do not fit other more general classes. A 13 set of generic read, write and ioctl methods may be used to 14 access the device. 15 16config SPL_MISC 17 bool "Enable Driver Model for Misc drivers in SPL" 18 depends on SPL_DM 19 help 20 Enable driver model for miscellaneous devices. This class is 21 used only for those do not fit other more general classes. A 22 set of generic read, write and ioctl methods may be used to 23 access the device. 24 25config TPL_MISC 26 bool "Enable Driver Model for Misc drivers in TPL" 27 depends on TPL_DM 28 help 29 Enable driver model for miscellaneous devices. This class is 30 used only for those do not fit other more general classes. A 31 set of generic read, write and ioctl methods may be used to 32 access the device. 33 34config MISC_DECOMPRESS 35 bool "Enable misc decompress driver support" 36 depends on MISC 37 help 38 Enable misc decompress driver support. 39 40config SPL_MISC_DECOMPRESS 41 bool "Enable misc decompress driver support in SPL" 42 depends on SPL_MISC 43 help 44 Enable misc decompress driver support in spl. 45 46config ALTERA_SYSID 47 bool "Altera Sysid support" 48 depends on MISC 49 help 50 Select this to enable a sysid for Altera devices. Please find 51 details on the "Embedded Peripherals IP User Guide" of Altera. 52 53config ATSHA204A 54 bool "Support for Atmel ATSHA204A module" 55 depends on MISC 56 help 57 Enable support for I2C connected Atmel's ATSHA204A 58 CryptoAuthentication module found for example on the Turris Omnia 59 board. 60 61config ROCKCHIP_EFUSE 62 bool "Rockchip e-fuse support" 63 depends on MISC 64 help 65 Enable (read-only) access for the e-fuse block found in Rockchip 66 SoCs: accesses can either be made using byte addressing and a length 67 or through child-nodes that are generated based on the e-fuse map 68 retrieved from the DTS. 69 70 This driver currently supports the RK3399 only, but can easily be 71 extended (by porting the read function from the Linux kernel sources) 72 to support other recent Rockchip devices. 73 74config ROCKCHIP_OTP 75 bool "Rockchip OTP Support" 76 depends on MISC 77 help 78 This is a simple drive to dump specified values of Rockchip SoC 79 from otp, such as cpu-leakage. 80 81config ROCKCHIP_HW_DECOMPRESS 82 bool "Rockchip HardWare Decompress Support" 83 depends on MISC_DECOMPRESS 84 help 85 This driver support Decompress IP built-in Rockchip SoC, support 86 LZ4, GZIP, PNG, ZLIB. 87 88config SPL_ROCKCHIP_HW_DECOMPRESS 89 bool "Rockchip HardWare Decompress Support" 90 depends on SPL_MISC_DECOMPRESS 91 help 92 This driver support Decompress IP built-in Rockchip SoC, support 93 LZ4, GZIP, PNG, ZLIB. 94 95config SPL_ROCKCHIP_SECURE_OTP_V1 96 bool "Rockchip Secure OTP Version 1 Support in spl" 97 depends on SPL_MISC 98 help 99 Support read & write secure otp in spl. Support platforms: rk3308, 100 rk3326, px30, rk3568, rk3566. 101 102config SPL_ROCKCHIP_SECURE_OTP_V2 103 bool "Rockchip Secure OTP Version 2 Support in spl" 104 depends on SPL_MISC 105 help 106 Support read & write secure otp in spl. Support platforms: rv1126. 107 108config CMD_CROS_EC 109 bool "Enable crosec command" 110 depends on CROS_EC 111 help 112 Enable command-line access to the Chrome OS EC (Embedded 113 Controller). This provides the 'crosec' command which has 114 a number of sub-commands for performing EC tasks such as 115 updating its flash, accessing a small saved context area 116 and talking to the I2C bus behind the EC (if there is one). 117 118config CROS_EC 119 bool "Enable Chrome OS EC" 120 help 121 Enable access to the Chrome OS EC. This is a separate 122 microcontroller typically available on a SPI bus on Chromebooks. It 123 provides access to the keyboard, some internal storage and may 124 control access to the battery and main PMIC depending on the 125 device. You can use the 'crosec' command to access it. 126 127config CROS_EC_I2C 128 bool "Enable Chrome OS EC I2C driver" 129 depends on CROS_EC 130 help 131 Enable I2C access to the Chrome OS EC. This is used on older 132 ARM Chromebooks such as snow and spring before the standard bus 133 changed to SPI. The EC will accept commands across the I2C using 134 a special message protocol, and provide responses. 135 136config CROS_EC_LPC 137 bool "Enable Chrome OS EC LPC driver" 138 depends on CROS_EC 139 help 140 Enable I2C access to the Chrome OS EC. This is used on x86 141 Chromebooks such as link and falco. The keyboard is provided 142 through a legacy port interface, so on x86 machines the main 143 function of the EC is power and thermal management. 144 145config CROS_EC_SANDBOX 146 bool "Enable Chrome OS EC sandbox driver" 147 depends on CROS_EC && SANDBOX 148 help 149 Enable a sandbox emulation of the Chrome OS EC. This supports 150 keyboard (use the -l flag to enable the LCD), verified boot context, 151 EC flash read/write/erase support and a few other things. It is 152 enough to perform a Chrome OS verified boot on sandbox. 153 154config CROS_EC_SPI 155 bool "Enable Chrome OS EC SPI driver" 156 depends on CROS_EC 157 help 158 Enable SPI access to the Chrome OS EC. This is used on newer 159 ARM Chromebooks such as pit, pi and nyan-big. The SPI interface 160 provides a faster and more robust interface than I2C but the bugs 161 are less interesting. 162 163config DS4510 164 bool "Enable support for DS4510 CPU supervisor" 165 help 166 Enable support for the Maxim DS4510 CPU supervisor. It has an 167 integrated 64-byte EEPROM, four programmable non-volatile I/O pins 168 and a configurable timer for the supervisor function. The device is 169 connected over I2C. 170 171config FSL_SEC_MON 172 bool "Enable FSL SEC_MON Driver" 173 help 174 Freescale Security Monitor block is responsible for monitoring 175 system states. 176 Security Monitor can be transitioned on any security failures, 177 like software violations or hardware security violations. 178 179config MXC_OCOTP 180 bool "Enable MXC OCOTP Driver" 181 help 182 If you say Y here, you will get support for the One Time 183 Programmable memory pages that are stored on the some 184 Freescale i.MX processors. 185 186config NUVOTON_NCT6102D 187 bool "Enable Nuvoton NCT6102D Super I/O driver" 188 help 189 If you say Y here, you will get support for the Nuvoton 190 NCT6102D Super I/O driver. This can be used to enable or 191 disable the legacy UART, the watchdog or other devices 192 in the Nuvoton Super IO chips on X86 platforms. 193 194config PWRSEQ 195 bool "Enable power-sequencing drivers" 196 depends on DM 197 help 198 Power-sequencing drivers provide support for controlling power for 199 devices. They are typically referenced by a phandle from another 200 device. When the device is started up, its power sequence can be 201 initiated. 202 203config SPL_PWRSEQ 204 bool "Enable power-sequencing drivers for SPL" 205 depends on PWRSEQ 206 help 207 Power-sequencing drivers provide support for controlling power for 208 devices. They are typically referenced by a phandle from another 209 device. When the device is started up, its power sequence can be 210 initiated. 211 212config PCA9551_LED 213 bool "Enable PCA9551 LED driver" 214 help 215 Enable driver for PCA9551 LED controller. This controller 216 is connected via I2C. So I2C needs to be enabled. 217 218config PCA9551_I2C_ADDR 219 hex "I2C address of PCA9551 LED controller" 220 depends on PCA9551_LED 221 default 0x60 222 help 223 The I2C address of the PCA9551 LED controller. 224 225config TEGRA_CAR 226 bool "Enable support for the Tegra CAR driver" 227 depends on TEGRA_NO_BPMP 228 help 229 The Tegra CAR (Clock and Reset Controller) is a HW module that 230 controls almost all clocks and resets in a Tegra SoC. 231 232config TEGRA186_BPMP 233 bool "Enable support for the Tegra186 BPMP driver" 234 depends on TEGRA186 235 help 236 The Tegra BPMP (Boot and Power Management Processor) is a separate 237 auxiliary CPU embedded into Tegra to perform power management work, 238 and controls related features such as clocks, resets, power domains, 239 PMIC I2C bus, etc. This driver provides the core low-level 240 communication path by which feature-specific drivers (such as clock) 241 can make requests to the BPMP. This driver is similar to an MFD 242 driver in the Linux kernel. 243 244config WINBOND_W83627 245 bool "Enable Winbond Super I/O driver" 246 help 247 If you say Y here, you will get support for the Winbond 248 W83627 Super I/O driver. This can be used to enable the 249 legacy UART or other devices in the Winbond Super IO chips 250 on X86 platforms. 251 252config QFW 253 bool 254 help 255 Hidden option to enable QEMU fw_cfg interface. This will be selected by 256 either CONFIG_CMD_QFW or CONFIG_GENERATE_ACPI_TABLE. 257 258config I2C_EEPROM 259 bool "Enable driver for generic I2C-attached EEPROMs" 260 depends on MISC 261 help 262 Enable a generic driver for EEPROMs attached via I2C. 263 264if I2C_EEPROM 265 266config SYS_I2C_EEPROM_ADDR 267 hex "Chip address of the EEPROM device" 268 default 0 269 270config SYS_I2C_EEPROM_BUS 271 int "I2C bus of the EEPROM device." 272 default 0 273 274config SYS_EEPROM_SIZE 275 int "Size in bytes of the EEPROM device" 276 default 256 277 278config SYS_EEPROM_PAGE_WRITE_BITS 279 int "Number of bits used to address bytes in a single page" 280 default 0 281 help 282 The EEPROM page size is 2^SYS_EEPROM_PAGE_WRITE_BITS. 283 A 64 byte page, for example would require six bits. 284 285config SYS_EEPROM_PAGE_WRITE_DELAY_MS 286 int "Number of milliseconds to delay between page writes" 287 default 0 288 289config SYS_I2C_EEPROM_ADDR_LEN 290 int "Length in bytes of the EEPROM memory array address" 291 default 1 292 help 293 Note: This is NOT the chip address length! 294 295config SYS_I2C_EEPROM_ADDR_OVERFLOW 296 hex "EEPROM Address Overflow" 297 default 0 298 help 299 EEPROM chips that implement "address overflow" are ones 300 like Catalyst 24WC04/08/16 which has 9/10/11 bits of 301 address and the extra bits end up in the "chip address" bit 302 slots. This makes a 24WC08 (1Kbyte) chip look like four 256 303 byte chips. 304 305endif 306 307 308endmenu 309