1# 2# Multifunction miscellaneous devices 3# 4 5menu "Multifunction device drivers" 6 7config MISC 8 bool "Enable Driver Model for Misc drivers" 9 depends on DM 10 help 11 Enable driver model for miscellaneous devices. This class is 12 used only for those do not fit other more general classes. A 13 set of generic read, write and ioctl methods may be used to 14 access the device. 15 16config SPL_MISC 17 bool "Enable Driver Model for Misc drivers in SPL" 18 depends on SPL_DM 19 help 20 Enable driver model for miscellaneous devices. This class is 21 used only for those do not fit other more general classes. A 22 set of generic read, write and ioctl methods may be used to 23 access the device. 24 25config TPL_MISC 26 bool "Enable Driver Model for Misc drivers in TPL" 27 depends on TPL_DM 28 help 29 Enable driver model for miscellaneous devices. This class is 30 used only for those do not fit other more general classes. A 31 set of generic read, write and ioctl methods may be used to 32 access the device. 33 34config MISC_DECOMPRESS 35 bool "Enable misc decompress driver support" 36 depends on MISC 37 help 38 Enable misc decompress driver support. 39 40config SPL_MISC_DECOMPRESS 41 bool "Enable misc decompress driver support in SPL" 42 depends on SPL_MISC 43 help 44 Enable misc decompress driver support in spl. 45 46config ALTERA_SYSID 47 bool "Altera Sysid support" 48 depends on MISC 49 help 50 Select this to enable a sysid for Altera devices. Please find 51 details on the "Embedded Peripherals IP User Guide" of Altera. 52 53config ATSHA204A 54 bool "Support for Atmel ATSHA204A module" 55 depends on MISC 56 help 57 Enable support for I2C connected Atmel's ATSHA204A 58 CryptoAuthentication module found for example on the Turris Omnia 59 board. 60 61config ROCKCHIP_EFUSE 62 bool "Rockchip e-fuse support" 63 depends on MISC 64 help 65 Enable (read-only) access for the e-fuse block found in Rockchip 66 SoCs: accesses can either be made using byte addressing and a length 67 or through child-nodes that are generated based on the e-fuse map 68 retrieved from the DTS. 69 70 This driver currently supports the RK3399 only, but can easily be 71 extended (by porting the read function from the Linux kernel sources) 72 to support other recent Rockchip devices. 73 74config ROCKCHIP_OTP 75 bool "Rockchip OTP Support" 76 depends on MISC 77 help 78 This is a simple drive to dump specified values of Rockchip SoC 79 from otp, such as cpu-leakage. 80 81config ROCKCHIP_HW_DECOMPRESS 82 bool "Rockchip HardWare Decompress Support" 83 depends on MISC_DECOMPRESS 84 help 85 This driver support Decompress IP built-in Rockchip SoC, support 86 LZ4, GZIP, PNG, ZLIB. 87 88config ROCKCHIP_PM_CONFIG 89 bool "Rockchip PM Config Support" 90 depends on ARM_CPU_SUSPEND 91 help 92 This driver supports to configure parameters of system sleep. 93 94config SPL_ROCKCHIP_HW_DECOMPRESS 95 bool "Rockchip HardWare Decompress Support" 96 depends on SPL_MISC_DECOMPRESS 97 help 98 This driver support Decompress IP built-in Rockchip SoC, support 99 LZ4, GZIP, PNG, ZLIB. 100 101config ROCKCHIP_SECURE_OTP 102 bool "Rockchip Secure OTP Support" 103 depends on MISC && !OPTEE_CLIENT 104 help 105 Support read & write secure otp. 106 107config SPL_ROCKCHIP_SECURE_OTP 108 bool "Rockchip Secure OTP Support in spl" 109 depends on SPL_MISC 110 help 111 Support read & write secure otp in spl. 112 113config SPL_OTP_DISABLE_SD 114 bool "Rockchip disable sd upgrade Support" 115 depends on SPL_ROCKCHIP_SECURE_OTP 116 default n 117 help 118 Support write otp to disable sd upgrade. 119 120config SPL_OTP_DISABLE_USB 121 bool "Rockchip disable usb upgrade Support" 122 depends on SPL_ROCKCHIP_SECURE_OTP 123 default n 124 help 125 Support write otp to disable usb upgrade. 126 127config SPL_OTP_DISABLE_UART 128 bool "Rockchip disable uart upgrade Support" 129 depends on SPL_ROCKCHIP_SECURE_OTP 130 default n 131 help 132 Support write otp to disable uart upgrade. 133 134config SPL_OTP_DISABLE_SPI2APB 135 bool "Rockchip disable spi2apb upgrade Support" 136 depends on SPL_ROCKCHIP_SECURE_OTP 137 default n 138 help 139 Support write otp to disable spi2apb upgrade. 140 141config SPL_REVOKE_PUB_KEY 142 bool "Rockchip revoke current public key Support" 143 depends on SPL_ROCKCHIP_SECURE_OTP 144 default n 145 help 146 Support write otp to revoke current public key. 147 148config CMD_CROS_EC 149 bool "Enable crosec command" 150 depends on CROS_EC 151 help 152 Enable command-line access to the Chrome OS EC (Embedded 153 Controller). This provides the 'crosec' command which has 154 a number of sub-commands for performing EC tasks such as 155 updating its flash, accessing a small saved context area 156 and talking to the I2C bus behind the EC (if there is one). 157 158config CROS_EC 159 bool "Enable Chrome OS EC" 160 help 161 Enable access to the Chrome OS EC. This is a separate 162 microcontroller typically available on a SPI bus on Chromebooks. It 163 provides access to the keyboard, some internal storage and may 164 control access to the battery and main PMIC depending on the 165 device. You can use the 'crosec' command to access it. 166 167config CROS_EC_I2C 168 bool "Enable Chrome OS EC I2C driver" 169 depends on CROS_EC 170 help 171 Enable I2C access to the Chrome OS EC. This is used on older 172 ARM Chromebooks such as snow and spring before the standard bus 173 changed to SPI. The EC will accept commands across the I2C using 174 a special message protocol, and provide responses. 175 176config CROS_EC_LPC 177 bool "Enable Chrome OS EC LPC driver" 178 depends on CROS_EC 179 help 180 Enable I2C access to the Chrome OS EC. This is used on x86 181 Chromebooks such as link and falco. The keyboard is provided 182 through a legacy port interface, so on x86 machines the main 183 function of the EC is power and thermal management. 184 185config CROS_EC_SANDBOX 186 bool "Enable Chrome OS EC sandbox driver" 187 depends on CROS_EC && SANDBOX 188 help 189 Enable a sandbox emulation of the Chrome OS EC. This supports 190 keyboard (use the -l flag to enable the LCD), verified boot context, 191 EC flash read/write/erase support and a few other things. It is 192 enough to perform a Chrome OS verified boot on sandbox. 193 194config CROS_EC_SPI 195 bool "Enable Chrome OS EC SPI driver" 196 depends on CROS_EC 197 help 198 Enable SPI access to the Chrome OS EC. This is used on newer 199 ARM Chromebooks such as pit, pi and nyan-big. The SPI interface 200 provides a faster and more robust interface than I2C but the bugs 201 are less interesting. 202 203config DS4510 204 bool "Enable support for DS4510 CPU supervisor" 205 help 206 Enable support for the Maxim DS4510 CPU supervisor. It has an 207 integrated 64-byte EEPROM, four programmable non-volatile I/O pins 208 and a configurable timer for the supervisor function. The device is 209 connected over I2C. 210 211config FSL_SEC_MON 212 bool "Enable FSL SEC_MON Driver" 213 help 214 Freescale Security Monitor block is responsible for monitoring 215 system states. 216 Security Monitor can be transitioned on any security failures, 217 like software violations or hardware security violations. 218 219config MXC_OCOTP 220 bool "Enable MXC OCOTP Driver" 221 help 222 If you say Y here, you will get support for the One Time 223 Programmable memory pages that are stored on the some 224 Freescale i.MX processors. 225 226config NUVOTON_NCT6102D 227 bool "Enable Nuvoton NCT6102D Super I/O driver" 228 help 229 If you say Y here, you will get support for the Nuvoton 230 NCT6102D Super I/O driver. This can be used to enable or 231 disable the legacy UART, the watchdog or other devices 232 in the Nuvoton Super IO chips on X86 platforms. 233 234config PWRSEQ 235 bool "Enable power-sequencing drivers" 236 depends on DM 237 help 238 Power-sequencing drivers provide support for controlling power for 239 devices. They are typically referenced by a phandle from another 240 device. When the device is started up, its power sequence can be 241 initiated. 242 243config SPL_PWRSEQ 244 bool "Enable power-sequencing drivers for SPL" 245 depends on PWRSEQ 246 help 247 Power-sequencing drivers provide support for controlling power for 248 devices. They are typically referenced by a phandle from another 249 device. When the device is started up, its power sequence can be 250 initiated. 251 252config PCA9551_LED 253 bool "Enable PCA9551 LED driver" 254 help 255 Enable driver for PCA9551 LED controller. This controller 256 is connected via I2C. So I2C needs to be enabled. 257 258config PCA9551_I2C_ADDR 259 hex "I2C address of PCA9551 LED controller" 260 depends on PCA9551_LED 261 default 0x60 262 help 263 The I2C address of the PCA9551 LED controller. 264 265config TEGRA_CAR 266 bool "Enable support for the Tegra CAR driver" 267 depends on TEGRA_NO_BPMP 268 help 269 The Tegra CAR (Clock and Reset Controller) is a HW module that 270 controls almost all clocks and resets in a Tegra SoC. 271 272config TEGRA186_BPMP 273 bool "Enable support for the Tegra186 BPMP driver" 274 depends on TEGRA186 275 help 276 The Tegra BPMP (Boot and Power Management Processor) is a separate 277 auxiliary CPU embedded into Tegra to perform power management work, 278 and controls related features such as clocks, resets, power domains, 279 PMIC I2C bus, etc. This driver provides the core low-level 280 communication path by which feature-specific drivers (such as clock) 281 can make requests to the BPMP. This driver is similar to an MFD 282 driver in the Linux kernel. 283 284config WINBOND_W83627 285 bool "Enable Winbond Super I/O driver" 286 help 287 If you say Y here, you will get support for the Winbond 288 W83627 Super I/O driver. This can be used to enable the 289 legacy UART or other devices in the Winbond Super IO chips 290 on X86 platforms. 291 292config QFW 293 bool 294 help 295 Hidden option to enable QEMU fw_cfg interface. This will be selected by 296 either CONFIG_CMD_QFW or CONFIG_GENERATE_ACPI_TABLE. 297 298config I2C_EEPROM 299 bool "Enable driver for generic I2C-attached EEPROMs" 300 depends on MISC 301 help 302 Enable a generic driver for EEPROMs attached via I2C. 303 304if I2C_EEPROM 305 306config SYS_I2C_EEPROM_ADDR 307 hex "Chip address of the EEPROM device" 308 default 0 309 310config SYS_I2C_EEPROM_BUS 311 int "I2C bus of the EEPROM device." 312 default 0 313 314config SYS_EEPROM_SIZE 315 int "Size in bytes of the EEPROM device" 316 default 256 317 318config SYS_EEPROM_PAGE_WRITE_BITS 319 int "Number of bits used to address bytes in a single page" 320 default 0 321 help 322 The EEPROM page size is 2^SYS_EEPROM_PAGE_WRITE_BITS. 323 A 64 byte page, for example would require six bits. 324 325config SYS_EEPROM_PAGE_WRITE_DELAY_MS 326 int "Number of milliseconds to delay between page writes" 327 default 0 328 329config SYS_I2C_EEPROM_ADDR_LEN 330 int "Length in bytes of the EEPROM memory array address" 331 default 1 332 help 333 Note: This is NOT the chip address length! 334 335config SYS_I2C_EEPROM_ADDR_OVERFLOW 336 hex "EEPROM Address Overflow" 337 default 0 338 help 339 EEPROM chips that implement "address overflow" are ones 340 like Catalyst 24WC04/08/16 which has 9/10/11 bits of 341 address and the extra bits end up in the "chip address" bit 342 slots. This makes a 24WC08 (1Kbyte) chip look like four 256 343 byte chips. 344 345endif 346 347 348endmenu 349