1# 2# Multifunction miscellaneous devices 3# 4 5menu "Multifunction device drivers" 6 7config MISC 8 bool "Enable Driver Model for Misc drivers" 9 depends on DM 10 help 11 Enable driver model for miscellaneous devices. This class is 12 used only for those do not fit other more general classes. A 13 set of generic read, write and ioctl methods may be used to 14 access the device. 15 16config SPL_MISC 17 bool "Enable Driver Model for Misc drivers in SPL" 18 depends on SPL_DM 19 help 20 Enable driver model for miscellaneous devices. This class is 21 used only for those do not fit other more general classes. A 22 set of generic read, write and ioctl methods may be used to 23 access the device. 24 25config TPL_MISC 26 bool "Enable Driver Model for Misc drivers in TPL" 27 depends on TPL_DM 28 help 29 Enable driver model for miscellaneous devices. This class is 30 used only for those do not fit other more general classes. A 31 set of generic read, write and ioctl methods may be used to 32 access the device. 33 34config MISC_DECOMPRESS 35 bool "Enable misc decompress driver support" 36 depends on MISC 37 help 38 Enable misc decompress driver support. 39 40config SPL_MISC_DECOMPRESS 41 bool "Enable misc decompress driver support in SPL" 42 depends on SPL_MISC 43 help 44 Enable misc decompress driver support in spl. 45 46config ALTERA_SYSID 47 bool "Altera Sysid support" 48 depends on MISC 49 help 50 Select this to enable a sysid for Altera devices. Please find 51 details on the "Embedded Peripherals IP User Guide" of Altera. 52 53config ATSHA204A 54 bool "Support for Atmel ATSHA204A module" 55 depends on MISC 56 help 57 Enable support for I2C connected Atmel's ATSHA204A 58 CryptoAuthentication module found for example on the Turris Omnia 59 board. 60 61config ROCKCHIP_EFUSE 62 bool "Rockchip e-fuse support" 63 depends on MISC 64 help 65 Enable (read-only) access for the e-fuse block found in Rockchip 66 SoCs: accesses can either be made using byte addressing and a length 67 or through child-nodes that are generated based on the e-fuse map 68 retrieved from the DTS. 69 70 This driver currently supports the RK3399 only, but can easily be 71 extended (by porting the read function from the Linux kernel sources) 72 to support other recent Rockchip devices. 73 74config ROCKCHIP_OTP 75 bool "Rockchip OTP Support" 76 depends on MISC 77 help 78 This is a simple drive to dump specified values of Rockchip SoC 79 from otp, such as cpu-leakage. 80 81config ROCKCHIP_HW_DECOMPRESS 82 bool "Rockchip HardWare Decompress Support" 83 depends on MISC_DECOMPRESS 84 help 85 This driver support Decompress IP built-in Rockchip SoC, support 86 LZ4, GZIP, PNG, ZLIB. 87 88config SPL_ROCKCHIP_HW_DECOMPRESS 89 bool "Rockchip HardWare Decompress Support" 90 depends on SPL_MISC_DECOMPRESS 91 help 92 This driver support Decompress IP built-in Rockchip SoC, support 93 LZ4, GZIP, PNG, ZLIB. 94 95config SPL_ROCKCHIP_SECURE_OTP 96 bool "Rockchip Secure OTP Support in spl" 97 depends on SPL_MISC 98 help 99 Support read & write secure otp in spl. 100 101config CMD_CROS_EC 102 bool "Enable crosec command" 103 depends on CROS_EC 104 help 105 Enable command-line access to the Chrome OS EC (Embedded 106 Controller). This provides the 'crosec' command which has 107 a number of sub-commands for performing EC tasks such as 108 updating its flash, accessing a small saved context area 109 and talking to the I2C bus behind the EC (if there is one). 110 111config CROS_EC 112 bool "Enable Chrome OS EC" 113 help 114 Enable access to the Chrome OS EC. This is a separate 115 microcontroller typically available on a SPI bus on Chromebooks. It 116 provides access to the keyboard, some internal storage and may 117 control access to the battery and main PMIC depending on the 118 device. You can use the 'crosec' command to access it. 119 120config CROS_EC_I2C 121 bool "Enable Chrome OS EC I2C driver" 122 depends on CROS_EC 123 help 124 Enable I2C access to the Chrome OS EC. This is used on older 125 ARM Chromebooks such as snow and spring before the standard bus 126 changed to SPI. The EC will accept commands across the I2C using 127 a special message protocol, and provide responses. 128 129config CROS_EC_LPC 130 bool "Enable Chrome OS EC LPC driver" 131 depends on CROS_EC 132 help 133 Enable I2C access to the Chrome OS EC. This is used on x86 134 Chromebooks such as link and falco. The keyboard is provided 135 through a legacy port interface, so on x86 machines the main 136 function of the EC is power and thermal management. 137 138config CROS_EC_SANDBOX 139 bool "Enable Chrome OS EC sandbox driver" 140 depends on CROS_EC && SANDBOX 141 help 142 Enable a sandbox emulation of the Chrome OS EC. This supports 143 keyboard (use the -l flag to enable the LCD), verified boot context, 144 EC flash read/write/erase support and a few other things. It is 145 enough to perform a Chrome OS verified boot on sandbox. 146 147config CROS_EC_SPI 148 bool "Enable Chrome OS EC SPI driver" 149 depends on CROS_EC 150 help 151 Enable SPI access to the Chrome OS EC. This is used on newer 152 ARM Chromebooks such as pit, pi and nyan-big. The SPI interface 153 provides a faster and more robust interface than I2C but the bugs 154 are less interesting. 155 156config DS4510 157 bool "Enable support for DS4510 CPU supervisor" 158 help 159 Enable support for the Maxim DS4510 CPU supervisor. It has an 160 integrated 64-byte EEPROM, four programmable non-volatile I/O pins 161 and a configurable timer for the supervisor function. The device is 162 connected over I2C. 163 164config FSL_SEC_MON 165 bool "Enable FSL SEC_MON Driver" 166 help 167 Freescale Security Monitor block is responsible for monitoring 168 system states. 169 Security Monitor can be transitioned on any security failures, 170 like software violations or hardware security violations. 171 172config MXC_OCOTP 173 bool "Enable MXC OCOTP Driver" 174 help 175 If you say Y here, you will get support for the One Time 176 Programmable memory pages that are stored on the some 177 Freescale i.MX processors. 178 179config NUVOTON_NCT6102D 180 bool "Enable Nuvoton NCT6102D Super I/O driver" 181 help 182 If you say Y here, you will get support for the Nuvoton 183 NCT6102D Super I/O driver. This can be used to enable or 184 disable the legacy UART, the watchdog or other devices 185 in the Nuvoton Super IO chips on X86 platforms. 186 187config PWRSEQ 188 bool "Enable power-sequencing drivers" 189 depends on DM 190 help 191 Power-sequencing drivers provide support for controlling power for 192 devices. They are typically referenced by a phandle from another 193 device. When the device is started up, its power sequence can be 194 initiated. 195 196config SPL_PWRSEQ 197 bool "Enable power-sequencing drivers for SPL" 198 depends on PWRSEQ 199 help 200 Power-sequencing drivers provide support for controlling power for 201 devices. They are typically referenced by a phandle from another 202 device. When the device is started up, its power sequence can be 203 initiated. 204 205config PCA9551_LED 206 bool "Enable PCA9551 LED driver" 207 help 208 Enable driver for PCA9551 LED controller. This controller 209 is connected via I2C. So I2C needs to be enabled. 210 211config PCA9551_I2C_ADDR 212 hex "I2C address of PCA9551 LED controller" 213 depends on PCA9551_LED 214 default 0x60 215 help 216 The I2C address of the PCA9551 LED controller. 217 218config TEGRA_CAR 219 bool "Enable support for the Tegra CAR driver" 220 depends on TEGRA_NO_BPMP 221 help 222 The Tegra CAR (Clock and Reset Controller) is a HW module that 223 controls almost all clocks and resets in a Tegra SoC. 224 225config TEGRA186_BPMP 226 bool "Enable support for the Tegra186 BPMP driver" 227 depends on TEGRA186 228 help 229 The Tegra BPMP (Boot and Power Management Processor) is a separate 230 auxiliary CPU embedded into Tegra to perform power management work, 231 and controls related features such as clocks, resets, power domains, 232 PMIC I2C bus, etc. This driver provides the core low-level 233 communication path by which feature-specific drivers (such as clock) 234 can make requests to the BPMP. This driver is similar to an MFD 235 driver in the Linux kernel. 236 237config WINBOND_W83627 238 bool "Enable Winbond Super I/O driver" 239 help 240 If you say Y here, you will get support for the Winbond 241 W83627 Super I/O driver. This can be used to enable the 242 legacy UART or other devices in the Winbond Super IO chips 243 on X86 platforms. 244 245config QFW 246 bool 247 help 248 Hidden option to enable QEMU fw_cfg interface. This will be selected by 249 either CONFIG_CMD_QFW or CONFIG_GENERATE_ACPI_TABLE. 250 251config I2C_EEPROM 252 bool "Enable driver for generic I2C-attached EEPROMs" 253 depends on MISC 254 help 255 Enable a generic driver for EEPROMs attached via I2C. 256 257if I2C_EEPROM 258 259config SYS_I2C_EEPROM_ADDR 260 hex "Chip address of the EEPROM device" 261 default 0 262 263config SYS_I2C_EEPROM_BUS 264 int "I2C bus of the EEPROM device." 265 default 0 266 267config SYS_EEPROM_SIZE 268 int "Size in bytes of the EEPROM device" 269 default 256 270 271config SYS_EEPROM_PAGE_WRITE_BITS 272 int "Number of bits used to address bytes in a single page" 273 default 0 274 help 275 The EEPROM page size is 2^SYS_EEPROM_PAGE_WRITE_BITS. 276 A 64 byte page, for example would require six bits. 277 278config SYS_EEPROM_PAGE_WRITE_DELAY_MS 279 int "Number of milliseconds to delay between page writes" 280 default 0 281 282config SYS_I2C_EEPROM_ADDR_LEN 283 int "Length in bytes of the EEPROM memory array address" 284 default 1 285 help 286 Note: This is NOT the chip address length! 287 288config SYS_I2C_EEPROM_ADDR_OVERFLOW 289 hex "EEPROM Address Overflow" 290 default 0 291 help 292 EEPROM chips that implement "address overflow" are ones 293 like Catalyst 24WC04/08/16 which has 9/10/11 bits of 294 address and the extra bits end up in the "chip address" bit 295 slots. This makes a 24WC08 (1Kbyte) chip look like four 256 296 byte chips. 297 298endif 299 300 301endmenu 302