1# 2# Multifunction miscellaneous devices 3# 4 5menu "Multifunction device drivers" 6 7config MISC 8 bool "Enable Driver Model for Misc drivers" 9 depends on DM 10 help 11 Enable driver model for miscellaneous devices. This class is 12 used only for those do not fit other more general classes. A 13 set of generic read, write and ioctl methods may be used to 14 access the device. 15 16config SPL_MISC 17 bool "Enable Driver Model for Misc drivers in SPL" 18 depends on SPL_DM 19 help 20 Enable driver model for miscellaneous devices. This class is 21 used only for those do not fit other more general classes. A 22 set of generic read, write and ioctl methods may be used to 23 access the device. 24 25config ALTERA_SYSID 26 bool "Altera Sysid support" 27 depends on MISC 28 help 29 Select this to enable a sysid for Altera devices. Please find 30 details on the "Embedded Peripherals IP User Guide" of Altera. 31 32config ATSHA204A 33 bool "Support for Atmel ATSHA204A module" 34 depends on MISC 35 help 36 Enable support for I2C connected Atmel's ATSHA204A 37 CryptoAuthentication module found for example on the Turris Omnia 38 board. 39 40config ROCKCHIP_EFUSE 41 bool "Rockchip e-fuse support" 42 depends on MISC 43 help 44 Enable (read-only) access for the e-fuse block found in Rockchip 45 SoCs: accesses can either be made using byte addressing and a length 46 or through child-nodes that are generated based on the e-fuse map 47 retrieved from the DTS. 48 49 This driver currently supports the RK3399 only, but can easily be 50 extended (by porting the read function from the Linux kernel sources) 51 to support other recent Rockchip devices. 52 53config ROCKCHIP_OTP 54 bool "Rockchip OTP Support" 55 depends on MISC 56 help 57 This is a simple drive to dump specified values of Rockchip SoC 58 from otp, such as cpu-leakage. 59 60config CMD_CROS_EC 61 bool "Enable crosec command" 62 depends on CROS_EC 63 help 64 Enable command-line access to the Chrome OS EC (Embedded 65 Controller). This provides the 'crosec' command which has 66 a number of sub-commands for performing EC tasks such as 67 updating its flash, accessing a small saved context area 68 and talking to the I2C bus behind the EC (if there is one). 69 70config CROS_EC 71 bool "Enable Chrome OS EC" 72 help 73 Enable access to the Chrome OS EC. This is a separate 74 microcontroller typically available on a SPI bus on Chromebooks. It 75 provides access to the keyboard, some internal storage and may 76 control access to the battery and main PMIC depending on the 77 device. You can use the 'crosec' command to access it. 78 79config CROS_EC_I2C 80 bool "Enable Chrome OS EC I2C driver" 81 depends on CROS_EC 82 help 83 Enable I2C access to the Chrome OS EC. This is used on older 84 ARM Chromebooks such as snow and spring before the standard bus 85 changed to SPI. The EC will accept commands across the I2C using 86 a special message protocol, and provide responses. 87 88config CROS_EC_LPC 89 bool "Enable Chrome OS EC LPC driver" 90 depends on CROS_EC 91 help 92 Enable I2C access to the Chrome OS EC. This is used on x86 93 Chromebooks such as link and falco. The keyboard is provided 94 through a legacy port interface, so on x86 machines the main 95 function of the EC is power and thermal management. 96 97config CROS_EC_SANDBOX 98 bool "Enable Chrome OS EC sandbox driver" 99 depends on CROS_EC && SANDBOX 100 help 101 Enable a sandbox emulation of the Chrome OS EC. This supports 102 keyboard (use the -l flag to enable the LCD), verified boot context, 103 EC flash read/write/erase support and a few other things. It is 104 enough to perform a Chrome OS verified boot on sandbox. 105 106config CROS_EC_SPI 107 bool "Enable Chrome OS EC SPI driver" 108 depends on CROS_EC 109 help 110 Enable SPI access to the Chrome OS EC. This is used on newer 111 ARM Chromebooks such as pit, pi and nyan-big. The SPI interface 112 provides a faster and more robust interface than I2C but the bugs 113 are less interesting. 114 115config DS4510 116 bool "Enable support for DS4510 CPU supervisor" 117 help 118 Enable support for the Maxim DS4510 CPU supervisor. It has an 119 integrated 64-byte EEPROM, four programmable non-volatile I/O pins 120 and a configurable timer for the supervisor function. The device is 121 connected over I2C. 122 123config FSL_SEC_MON 124 bool "Enable FSL SEC_MON Driver" 125 help 126 Freescale Security Monitor block is responsible for monitoring 127 system states. 128 Security Monitor can be transitioned on any security failures, 129 like software violations or hardware security violations. 130 131config MXC_OCOTP 132 bool "Enable MXC OCOTP Driver" 133 help 134 If you say Y here, you will get support for the One Time 135 Programmable memory pages that are stored on the some 136 Freescale i.MX processors. 137 138config NUVOTON_NCT6102D 139 bool "Enable Nuvoton NCT6102D Super I/O driver" 140 help 141 If you say Y here, you will get support for the Nuvoton 142 NCT6102D Super I/O driver. This can be used to enable or 143 disable the legacy UART, the watchdog or other devices 144 in the Nuvoton Super IO chips on X86 platforms. 145 146config PWRSEQ 147 bool "Enable power-sequencing drivers" 148 depends on DM 149 help 150 Power-sequencing drivers provide support for controlling power for 151 devices. They are typically referenced by a phandle from another 152 device. When the device is started up, its power sequence can be 153 initiated. 154 155config SPL_PWRSEQ 156 bool "Enable power-sequencing drivers for SPL" 157 depends on PWRSEQ 158 help 159 Power-sequencing drivers provide support for controlling power for 160 devices. They are typically referenced by a phandle from another 161 device. When the device is started up, its power sequence can be 162 initiated. 163 164config PCA9551_LED 165 bool "Enable PCA9551 LED driver" 166 help 167 Enable driver for PCA9551 LED controller. This controller 168 is connected via I2C. So I2C needs to be enabled. 169 170config PCA9551_I2C_ADDR 171 hex "I2C address of PCA9551 LED controller" 172 depends on PCA9551_LED 173 default 0x60 174 help 175 The I2C address of the PCA9551 LED controller. 176 177config TEGRA_CAR 178 bool "Enable support for the Tegra CAR driver" 179 depends on TEGRA_NO_BPMP 180 help 181 The Tegra CAR (Clock and Reset Controller) is a HW module that 182 controls almost all clocks and resets in a Tegra SoC. 183 184config TEGRA186_BPMP 185 bool "Enable support for the Tegra186 BPMP driver" 186 depends on TEGRA186 187 help 188 The Tegra BPMP (Boot and Power Management Processor) is a separate 189 auxiliary CPU embedded into Tegra to perform power management work, 190 and controls related features such as clocks, resets, power domains, 191 PMIC I2C bus, etc. This driver provides the core low-level 192 communication path by which feature-specific drivers (such as clock) 193 can make requests to the BPMP. This driver is similar to an MFD 194 driver in the Linux kernel. 195 196config WINBOND_W83627 197 bool "Enable Winbond Super I/O driver" 198 help 199 If you say Y here, you will get support for the Winbond 200 W83627 Super I/O driver. This can be used to enable the 201 legacy UART or other devices in the Winbond Super IO chips 202 on X86 platforms. 203 204config QFW 205 bool 206 help 207 Hidden option to enable QEMU fw_cfg interface. This will be selected by 208 either CONFIG_CMD_QFW or CONFIG_GENERATE_ACPI_TABLE. 209 210config I2C_EEPROM 211 bool "Enable driver for generic I2C-attached EEPROMs" 212 depends on MISC 213 help 214 Enable a generic driver for EEPROMs attached via I2C. 215 216if I2C_EEPROM 217 218config SYS_I2C_EEPROM_ADDR 219 hex "Chip address of the EEPROM device" 220 default 0 221 222config SYS_I2C_EEPROM_BUS 223 int "I2C bus of the EEPROM device." 224 default 0 225 226config SYS_EEPROM_SIZE 227 int "Size in bytes of the EEPROM device" 228 default 256 229 230config SYS_EEPROM_PAGE_WRITE_BITS 231 int "Number of bits used to address bytes in a single page" 232 default 0 233 help 234 The EEPROM page size is 2^SYS_EEPROM_PAGE_WRITE_BITS. 235 A 64 byte page, for example would require six bits. 236 237config SYS_EEPROM_PAGE_WRITE_DELAY_MS 238 int "Number of milliseconds to delay between page writes" 239 default 0 240 241config SYS_I2C_EEPROM_ADDR_LEN 242 int "Length in bytes of the EEPROM memory array address" 243 default 1 244 help 245 Note: This is NOT the chip address length! 246 247config SYS_I2C_EEPROM_ADDR_OVERFLOW 248 hex "EEPROM Address Overflow" 249 default 0 250 help 251 EEPROM chips that implement "address overflow" are ones 252 like Catalyst 24WC04/08/16 which has 9/10/11 bits of 253 address and the extra bits end up in the "chip address" bit 254 slots. This makes a 24WC08 (1Kbyte) chip look like four 256 255 byte chips. 256 257endif 258 259 260endmenu 261