xref: /rk3399_rockchip-uboot/drivers/misc/Kconfig (revision e9290b3b062c5d6b2e3129d2cafcd12d93f3bf26)
10b11dbf7SMasahiro Yamada#
20b11dbf7SMasahiro Yamada# Multifunction miscellaneous devices
30b11dbf7SMasahiro Yamada#
40b11dbf7SMasahiro Yamada
50b11dbf7SMasahiro Yamadamenu "Multifunction device drivers"
60b11dbf7SMasahiro Yamada
74395e06eSThomas Chouconfig MISC
84395e06eSThomas Chou	bool "Enable Driver Model for Misc drivers"
94395e06eSThomas Chou	depends on DM
104395e06eSThomas Chou	help
114395e06eSThomas Chou	  Enable driver model for miscellaneous devices. This class is
124395e06eSThomas Chou	  used only for those do not fit other more general classes. A
134395e06eSThomas Chou	  set of generic read, write and ioctl methods may be used to
144395e06eSThomas Chou	  access the device.
154395e06eSThomas Chou
1606536c20SJason Zhuconfig SPL_MISC
1706536c20SJason Zhu	bool "Enable Driver Model for Misc drivers in SPL"
1806536c20SJason Zhu	depends on SPL_DM
1906536c20SJason Zhu	help
2006536c20SJason Zhu	  Enable driver model for miscellaneous devices. This class is
2106536c20SJason Zhu	  used only for those do not fit other more general classes. A
2206536c20SJason Zhu	  set of generic read, write and ioctl methods may be used to
2306536c20SJason Zhu	  access the device.
2406536c20SJason Zhu
25bc94d102SJason Zhuconfig TPL_MISC
26bc94d102SJason Zhu	bool "Enable Driver Model for Misc drivers in TPL"
27bc94d102SJason Zhu	depends on TPL_DM
28bc94d102SJason Zhu	help
29bc94d102SJason Zhu	  Enable driver model for miscellaneous devices. This class is
30bc94d102SJason Zhu	  used only for those do not fit other more general classes. A
31bc94d102SJason Zhu	  set of generic read, write and ioctl methods may be used to
32bc94d102SJason Zhu	  access the device.
33bc94d102SJason Zhu
3401b57c06SJoseph Chenconfig MISC_DECOMPRESS
3501b57c06SJoseph Chen	bool "Enable misc decompress driver support"
3601b57c06SJoseph Chen	depends on MISC
3701b57c06SJoseph Chen	help
3801b57c06SJoseph Chen	  Enable misc decompress driver support.
3901b57c06SJoseph Chen
4001b57c06SJoseph Chenconfig SPL_MISC_DECOMPRESS
4101b57c06SJoseph Chen	bool "Enable misc decompress driver support in SPL"
4201b57c06SJoseph Chen	depends on SPL_MISC
4301b57c06SJoseph Chen	help
4401b57c06SJoseph Chen	  Enable misc decompress driver support in spl.
4501b57c06SJoseph Chen
46ca844dd8SThomas Chouconfig ALTERA_SYSID
47ca844dd8SThomas Chou	bool "Altera Sysid support"
48ca844dd8SThomas Chou	depends on MISC
49ca844dd8SThomas Chou	help
50ca844dd8SThomas Chou	  Select this to enable a sysid for Altera devices. Please find
51ca844dd8SThomas Chou	  details on the "Embedded Peripherals IP User Guide" of Altera.
52ca844dd8SThomas Chou
53aa5eb9a3SMarek Behúnconfig ATSHA204A
54aa5eb9a3SMarek Behún	bool "Support for Atmel ATSHA204A module"
55aa5eb9a3SMarek Behún	depends on MISC
56aa5eb9a3SMarek Behún	help
57aa5eb9a3SMarek Behún	   Enable support for I2C connected Atmel's ATSHA204A
58aa5eb9a3SMarek Behún	   CryptoAuthentication module found for example on the Turris Omnia
59aa5eb9a3SMarek Behún	   board.
60aa5eb9a3SMarek Behún
6149cd8e85SPhilipp Tomsichconfig ROCKCHIP_EFUSE
6249cd8e85SPhilipp Tomsich        bool "Rockchip e-fuse support"
6349cd8e85SPhilipp Tomsich	depends on MISC
6449cd8e85SPhilipp Tomsich	help
6549cd8e85SPhilipp Tomsich	  Enable (read-only) access for the e-fuse block found in Rockchip
6649cd8e85SPhilipp Tomsich	  SoCs: accesses can either be made using byte addressing and a length
6749cd8e85SPhilipp Tomsich	  or through child-nodes that are generated based on the e-fuse map
6849cd8e85SPhilipp Tomsich	  retrieved from the DTS.
6949cd8e85SPhilipp Tomsich
7049cd8e85SPhilipp Tomsich	  This driver currently supports the RK3399 only, but can easily be
7149cd8e85SPhilipp Tomsich	  extended (by porting the read function from the Linux kernel sources)
7249cd8e85SPhilipp Tomsich	  to support other recent Rockchip devices.
7349cd8e85SPhilipp Tomsich
744973d825SFinley Xiaoconfig ROCKCHIP_OTP
754973d825SFinley Xiao	bool "Rockchip OTP Support"
764973d825SFinley Xiao	depends on MISC
774973d825SFinley Xiao	help
784973d825SFinley Xiao	  This is a simple drive to dump specified values of Rockchip SoC
794973d825SFinley Xiao	  from otp, such as cpu-leakage.
804973d825SFinley Xiao
812bb8d138SSimon Xueconfig ROCKCHIP_HW_DECOMPRESS
822bb8d138SSimon Xue	bool "Rockchip HardWare Decompress Support"
83adf69379SJoseph Chen	depends on MISC_DECOMPRESS
842bb8d138SSimon Xue	help
852bb8d138SSimon Xue	  This driver support Decompress IP built-in Rockchip SoC, support
862bb8d138SSimon Xue	  LZ4, GZIP, PNG, ZLIB.
872bb8d138SSimon Xue
882bb8d138SSimon Xueconfig SPL_ROCKCHIP_HW_DECOMPRESS
892bb8d138SSimon Xue	bool "Rockchip HardWare Decompress Support"
90adf69379SJoseph Chen	depends on SPL_MISC_DECOMPRESS
912bb8d138SSimon Xue	help
922bb8d138SSimon Xue	  This driver support Decompress IP built-in Rockchip SoC, support
932bb8d138SSimon Xue	  LZ4, GZIP, PNG, ZLIB.
942bb8d138SSimon Xue
95*e9290b3bSJason Zhuconfig ROCKCHIP_SECURE_OTP
96*e9290b3bSJason Zhu	bool "Rockchip Secure OTP Support"
97*e9290b3bSJason Zhu	depends on MISC && !OPTEE_CLIENT
98*e9290b3bSJason Zhu	help
99*e9290b3bSJason Zhu	  Support read & write secure otp.
100*e9290b3bSJason Zhu
1012867e1b2SNico Chengconfig SPL_ROCKCHIP_SECURE_OTP
1022867e1b2SNico Cheng	bool "Rockchip Secure OTP Support in spl"
10352ed8851SJason Zhu	depends on SPL_MISC
10452ed8851SJason Zhu	help
1052867e1b2SNico Cheng	  Support read & write secure otp in spl.
106f9519410SJason Zhu
1076fb9ac15SSimon Glassconfig CMD_CROS_EC
1086fb9ac15SSimon Glass	bool "Enable crosec command"
1096fb9ac15SSimon Glass	depends on CROS_EC
1106fb9ac15SSimon Glass	help
1116fb9ac15SSimon Glass	  Enable command-line access to the Chrome OS EC (Embedded
1126fb9ac15SSimon Glass	  Controller). This provides the 'crosec' command which has
1136fb9ac15SSimon Glass	  a number of sub-commands for performing EC tasks such as
1146fb9ac15SSimon Glass	  updating its flash, accessing a small saved context area
1156fb9ac15SSimon Glass	  and talking to the I2C bus behind the EC (if there is one).
1166fb9ac15SSimon Glass
1176fb9ac15SSimon Glassconfig CROS_EC
1186fb9ac15SSimon Glass	bool "Enable Chrome OS EC"
1196fb9ac15SSimon Glass	help
1206fb9ac15SSimon Glass	  Enable access to the Chrome OS EC. This is a separate
1216fb9ac15SSimon Glass	  microcontroller typically available on a SPI bus on Chromebooks. It
1226fb9ac15SSimon Glass	  provides access to the keyboard, some internal storage and may
1236fb9ac15SSimon Glass	  control access to the battery and main PMIC depending on the
1246fb9ac15SSimon Glass	  device. You can use the 'crosec' command to access it.
1256fb9ac15SSimon Glass
1266fb9ac15SSimon Glassconfig CROS_EC_I2C
1276fb9ac15SSimon Glass	bool "Enable Chrome OS EC I2C driver"
1286fb9ac15SSimon Glass	depends on CROS_EC
1296fb9ac15SSimon Glass	help
1306fb9ac15SSimon Glass	  Enable I2C access to the Chrome OS EC. This is used on older
1316fb9ac15SSimon Glass	  ARM Chromebooks such as snow and spring before the standard bus
1326fb9ac15SSimon Glass	  changed to SPI. The EC will accept commands across the I2C using
1336fb9ac15SSimon Glass	  a special message protocol, and provide responses.
1346fb9ac15SSimon Glass
1356fb9ac15SSimon Glassconfig CROS_EC_LPC
1366fb9ac15SSimon Glass	bool "Enable Chrome OS EC LPC driver"
1376fb9ac15SSimon Glass	depends on CROS_EC
1386fb9ac15SSimon Glass	help
1396fb9ac15SSimon Glass	  Enable I2C access to the Chrome OS EC. This is used on x86
1406fb9ac15SSimon Glass	  Chromebooks such as link and falco. The keyboard is provided
1416fb9ac15SSimon Glass	  through a legacy port interface, so on x86 machines the main
1426fb9ac15SSimon Glass	  function of the EC is power and thermal management.
1436fb9ac15SSimon Glass
14447cb8c65SSimon Glassconfig CROS_EC_SANDBOX
14547cb8c65SSimon Glass	bool "Enable Chrome OS EC sandbox driver"
14647cb8c65SSimon Glass	depends on CROS_EC && SANDBOX
14747cb8c65SSimon Glass	help
14847cb8c65SSimon Glass	  Enable a sandbox emulation of the Chrome OS EC. This supports
14947cb8c65SSimon Glass	  keyboard (use the -l flag to enable the LCD), verified boot context,
15047cb8c65SSimon Glass	  EC flash read/write/erase support and a few other things. It is
15147cb8c65SSimon Glass	  enough to perform a Chrome OS verified boot on sandbox.
15247cb8c65SSimon Glass
1536fb9ac15SSimon Glassconfig CROS_EC_SPI
1546fb9ac15SSimon Glass	bool "Enable Chrome OS EC SPI driver"
1556fb9ac15SSimon Glass	depends on CROS_EC
1566fb9ac15SSimon Glass	help
1576fb9ac15SSimon Glass	  Enable SPI access to the Chrome OS EC. This is used on newer
1586fb9ac15SSimon Glass	  ARM Chromebooks such as pit, pi and nyan-big. The SPI interface
1596fb9ac15SSimon Glass	  provides a faster and more robust interface than I2C but the bugs
1606fb9ac15SSimon Glass	  are less interesting.
1616fb9ac15SSimon Glass
162879704d8SSimon Glassconfig DS4510
163879704d8SSimon Glass	bool "Enable support for DS4510 CPU supervisor"
164879704d8SSimon Glass	help
165879704d8SSimon Glass	  Enable support for the Maxim DS4510 CPU supervisor. It has an
166879704d8SSimon Glass	  integrated 64-byte EEPROM, four programmable non-volatile I/O pins
167879704d8SSimon Glass	  and a configurable timer for the supervisor function. The device is
168879704d8SSimon Glass	  connected over I2C.
169879704d8SSimon Glass
170c12e0d93SPeng Fanconfig FSL_SEC_MON
171fe78378dSgaurav rana	bool "Enable FSL SEC_MON Driver"
172fe78378dSgaurav rana	help
173fe78378dSgaurav rana	  Freescale Security Monitor block is responsible for monitoring
174fe78378dSgaurav rana	  system states.
175fe78378dSgaurav rana	  Security Monitor can be transitioned on any security failures,
176fe78378dSgaurav rana	  like software violations or hardware security violations.
1771cdd9412SStefan Roese
1783e020f03SPeng Fanconfig MXC_OCOTP
1793e020f03SPeng Fan	bool "Enable MXC OCOTP Driver"
1803e020f03SPeng Fan	help
1813e020f03SPeng Fan	  If you say Y here, you will get support for the One Time
1823e020f03SPeng Fan	  Programmable memory pages that are stored on the some
1833e020f03SPeng Fan	  Freescale i.MX processors.
1843e020f03SPeng Fan
1854cf9e464SStefan Roeseconfig NUVOTON_NCT6102D
1864cf9e464SStefan Roese	bool "Enable Nuvoton NCT6102D Super I/O driver"
1874cf9e464SStefan Roese	help
1884cf9e464SStefan Roese	  If you say Y here, you will get support for the Nuvoton
1894cf9e464SStefan Roese	  NCT6102D Super I/O driver. This can be used to enable or
1904cf9e464SStefan Roese	  disable the legacy UART, the watchdog or other devices
1914cf9e464SStefan Roese	  in the Nuvoton Super IO chips on X86 platforms.
1924cf9e464SStefan Roese
1935fd6badbSSimon Glassconfig PWRSEQ
1945fd6badbSSimon Glass	bool "Enable power-sequencing drivers"
1955fd6badbSSimon Glass	depends on DM
1965fd6badbSSimon Glass	help
1975fd6badbSSimon Glass	  Power-sequencing drivers provide support for controlling power for
1985fd6badbSSimon Glass	  devices. They are typically referenced by a phandle from another
1995fd6badbSSimon Glass	  device. When the device is started up, its power sequence can be
2005fd6badbSSimon Glass	  initiated.
2015fd6badbSSimon Glass
2025fd6badbSSimon Glassconfig SPL_PWRSEQ
2035fd6badbSSimon Glass	bool "Enable power-sequencing drivers for SPL"
2045fd6badbSSimon Glass	depends on PWRSEQ
2055fd6badbSSimon Glass	help
2065fd6badbSSimon Glass	  Power-sequencing drivers provide support for controlling power for
2075fd6badbSSimon Glass	  devices. They are typically referenced by a phandle from another
2085fd6badbSSimon Glass	  device. When the device is started up, its power sequence can be
2095fd6badbSSimon Glass	  initiated.
2105fd6badbSSimon Glass
2111cdd9412SStefan Roeseconfig PCA9551_LED
2121cdd9412SStefan Roese	bool "Enable PCA9551 LED driver"
2131cdd9412SStefan Roese	help
2141cdd9412SStefan Roese	  Enable driver for PCA9551 LED controller. This controller
2151cdd9412SStefan Roese	  is connected via I2C. So I2C needs to be enabled.
2161cdd9412SStefan Roese
2171cdd9412SStefan Roeseconfig PCA9551_I2C_ADDR
2181cdd9412SStefan Roese	hex "I2C address of PCA9551 LED controller"
2191cdd9412SStefan Roese	depends on PCA9551_LED
2201cdd9412SStefan Roese	default 0x60
2211cdd9412SStefan Roese	help
2221cdd9412SStefan Roese	  The I2C address of the PCA9551 LED controller.
223f9917454SSimon Glass
224bd3ee84aSStephen Warrenconfig TEGRA_CAR
225bd3ee84aSStephen Warren	bool "Enable support for the Tegra CAR driver"
226bd3ee84aSStephen Warren	depends on TEGRA_NO_BPMP
227bd3ee84aSStephen Warren	help
228bd3ee84aSStephen Warren	  The Tegra CAR (Clock and Reset Controller) is a HW module that
229bd3ee84aSStephen Warren	  controls almost all clocks and resets in a Tegra SoC.
230bd3ee84aSStephen Warren
23173dd5c4cSStephen Warrenconfig TEGRA186_BPMP
23273dd5c4cSStephen Warren	bool "Enable support for the Tegra186 BPMP driver"
23373dd5c4cSStephen Warren	depends on TEGRA186
23473dd5c4cSStephen Warren	help
23573dd5c4cSStephen Warren	  The Tegra BPMP (Boot and Power Management Processor) is a separate
23673dd5c4cSStephen Warren	  auxiliary CPU embedded into Tegra to perform power management work,
23773dd5c4cSStephen Warren	  and controls related features such as clocks, resets, power domains,
23873dd5c4cSStephen Warren	  PMIC I2C bus, etc. This driver provides the core low-level
23973dd5c4cSStephen Warren	  communication path by which feature-specific drivers (such as clock)
24073dd5c4cSStephen Warren	  can make requests to the BPMP. This driver is similar to an MFD
24173dd5c4cSStephen Warren	  driver in the Linux kernel.
24273dd5c4cSStephen Warren
24385056932SStefan Roeseconfig WINBOND_W83627
24485056932SStefan Roese	bool "Enable Winbond Super I/O driver"
24585056932SStefan Roese	help
24685056932SStefan Roese	  If you say Y here, you will get support for the Winbond
24785056932SStefan Roese	  W83627 Super I/O driver. This can be used to enable the
24885056932SStefan Roese	  legacy UART or other devices in the Winbond Super IO chips
24985056932SStefan Roese	  on X86 platforms.
25085056932SStefan Roese
251fcf5c041SMiao Yanconfig QFW
252fcf5c041SMiao Yan	bool
253fcf5c041SMiao Yan	help
254fcf5c041SMiao Yan	  Hidden option to enable QEMU fw_cfg interface. This will be selected by
25518686590SMiao Yan	  either CONFIG_CMD_QFW or CONFIG_GENERATE_ACPI_TABLE.
256fcf5c041SMiao Yan
257d7e28918Smario.six@gdsys.ccconfig I2C_EEPROM
258d7e28918Smario.six@gdsys.cc	bool "Enable driver for generic I2C-attached EEPROMs"
259d7e28918Smario.six@gdsys.cc	depends on MISC
260d7e28918Smario.six@gdsys.cc	help
261d7e28918Smario.six@gdsys.cc	  Enable a generic driver for EEPROMs attached via I2C.
262e3f24d4fSAdam Ford
263e3f24d4fSAdam Fordif I2C_EEPROM
264e3f24d4fSAdam Ford
265e3f24d4fSAdam Fordconfig SYS_I2C_EEPROM_ADDR
266e3f24d4fSAdam Ford	hex "Chip address of the EEPROM device"
267e3f24d4fSAdam Ford	default 0
268e3f24d4fSAdam Ford
269e3f24d4fSAdam Fordconfig SYS_I2C_EEPROM_BUS
270e3f24d4fSAdam Ford	int "I2C bus of the EEPROM device."
271e3f24d4fSAdam Ford	default 0
272e3f24d4fSAdam Ford
273e3f24d4fSAdam Fordconfig SYS_EEPROM_SIZE
274e3f24d4fSAdam Ford	int "Size in bytes of the EEPROM device"
275e3f24d4fSAdam Ford	default 256
276e3f24d4fSAdam Ford
277e3f24d4fSAdam Fordconfig SYS_EEPROM_PAGE_WRITE_BITS
278e3f24d4fSAdam Ford	int "Number of bits used to address bytes in a single page"
279e3f24d4fSAdam Ford	default 0
280e3f24d4fSAdam Ford	help
281e3f24d4fSAdam Ford	  The EEPROM page size is 2^SYS_EEPROM_PAGE_WRITE_BITS.
282e3f24d4fSAdam Ford	  A 64 byte page, for example would require six bits.
283e3f24d4fSAdam Ford
284e3f24d4fSAdam Fordconfig SYS_EEPROM_PAGE_WRITE_DELAY_MS
285e3f24d4fSAdam Ford	int "Number of milliseconds to delay between page writes"
286e3f24d4fSAdam Ford	default 0
287e3f24d4fSAdam Ford
288e3f24d4fSAdam Fordconfig SYS_I2C_EEPROM_ADDR_LEN
289e3f24d4fSAdam Ford	int "Length in bytes of the EEPROM memory array address"
290e3f24d4fSAdam Ford	default 1
291e3f24d4fSAdam Ford	help
292e3f24d4fSAdam Ford	  Note: This is NOT the chip address length!
293e3f24d4fSAdam Ford
294e3f24d4fSAdam Fordconfig SYS_I2C_EEPROM_ADDR_OVERFLOW
295e3f24d4fSAdam Ford	hex "EEPROM Address Overflow"
296e3f24d4fSAdam Ford	default 0
297e3f24d4fSAdam Ford	help
298e3f24d4fSAdam Ford	  EEPROM chips that implement "address overflow" are ones
299e3f24d4fSAdam Ford	  like Catalyst 24WC04/08/16 which has 9/10/11 bits of
300e3f24d4fSAdam Ford	  address and the extra bits end up in the "chip address" bit
301e3f24d4fSAdam Ford	  slots. This makes a 24WC08 (1Kbyte) chip look like four 256
302e3f24d4fSAdam Ford	  byte chips.
303e3f24d4fSAdam Ford
304e3f24d4fSAdam Fordendif
305e3f24d4fSAdam Ford
306e3f24d4fSAdam Ford
3070b11dbf7SMasahiro Yamadaendmenu
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