xref: /rk3399_rockchip-uboot/drivers/input/ps2ser.c (revision a89c33db96a1e55319a286dd4c3c05ca64ac6bfd)
1 /***********************************************************************
2  *
3  * (C) Copyright 2004-2009
4  * DENX Software Engineering
5  * Wolfgang Denk, wd@denx.de
6  * All rights reserved.
7  *
8  * Simple 16550A serial driver
9  *
10  * Originally from linux source (drivers/char/ps2ser.c)
11  *
12  * Used by the PS/2 multiplexer driver (ps2mult.c)
13  *
14  ***********************************************************************/
15 
16 #include <common.h>
17 
18 #include <asm/io.h>
19 #include <asm/atomic.h>
20 #include <ps2mult.h>
21 /* This is needed for ns16550.h */
22 #ifndef CONFIG_SYS_NS16550_REG_SIZE
23 #define CONFIG_SYS_NS16550_REG_SIZE 1
24 #endif
25 #include <ns16550.h>
26 
27 DECLARE_GLOBAL_DATA_PTR;
28 
29 /* #define	DEBUG */
30 
31 #define PS2SER_BAUD	57600
32 
33 #ifdef CONFIG_MPC5xxx
34 #if CONFIG_PS2SERIAL == 1
35 #define PSC_BASE MPC5XXX_PSC1
36 #elif CONFIG_PS2SERIAL == 2
37 #define PSC_BASE MPC5XXX_PSC2
38 #elif CONFIG_PS2SERIAL == 3
39 #define PSC_BASE MPC5XXX_PSC3
40 #elif defined(CONFIG_MGT5100)
41 #error CONFIG_PS2SERIAL must be in 1, 2 or 3
42 #elif CONFIG_PS2SERIAL == 4
43 #define PSC_BASE MPC5XXX_PSC4
44 #elif CONFIG_PS2SERIAL == 5
45 #define PSC_BASE MPC5XXX_PSC5
46 #elif CONFIG_PS2SERIAL == 6
47 #define PSC_BASE MPC5XXX_PSC6
48 #else
49 #error CONFIG_PS2SERIAL must be in 1 ... 6
50 #endif
51 
52 #elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
53       defined(CONFIG_MPC8548) || defined(CONFIG_MPC8555)
54 
55 #if CONFIG_PS2SERIAL == 1
56 #define COM_BASE (CONFIG_SYS_CCSRBAR+0x4500)
57 #elif CONFIG_PS2SERIAL == 2
58 #define COM_BASE (CONFIG_SYS_CCSRBAR+0x4600)
59 #else
60 #error CONFIG_PS2SERIAL must be in 1 ... 2
61 #endif
62 
63 #endif /* CONFIG_MPC5xxx / CONFIG_MPC8540 / other */
64 
65 static int	ps2ser_getc_hw(void);
66 static void	ps2ser_interrupt(void *dev_id);
67 
68 extern struct	serial_state rs_table[]; /* in serial.c */
69 #if !defined(CONFIG_MPC5xxx) && !defined(CONFIG_MPC8540) && \
70     !defined(CONFIG_MPC8541) && !defined(CONFIG_MPC8548) && \
71     !defined(CONFIG_MPC8555)
72 static struct	serial_state *state;
73 #endif
74 
75 static u_char	ps2buf[PS2BUF_SIZE];
76 static atomic_t	ps2buf_cnt;
77 static int	ps2buf_in_idx;
78 static int	ps2buf_out_idx;
79 
80 #ifdef CONFIG_MPC5xxx
81 int ps2ser_init(void)
82 {
83 	volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE;
84 	unsigned long baseclk;
85 	int div;
86 
87 	/* reset PSC */
88 	psc->command = PSC_SEL_MODE_REG_1;
89 
90 	/* select clock sources */
91 #if defined(CONFIG_MGT5100)
92 	psc->psc_clock_select = 0xdd00;
93 	baseclk = (CONFIG_SYS_MPC5XXX_CLKIN + 16) / 32;
94 #elif defined(CONFIG_MPC5200)
95 	psc->psc_clock_select = 0;
96 	baseclk = (gd->ipb_clk + 16) / 32;
97 #endif
98 
99 	/* switch to UART mode */
100 	psc->sicr = 0;
101 
102 	/* configure parity, bit length and so on */
103 #if defined(CONFIG_MGT5100)
104 	psc->mode = PSC_MODE_ERR | PSC_MODE_8_BITS | PSC_MODE_PARNONE;
105 #elif defined(CONFIG_MPC5200)
106 	psc->mode = PSC_MODE_8_BITS | PSC_MODE_PARNONE;
107 #endif
108 	psc->mode = PSC_MODE_ONE_STOP;
109 
110 	/* set up UART divisor */
111 	div = (baseclk + (PS2SER_BAUD/2)) / PS2SER_BAUD;
112 	psc->ctur = (div >> 8) & 0xff;
113 	psc->ctlr = div & 0xff;
114 
115 	/* disable all interrupts */
116 	psc->psc_imr = 0;
117 
118 	/* reset and enable Rx/Tx */
119 	psc->command = PSC_RST_RX;
120 	psc->command = PSC_RST_TX;
121 	psc->command = PSC_RX_ENABLE | PSC_TX_ENABLE;
122 
123 	return (0);
124 }
125 
126 #elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
127       defined(CONFIG_MPC8548) || defined(CONFIG_MPC8555)
128 int ps2ser_init(void)
129 {
130 	NS16550_t com_port = (NS16550_t)COM_BASE;
131 
132 	com_port->ier = 0x00;
133 	com_port->lcr = UART_LCR_BKSE | UART_LCR_8N1;
134 	com_port->dll = (CONFIG_SYS_NS16550_CLK / 16 / PS2SER_BAUD) & 0xff;
135 	com_port->dlm = ((CONFIG_SYS_NS16550_CLK / 16 / PS2SER_BAUD) >> 8) & 0xff;
136 	com_port->lcr = UART_LCR_8N1;
137 	com_port->mcr = (UART_MCR_DTR | UART_MCR_RTS);
138 	com_port->fcr = (UART_FCR_FIFO_EN | UART_FCR_RXSR | UART_FCR_TXSR);
139 
140 	return (0);
141 }
142 
143 #else /* !CONFIG_MPC5xxx && !CONFIG_MPC8540 / other */
144 
145 static inline unsigned int ps2ser_in(int offset)
146 {
147 	return readb((unsigned long) state->iomem_base + offset);
148 }
149 
150 static inline void ps2ser_out(int offset, int value)
151 {
152 	writeb(value, (unsigned long) state->iomem_base + offset);
153 }
154 
155 int ps2ser_init(void)
156 {
157 	int quot;
158 	unsigned cval;
159 
160 	state = rs_table + CONFIG_PS2SERIAL;
161 
162 	quot = state->baud_base / PS2SER_BAUD;
163 	cval = 0x3; /* 8N1 - 8 data bits, no parity bits, 1 stop bit */
164 
165 	  /* Set speed, enable interrupts, enable FIFO
166 	   */
167 	ps2ser_out(UART_LCR, cval | UART_LCR_DLAB);
168 	ps2ser_out(UART_DLL, quot & 0xff);
169 	ps2ser_out(UART_DLM, quot >> 8);
170 	ps2ser_out(UART_LCR, cval);
171 	ps2ser_out(UART_IER, UART_IER_RDI);
172 	ps2ser_out(UART_MCR, UART_MCR_OUT2 | UART_MCR_DTR | UART_MCR_RTS);
173 	ps2ser_out(UART_FCR,
174 	    UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
175 
176 	/* If we read 0xff from the LSR, there is no UART here
177 	 */
178 	if (ps2ser_in(UART_LSR) == 0xff) {
179 		printf ("ps2ser.c: no UART found\n");
180 		return -1;
181 	}
182 
183 	irq_install_handler(state->irq, ps2ser_interrupt, NULL);
184 
185 	return 0;
186 }
187 #endif /* CONFIG_MPC5xxx / CONFIG_MPC8540 / other */
188 
189 void ps2ser_putc(int chr)
190 {
191 #ifdef CONFIG_MPC5xxx
192 	volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE;
193 #elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
194       defined(CONFIG_MPC8548) || defined(CONFIG_MPC8555)
195 	NS16550_t com_port = (NS16550_t)COM_BASE;
196 #endif
197 #ifdef DEBUG
198 	printf(">>>> 0x%02x\n", chr);
199 #endif
200 
201 #ifdef CONFIG_MPC5xxx
202 	while (!(psc->psc_status & PSC_SR_TXRDY));
203 
204 	psc->psc_buffer_8 = chr;
205 #elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
206       defined(CONFIG_MPC8548) || defined(CONFIG_MPC8555)
207 	while ((com_port->lsr & UART_LSR_THRE) == 0);
208 	com_port->thr = chr;
209 #else
210 	while (!(ps2ser_in(UART_LSR) & UART_LSR_THRE));
211 
212 	ps2ser_out(UART_TX, chr);
213 #endif
214 }
215 
216 static int ps2ser_getc_hw(void)
217 {
218 #ifdef CONFIG_MPC5xxx
219 	volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE;
220 #elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
221       defined(CONFIG_MPC8548) || defined(CONFIG_MPC8555)
222 	NS16550_t com_port = (NS16550_t)COM_BASE;
223 #endif
224 	int res = -1;
225 
226 #ifdef CONFIG_MPC5xxx
227 	if (psc->psc_status & PSC_SR_RXRDY) {
228 		res = (psc->psc_buffer_8);
229 	}
230 #elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
231       defined(CONFIG_MPC8548) || defined(CONFIG_MPC8555)
232 	if (com_port->lsr & UART_LSR_DR) {
233 		res = com_port->rbr;
234 	}
235 #else
236 	if (ps2ser_in(UART_LSR) & UART_LSR_DR) {
237 		res = (ps2ser_in(UART_RX));
238 	}
239 #endif
240 
241 	return res;
242 }
243 
244 int ps2ser_getc(void)
245 {
246 	volatile int chr;
247 	int flags;
248 
249 #ifdef DEBUG
250 	printf("<< ");
251 #endif
252 
253 	flags = disable_interrupts();
254 
255 	do {
256 		if (atomic_read(&ps2buf_cnt) != 0) {
257 			chr = ps2buf[ps2buf_out_idx++];
258 			ps2buf_out_idx &= (PS2BUF_SIZE - 1);
259 			atomic_dec(&ps2buf_cnt);
260 		} else {
261 			chr = ps2ser_getc_hw();
262 		}
263 	}
264 	while (chr < 0);
265 
266 	if (flags) enable_interrupts();
267 
268 #ifdef DEBUG
269 	printf("0x%02x\n", chr);
270 #endif
271 
272 	return chr;
273 }
274 
275 int ps2ser_check(void)
276 {
277 	int flags;
278 
279 	flags = disable_interrupts();
280 	ps2ser_interrupt(NULL);
281 	if (flags) enable_interrupts();
282 
283 	return atomic_read(&ps2buf_cnt);
284 }
285 
286 static void ps2ser_interrupt(void *dev_id)
287 {
288 #ifdef CONFIG_MPC5xxx
289 	volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE;
290 #elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
291       defined(CONFIG_MPC8548) || defined(CONFIG_MPC8555)
292 	NS16550_t com_port = (NS16550_t)COM_BASE;
293 #endif
294 	int chr;
295 	int status;
296 
297 	do {
298 		chr = ps2ser_getc_hw();
299 #ifdef CONFIG_MPC5xxx
300 		status = psc->psc_status;
301 #elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
302       defined(CONFIG_MPC8548) || defined(CONFIG_MPC8555)
303 		status = com_port->lsr;
304 #else
305 		status = ps2ser_in(UART_IIR);
306 #endif
307 		if (chr < 0) continue;
308 
309 		if (atomic_read(&ps2buf_cnt) < PS2BUF_SIZE) {
310 			ps2buf[ps2buf_in_idx++] = chr;
311 			ps2buf_in_idx &= (PS2BUF_SIZE - 1);
312 			atomic_inc(&ps2buf_cnt);
313 		} else {
314 			printf ("ps2ser.c: buffer overflow\n");
315 		}
316 #ifdef CONFIG_MPC5xxx
317 	} while (status & PSC_SR_RXRDY);
318 #elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
319       defined(CONFIG_MPC8548) || defined(CONFIG_MPC8555)
320 	} while (status & UART_LSR_DR);
321 #else
322 	} while (status & UART_IIR_RDI);
323 #endif
324 
325 	if (atomic_read(&ps2buf_cnt)) {
326 		ps2mult_callback(atomic_read(&ps2buf_cnt));
327 	}
328 }
329