1 /* 2 * (C) Copyright 2004 Tundra Semiconductor Corp. 3 * Author: Alex Bounine 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <config.h> 9 #include <common.h> 10 11 #include <tsi108.h> 12 13 #if defined(CONFIG_CMD_I2C) 14 15 #define I2C_DELAY 100000 16 #undef DEBUG_I2C 17 18 #ifdef DEBUG_I2C 19 #define DPRINT(x) printf (x) 20 #else 21 #define DPRINT(x) 22 #endif 23 24 /* All functions assume that Tsi108 I2C block is the only master on the bus */ 25 /* I2C read helper function */ 26 27 void i2c_init(int speed, int slaveaddr) 28 { 29 /* 30 * The TSI108 has a fixed I2C clock rate and doesn't support slave 31 * operation. This function only exists as a stub to fit into the 32 * U-Boot I2C API. 33 */ 34 } 35 36 static int i2c_read_byte ( 37 uint i2c_chan, /* I2C channel number: 0 - main, 1 - SDC SPD */ 38 uchar chip_addr,/* I2C device address on the bus */ 39 uint byte_addr, /* Byte address within I2C device */ 40 uchar * buffer /* pointer to data buffer */ 41 ) 42 { 43 u32 temp; 44 u32 to_count = I2C_DELAY; 45 u32 op_status = TSI108_I2C_TIMEOUT_ERR; 46 u32 chan_offset = TSI108_I2C_OFFSET; 47 48 DPRINT (("I2C read_byte() %d 0x%02x 0x%02x\n", 49 i2c_chan, chip_addr, byte_addr)); 50 51 if (0 != i2c_chan) 52 chan_offset = TSI108_I2C_SDRAM_OFFSET; 53 54 /* Check if I2C operation is in progress */ 55 temp = *(u32 *) (CONFIG_SYS_TSI108_CSR_BASE + chan_offset + I2C_CNTRL2); 56 57 if (0 == (temp & (I2C_CNTRL2_RD_STATUS | I2C_CNTRL2_WR_STATUS | 58 I2C_CNTRL2_START))) { 59 /* Set device address and operation (read = 0) */ 60 temp = (byte_addr << 16) | ((chip_addr & 0x07) << 8) | 61 ((chip_addr >> 3) & 0x0F); 62 *(u32 *) (CONFIG_SYS_TSI108_CSR_BASE + chan_offset + I2C_CNTRL1) = 63 temp; 64 65 /* Issue the read command 66 * (at this moment all other parameters are 0 67 * (size = 1 byte, lane = 0) 68 */ 69 70 *(u32 *) (CONFIG_SYS_TSI108_CSR_BASE + chan_offset + I2C_CNTRL2) = 71 (I2C_CNTRL2_START); 72 73 /* Wait until operation completed */ 74 do { 75 /* Read I2C operation status */ 76 temp = *(u32 *) (CONFIG_SYS_TSI108_CSR_BASE + chan_offset + I2C_CNTRL2); 77 78 if (0 == (temp & (I2C_CNTRL2_RD_STATUS | I2C_CNTRL2_START))) { 79 if (0 == (temp & 80 (I2C_CNTRL2_I2C_CFGERR | 81 I2C_CNTRL2_I2C_TO_ERR)) 82 ) { 83 op_status = TSI108_I2C_SUCCESS; 84 85 temp = *(u32 *) (CONFIG_SYS_TSI108_CSR_BASE + 86 chan_offset + 87 I2C_RD_DATA); 88 89 *buffer = (u8) (temp & 0xFF); 90 } else { 91 /* report HW error */ 92 op_status = TSI108_I2C_IF_ERROR; 93 94 DPRINT (("I2C HW error reported: 0x%02x\n", temp)); 95 } 96 97 break; 98 } 99 } while (to_count--); 100 } else { 101 op_status = TSI108_I2C_IF_BUSY; 102 103 DPRINT (("I2C Transaction start failed: 0x%02x\n", temp)); 104 } 105 106 DPRINT (("I2C read_byte() status: 0x%02x\n", op_status)); 107 return op_status; 108 } 109 110 /* 111 * I2C Read interface as defined in "include/i2c.h" : 112 * chip_addr: I2C chip address, range 0..127 113 * (to read from SPD channel EEPROM use (0xD0 ... 0xD7) 114 * NOTE: The bit 7 in the chip_addr serves as a channel select. 115 * This hack is for enabling "i2c sdram" command on Tsi108 boards 116 * without changes to common code. Used for I2C reads only. 117 * byte_addr: Memory or register address within the chip 118 * alen: Number of bytes to use for addr (typically 1, 2 for larger 119 * memories, 0 for register type devices with only one 120 * register) 121 * buffer: Pointer to destination buffer for data to be read 122 * len: How many bytes to read 123 * 124 * Returns: 0 on success, not 0 on failure 125 */ 126 127 int i2c_read (uchar chip_addr, uint byte_addr, int alen, 128 uchar * buffer, int len) 129 { 130 u32 op_status = TSI108_I2C_PARAM_ERR; 131 u32 i2c_if = 0; 132 133 /* Hack to support second (SPD) I2C controller (SPD EEPROM read only).*/ 134 if (0xD0 == (chip_addr & ~0x07)) { 135 i2c_if = 1; 136 chip_addr &= 0x7F; 137 } 138 /* Check for valid I2C address */ 139 if (chip_addr <= 0x7F && (byte_addr + len) <= (0x01 << (alen * 8))) { 140 while (len--) { 141 op_status = i2c_read_byte(i2c_if, chip_addr, byte_addr++, buffer++); 142 143 if (TSI108_I2C_SUCCESS != op_status) { 144 DPRINT (("I2C read_byte() failed: 0x%02x (%d left)\n", op_status, len)); 145 146 break; 147 } 148 } 149 } 150 151 DPRINT (("I2C read() status: 0x%02x\n", op_status)); 152 return op_status; 153 } 154 155 /* I2C write helper function */ 156 157 static int i2c_write_byte (uchar chip_addr,/* I2C device address on the bus */ 158 uint byte_addr, /* Byte address within I2C device */ 159 uchar * buffer /* pointer to data buffer */ 160 ) 161 { 162 u32 temp; 163 u32 to_count = I2C_DELAY; 164 u32 op_status = TSI108_I2C_TIMEOUT_ERR; 165 166 /* Check if I2C operation is in progress */ 167 temp = *(u32 *) (CONFIG_SYS_TSI108_CSR_BASE + TSI108_I2C_OFFSET + I2C_CNTRL2); 168 169 if (0 == (temp & (I2C_CNTRL2_RD_STATUS | I2C_CNTRL2_WR_STATUS | I2C_CNTRL2_START))) { 170 /* Place data into the I2C Tx Register */ 171 *(u32 *) (CONFIG_SYS_TSI108_CSR_BASE + TSI108_I2C_OFFSET + 172 I2C_TX_DATA) = (u32) * buffer; 173 174 /* Set device address and operation */ 175 temp = 176 I2C_CNTRL1_I2CWRITE | (byte_addr << 16) | 177 ((chip_addr & 0x07) << 8) | ((chip_addr >> 3) & 0x0F); 178 *(u32 *) (CONFIG_SYS_TSI108_CSR_BASE + TSI108_I2C_OFFSET + 179 I2C_CNTRL1) = temp; 180 181 /* Issue the write command (at this moment all other parameters 182 * are 0 (size = 1 byte, lane = 0) 183 */ 184 185 *(u32 *) (CONFIG_SYS_TSI108_CSR_BASE + TSI108_I2C_OFFSET + 186 I2C_CNTRL2) = (I2C_CNTRL2_START); 187 188 op_status = TSI108_I2C_TIMEOUT_ERR; 189 190 /* Wait until operation completed */ 191 do { 192 /* Read I2C operation status */ 193 temp = *(u32 *) (CONFIG_SYS_TSI108_CSR_BASE + TSI108_I2C_OFFSET + I2C_CNTRL2); 194 195 if (0 == (temp & (I2C_CNTRL2_WR_STATUS | I2C_CNTRL2_START))) { 196 if (0 == (temp & 197 (I2C_CNTRL2_I2C_CFGERR | 198 I2C_CNTRL2_I2C_TO_ERR))) { 199 op_status = TSI108_I2C_SUCCESS; 200 } else { 201 /* report detected HW error */ 202 op_status = TSI108_I2C_IF_ERROR; 203 204 DPRINT (("I2C HW error reported: 0x%02x\n", temp)); 205 } 206 207 break; 208 } 209 210 } while (to_count--); 211 } else { 212 op_status = TSI108_I2C_IF_BUSY; 213 214 DPRINT (("I2C Transaction start failed: 0x%02x\n", temp)); 215 } 216 217 return op_status; 218 } 219 220 /* 221 * I2C Write interface as defined in "include/i2c.h" : 222 * chip_addr: I2C chip address, range 0..127 223 * byte_addr: Memory or register address within the chip 224 * alen: Number of bytes to use for addr (typically 1, 2 for larger 225 * memories, 0 for register type devices with only one 226 * register) 227 * buffer: Pointer to data to be written 228 * len: How many bytes to write 229 * 230 * Returns: 0 on success, not 0 on failure 231 */ 232 233 int i2c_write (uchar chip_addr, uint byte_addr, int alen, uchar * buffer, 234 int len) 235 { 236 u32 op_status = TSI108_I2C_PARAM_ERR; 237 238 /* Check for valid I2C address */ 239 if (chip_addr <= 0x7F && (byte_addr + len) <= (0x01 << (alen * 8))) { 240 while (len--) { 241 op_status = 242 i2c_write_byte (chip_addr, byte_addr++, buffer++); 243 244 if (TSI108_I2C_SUCCESS != op_status) { 245 DPRINT (("I2C write_byte() failed: 0x%02x (%d left)\n", op_status, len)); 246 247 break; 248 } 249 } 250 } 251 252 return op_status; 253 } 254 255 /* 256 * I2C interface function as defined in "include/i2c.h". 257 * Probe the given I2C chip address by reading single byte from offset 0. 258 * Returns 0 if a chip responded, not 0 on failure. 259 */ 260 261 int i2c_probe (uchar chip) 262 { 263 u32 tmp; 264 265 /* 266 * Try to read the first location of the chip. 267 * The Tsi108 HW doesn't support sending just the chip address 268 * and checkong for an <ACK> back. 269 */ 270 return i2c_read (chip, 0, 1, (uchar *)&tmp, 1); 271 } 272 273 #endif 274