1 /* 2 * Copyright (c) 2012 The Chromium OS Authors. All rights reserved. 3 * Copyright (c) 2010-2011 NVIDIA Corporation 4 * NVIDIA Corporation <www.nvidia.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #include <common.h> 10 #include <fdtdec.h> 11 #include <i2c.h> 12 #include <asm/io.h> 13 #include <asm/arch/clock.h> 14 #include <asm/arch/funcmux.h> 15 #include <asm/arch/gpio.h> 16 #include <asm/arch/pinmux.h> 17 #include <asm/arch-tegra/clk_rst.h> 18 #include <asm/arch-tegra/tegra_i2c.h> 19 20 DECLARE_GLOBAL_DATA_PTR; 21 22 /* Information about i2c controller */ 23 struct i2c_bus { 24 int id; 25 enum periph_id periph_id; 26 int speed; 27 int pinmux_config; 28 struct i2c_control *control; 29 struct i2c_ctlr *regs; 30 int is_dvc; /* DVC type, rather than I2C */ 31 int is_scs; /* single clock source (T114+) */ 32 int inited; /* bus is inited */ 33 }; 34 35 static struct i2c_bus i2c_controllers[TEGRA_I2C_NUM_CONTROLLERS]; 36 37 static void set_packet_mode(struct i2c_bus *i2c_bus) 38 { 39 u32 config; 40 41 config = I2C_CNFG_NEW_MASTER_FSM_MASK | I2C_CNFG_PACKET_MODE_MASK; 42 43 if (i2c_bus->is_dvc) { 44 struct dvc_ctlr *dvc = (struct dvc_ctlr *)i2c_bus->regs; 45 46 writel(config, &dvc->cnfg); 47 } else { 48 writel(config, &i2c_bus->regs->cnfg); 49 /* 50 * program I2C_SL_CNFG.NEWSL to ENABLE. This fixes probe 51 * issues, i.e., some slaves may be wrongly detected. 52 */ 53 setbits_le32(&i2c_bus->regs->sl_cnfg, I2C_SL_CNFG_NEWSL_MASK); 54 } 55 } 56 57 static void i2c_reset_controller(struct i2c_bus *i2c_bus) 58 { 59 /* Reset I2C controller. */ 60 reset_periph(i2c_bus->periph_id, 1); 61 62 /* re-program config register to packet mode */ 63 set_packet_mode(i2c_bus); 64 } 65 66 static void i2c_init_controller(struct i2c_bus *i2c_bus) 67 { 68 /* 69 * Use PLLP - DP-04508-001_v06 datasheet indicates a divisor of 8 70 * here, in section 23.3.1, but in fact we seem to need a factor of 71 * 16 to get the right frequency. 72 */ 73 clock_start_periph_pll(i2c_bus->periph_id, CLOCK_ID_PERIPH, 74 i2c_bus->speed * 2 * 8); 75 76 if (i2c_bus->is_scs) { 77 /* 78 * T114 I2C went to a single clock source for standard/fast and 79 * HS clock speeds. The new clock rate setting calculation is: 80 * SCL = CLK_SOURCE.I2C / 81 * (CLK_MULT_STD_FAST_MODE * (I2C_CLK_DIV_STD_FAST_MODE+1) * 82 * I2C FREQUENCY DIVISOR) as per the T114 TRM (sec 30.3.1). 83 * 84 * NOTE: We do this here, after the initial clock/pll start, 85 * because if we read the clk_div reg before the controller 86 * is running, we hang, and we need it for the new calc. 87 */ 88 int clk_div_stdfst_mode = readl(&i2c_bus->regs->clk_div) >> 16; 89 debug("%s: CLK_DIV_STD_FAST_MODE setting = %d\n", __func__, 90 clk_div_stdfst_mode); 91 92 clock_start_periph_pll(i2c_bus->periph_id, CLOCK_ID_PERIPH, 93 CLK_MULT_STD_FAST_MODE * (clk_div_stdfst_mode + 1) * 94 i2c_bus->speed * 2); 95 } 96 97 /* Reset I2C controller. */ 98 i2c_reset_controller(i2c_bus); 99 100 /* Configure I2C controller. */ 101 if (i2c_bus->is_dvc) { /* only for DVC I2C */ 102 struct dvc_ctlr *dvc = (struct dvc_ctlr *)i2c_bus->regs; 103 104 setbits_le32(&dvc->ctrl3, DVC_CTRL_REG3_I2C_HW_SW_PROG_MASK); 105 } 106 107 funcmux_select(i2c_bus->periph_id, i2c_bus->pinmux_config); 108 } 109 110 static void send_packet_headers( 111 struct i2c_bus *i2c_bus, 112 struct i2c_trans_info *trans, 113 u32 packet_id, 114 bool end_with_repeated_start) 115 { 116 u32 data; 117 118 /* prepare header1: Header size = 0 Protocol = I2C, pktType = 0 */ 119 data = PROTOCOL_TYPE_I2C << PKT_HDR1_PROTOCOL_SHIFT; 120 data |= packet_id << PKT_HDR1_PKT_ID_SHIFT; 121 data |= i2c_bus->id << PKT_HDR1_CTLR_ID_SHIFT; 122 writel(data, &i2c_bus->control->tx_fifo); 123 debug("pkt header 1 sent (0x%x)\n", data); 124 125 /* prepare header2 */ 126 data = (trans->num_bytes - 1) << PKT_HDR2_PAYLOAD_SIZE_SHIFT; 127 writel(data, &i2c_bus->control->tx_fifo); 128 debug("pkt header 2 sent (0x%x)\n", data); 129 130 /* prepare IO specific header: configure the slave address */ 131 data = trans->address << PKT_HDR3_SLAVE_ADDR_SHIFT; 132 133 /* Enable Read if it is not a write transaction */ 134 if (!(trans->flags & I2C_IS_WRITE)) 135 data |= PKT_HDR3_READ_MODE_MASK; 136 if (end_with_repeated_start) 137 data |= PKT_HDR3_REPEAT_START_MASK; 138 139 /* Write I2C specific header */ 140 writel(data, &i2c_bus->control->tx_fifo); 141 debug("pkt header 3 sent (0x%x)\n", data); 142 } 143 144 static int wait_for_tx_fifo_empty(struct i2c_control *control) 145 { 146 u32 count; 147 int timeout_us = I2C_TIMEOUT_USEC; 148 149 while (timeout_us >= 0) { 150 count = (readl(&control->fifo_status) & TX_FIFO_EMPTY_CNT_MASK) 151 >> TX_FIFO_EMPTY_CNT_SHIFT; 152 if (count == I2C_FIFO_DEPTH) 153 return 1; 154 udelay(10); 155 timeout_us -= 10; 156 } 157 158 return 0; 159 } 160 161 static int wait_for_rx_fifo_notempty(struct i2c_control *control) 162 { 163 u32 count; 164 int timeout_us = I2C_TIMEOUT_USEC; 165 166 while (timeout_us >= 0) { 167 count = (readl(&control->fifo_status) & TX_FIFO_FULL_CNT_MASK) 168 >> TX_FIFO_FULL_CNT_SHIFT; 169 if (count) 170 return 1; 171 udelay(10); 172 timeout_us -= 10; 173 } 174 175 return 0; 176 } 177 178 static int wait_for_transfer_complete(struct i2c_control *control) 179 { 180 int int_status; 181 int timeout_us = I2C_TIMEOUT_USEC; 182 183 while (timeout_us >= 0) { 184 int_status = readl(&control->int_status); 185 if (int_status & I2C_INT_NO_ACK_MASK) 186 return -int_status; 187 if (int_status & I2C_INT_ARBITRATION_LOST_MASK) 188 return -int_status; 189 if (int_status & I2C_INT_XFER_COMPLETE_MASK) 190 return 0; 191 192 udelay(10); 193 timeout_us -= 10; 194 } 195 196 return -1; 197 } 198 199 static int send_recv_packets(struct i2c_bus *i2c_bus, 200 struct i2c_trans_info *trans) 201 { 202 struct i2c_control *control = i2c_bus->control; 203 u32 int_status; 204 u32 words; 205 u8 *dptr; 206 u32 local; 207 uchar last_bytes; 208 int error = 0; 209 int is_write = trans->flags & I2C_IS_WRITE; 210 211 /* clear status from previous transaction, XFER_COMPLETE, NOACK, etc. */ 212 int_status = readl(&control->int_status); 213 writel(int_status, &control->int_status); 214 215 send_packet_headers(i2c_bus, trans, 1, 216 trans->flags & I2C_USE_REPEATED_START); 217 218 words = DIV_ROUND_UP(trans->num_bytes, 4); 219 last_bytes = trans->num_bytes & 3; 220 dptr = trans->buf; 221 222 while (words) { 223 u32 *wptr = (u32 *)dptr; 224 225 if (is_write) { 226 /* deal with word alignment */ 227 if ((unsigned)dptr & 3) { 228 memcpy(&local, dptr, sizeof(u32)); 229 writel(local, &control->tx_fifo); 230 debug("pkt data sent (0x%x)\n", local); 231 } else { 232 writel(*wptr, &control->tx_fifo); 233 debug("pkt data sent (0x%x)\n", *wptr); 234 } 235 if (!wait_for_tx_fifo_empty(control)) { 236 error = -1; 237 goto exit; 238 } 239 } else { 240 if (!wait_for_rx_fifo_notempty(control)) { 241 error = -1; 242 goto exit; 243 } 244 /* 245 * for the last word, we read into our local buffer, 246 * in case that caller did not provide enough buffer. 247 */ 248 local = readl(&control->rx_fifo); 249 if ((words == 1) && last_bytes) 250 memcpy(dptr, (char *)&local, last_bytes); 251 else if ((unsigned)dptr & 3) 252 memcpy(dptr, &local, sizeof(u32)); 253 else 254 *wptr = local; 255 debug("pkt data received (0x%x)\n", local); 256 } 257 words--; 258 dptr += sizeof(u32); 259 } 260 261 if (wait_for_transfer_complete(control)) { 262 error = -1; 263 goto exit; 264 } 265 return 0; 266 exit: 267 /* error, reset the controller. */ 268 i2c_reset_controller(i2c_bus); 269 270 return error; 271 } 272 273 static int tegra_i2c_write_data(struct i2c_bus *bus, u32 addr, u8 *data, 274 u32 len, bool end_with_repeated_start) 275 { 276 int error; 277 struct i2c_trans_info trans_info; 278 279 trans_info.address = addr; 280 trans_info.buf = data; 281 trans_info.flags = I2C_IS_WRITE; 282 if (end_with_repeated_start) 283 trans_info.flags |= I2C_USE_REPEATED_START; 284 trans_info.num_bytes = len; 285 trans_info.is_10bit_address = 0; 286 287 error = send_recv_packets(bus, &trans_info); 288 if (error) 289 debug("tegra_i2c_write_data: Error (%d) !!!\n", error); 290 291 return error; 292 } 293 294 static int tegra_i2c_read_data(struct i2c_bus *bus, u32 addr, u8 *data, 295 u32 len) 296 { 297 int error; 298 struct i2c_trans_info trans_info; 299 300 trans_info.address = addr | 1; 301 trans_info.buf = data; 302 trans_info.flags = 0; 303 trans_info.num_bytes = len; 304 trans_info.is_10bit_address = 0; 305 306 error = send_recv_packets(bus, &trans_info); 307 if (error) 308 debug("tegra_i2c_read_data: Error (%d) !!!\n", error); 309 310 return error; 311 } 312 313 #ifndef CONFIG_OF_CONTROL 314 #error "Please enable device tree support to use this driver" 315 #endif 316 317 /** 318 * Check that a bus number is valid and return a pointer to it 319 * 320 * @param bus_num Bus number to check / return 321 * @return pointer to bus, if valid, else NULL 322 */ 323 static struct i2c_bus *tegra_i2c_get_bus(struct i2c_adapter *adap) 324 { 325 struct i2c_bus *bus; 326 327 bus = &i2c_controllers[adap->hwadapnr]; 328 if (!bus->inited) { 329 debug("%s: Bus %u not available\n", __func__, adap->hwadapnr); 330 return NULL; 331 } 332 333 return bus; 334 } 335 336 static unsigned int tegra_i2c_set_bus_speed(struct i2c_adapter *adap, 337 unsigned int speed) 338 { 339 struct i2c_bus *bus; 340 341 bus = tegra_i2c_get_bus(adap); 342 if (!bus) 343 return 0; 344 bus->speed = speed; 345 i2c_init_controller(bus); 346 347 return 0; 348 } 349 350 static int i2c_get_config(const void *blob, int node, struct i2c_bus *i2c_bus) 351 { 352 i2c_bus->regs = (struct i2c_ctlr *)fdtdec_get_addr(blob, node, "reg"); 353 354 /* 355 * We don't have a binding for pinmux yet. Leave it out for now. So 356 * far no one needs anything other than the default. 357 */ 358 i2c_bus->pinmux_config = FUNCMUX_DEFAULT; 359 i2c_bus->speed = fdtdec_get_int(blob, node, "clock-frequency", 0); 360 i2c_bus->periph_id = clock_decode_periph_id(blob, node); 361 362 /* 363 * We can't specify the pinmux config in the fdt, so I2C2 will not 364 * work on Seaboard. It normally has no devices on it anyway. 365 * You could add in this little hack if you need to use it. 366 * The correct solution is a pinmux binding in the fdt. 367 * 368 * if (i2c_bus->periph_id == PERIPH_ID_I2C2) 369 * i2c_bus->pinmux_config = FUNCMUX_I2C2_PTA; 370 */ 371 if (i2c_bus->periph_id == -1) 372 return -FDT_ERR_NOTFOUND; 373 374 return 0; 375 } 376 377 /* 378 * Process a list of nodes, adding them to our list of I2C ports. 379 * 380 * @param blob fdt blob 381 * @param node_list list of nodes to process (any <=0 are ignored) 382 * @param count number of nodes to process 383 * @param is_dvc 1 if these are DVC ports, 0 if standard I2C 384 * @param is_scs 1 if this HW uses a single clock source (T114+) 385 * @return 0 if ok, -1 on error 386 */ 387 static int process_nodes(const void *blob, int node_list[], int count, 388 int is_dvc, int is_scs) 389 { 390 struct i2c_bus *i2c_bus; 391 int i; 392 393 /* build the i2c_controllers[] for each controller */ 394 for (i = 0; i < count; i++) { 395 int node = node_list[i]; 396 397 if (node <= 0) 398 continue; 399 400 i2c_bus = &i2c_controllers[i]; 401 i2c_bus->id = i; 402 403 if (i2c_get_config(blob, node, i2c_bus)) { 404 printf("i2c_init_board: failed to decode bus %d\n", i); 405 return -1; 406 } 407 408 i2c_bus->is_scs = is_scs; 409 410 i2c_bus->is_dvc = is_dvc; 411 if (is_dvc) { 412 i2c_bus->control = 413 &((struct dvc_ctlr *)i2c_bus->regs)->control; 414 } else { 415 i2c_bus->control = &i2c_bus->regs->control; 416 } 417 debug("%s: controller bus %d at %p, periph_id %d, speed %d: ", 418 is_dvc ? "dvc" : "i2c", i, i2c_bus->regs, 419 i2c_bus->periph_id, i2c_bus->speed); 420 i2c_init_controller(i2c_bus); 421 debug("ok\n"); 422 i2c_bus->inited = 1; 423 424 /* Mark position as used */ 425 node_list[i] = -1; 426 } 427 428 return 0; 429 } 430 431 /* Sadly there is no error return from this function */ 432 void i2c_init_board(void) 433 { 434 int node_list[TEGRA_I2C_NUM_CONTROLLERS]; 435 const void *blob = gd->fdt_blob; 436 int count; 437 438 /* First check for newer (T114+) I2C ports */ 439 count = fdtdec_find_aliases_for_id(blob, "i2c", 440 COMPAT_NVIDIA_TEGRA114_I2C, node_list, 441 TEGRA_I2C_NUM_CONTROLLERS); 442 if (process_nodes(blob, node_list, count, 0, 1)) 443 return; 444 445 /* Now get the older (T20/T30) normal I2C ports */ 446 count = fdtdec_find_aliases_for_id(blob, "i2c", 447 COMPAT_NVIDIA_TEGRA20_I2C, node_list, 448 TEGRA_I2C_NUM_CONTROLLERS); 449 if (process_nodes(blob, node_list, count, 0, 0)) 450 return; 451 452 /* Now look for dvc ports */ 453 count = fdtdec_add_aliases_for_id(blob, "i2c", 454 COMPAT_NVIDIA_TEGRA20_DVC, node_list, 455 TEGRA_I2C_NUM_CONTROLLERS); 456 if (process_nodes(blob, node_list, count, 1, 0)) 457 return; 458 } 459 460 static void tegra_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr) 461 { 462 /* No i2c support prior to relocation */ 463 if (!(gd->flags & GD_FLG_RELOC)) 464 return; 465 466 /* This will override the speed selected in the fdt for that port */ 467 debug("i2c_init(speed=%u, slaveaddr=0x%x)\n", speed, slaveaddr); 468 i2c_set_bus_speed(speed); 469 } 470 471 /* i2c write version without the register address */ 472 int i2c_write_data(struct i2c_bus *bus, uchar chip, uchar *buffer, int len, 473 bool end_with_repeated_start) 474 { 475 int rc; 476 477 debug("i2c_write_data: chip=0x%x, len=0x%x\n", chip, len); 478 debug("write_data: "); 479 /* use rc for counter */ 480 for (rc = 0; rc < len; ++rc) 481 debug(" 0x%02x", buffer[rc]); 482 debug("\n"); 483 484 /* Shift 7-bit address over for lower-level i2c functions */ 485 rc = tegra_i2c_write_data(bus, chip << 1, buffer, len, 486 end_with_repeated_start); 487 if (rc) 488 debug("i2c_write_data(): rc=%d\n", rc); 489 490 return rc; 491 } 492 493 /* i2c read version without the register address */ 494 int i2c_read_data(struct i2c_bus *bus, uchar chip, uchar *buffer, int len) 495 { 496 int rc; 497 498 debug("inside i2c_read_data():\n"); 499 /* Shift 7-bit address over for lower-level i2c functions */ 500 rc = tegra_i2c_read_data(bus, chip << 1, buffer, len); 501 if (rc) { 502 debug("i2c_read_data(): rc=%d\n", rc); 503 return rc; 504 } 505 506 debug("i2c_read_data: "); 507 /* reuse rc for counter*/ 508 for (rc = 0; rc < len; ++rc) 509 debug(" 0x%02x", buffer[rc]); 510 debug("\n"); 511 512 return 0; 513 } 514 515 /* Probe to see if a chip is present. */ 516 static int tegra_i2c_probe(struct i2c_adapter *adap, uchar chip) 517 { 518 struct i2c_bus *bus; 519 int rc; 520 uchar reg; 521 522 debug("i2c_probe: addr=0x%x\n", chip); 523 bus = tegra_i2c_get_bus(adap); 524 if (!bus) 525 return 1; 526 reg = 0; 527 rc = i2c_write_data(bus, chip, ®, 1, false); 528 if (rc) { 529 debug("Error probing 0x%x.\n", chip); 530 return 1; 531 } 532 return 0; 533 } 534 535 static int i2c_addr_ok(const uint addr, const int alen) 536 { 537 /* We support 7 or 10 bit addresses, so one or two bytes each */ 538 return alen == 1 || alen == 2; 539 } 540 541 /* Read bytes */ 542 static int tegra_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr, 543 int alen, uchar *buffer, int len) 544 { 545 struct i2c_bus *bus; 546 uint offset; 547 int i; 548 549 debug("i2c_read: chip=0x%x, addr=0x%x, len=0x%x\n", 550 chip, addr, len); 551 bus = tegra_i2c_get_bus(adap); 552 if (!bus) 553 return 1; 554 if (!i2c_addr_ok(addr, alen)) { 555 debug("i2c_read: Bad address %x.%d.\n", addr, alen); 556 return 1; 557 } 558 for (offset = 0; offset < len; offset++) { 559 if (alen) { 560 uchar data[alen]; 561 for (i = 0; i < alen; i++) { 562 data[alen - i - 1] = 563 (addr + offset) >> (8 * i); 564 } 565 if (i2c_write_data(bus, chip, data, alen, true)) { 566 debug("i2c_read: error sending (0x%x)\n", 567 addr); 568 return 1; 569 } 570 } 571 if (i2c_read_data(bus, chip, buffer + offset, 1)) { 572 debug("i2c_read: error reading (0x%x)\n", addr); 573 return 1; 574 } 575 } 576 577 return 0; 578 } 579 580 /* Write bytes */ 581 static int tegra_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr, 582 int alen, uchar *buffer, int len) 583 { 584 struct i2c_bus *bus; 585 uint offset; 586 int i; 587 588 debug("i2c_write: chip=0x%x, addr=0x%x, len=0x%x\n", 589 chip, addr, len); 590 bus = tegra_i2c_get_bus(adap); 591 if (!bus) 592 return 1; 593 if (!i2c_addr_ok(addr, alen)) { 594 debug("i2c_write: Bad address %x.%d.\n", addr, alen); 595 return 1; 596 } 597 for (offset = 0; offset < len; offset++) { 598 uchar data[alen + 1]; 599 for (i = 0; i < alen; i++) 600 data[alen - i - 1] = (addr + offset) >> (8 * i); 601 data[alen] = buffer[offset]; 602 if (i2c_write_data(bus, chip, data, alen + 1, false)) { 603 debug("i2c_write: error sending (0x%x)\n", addr); 604 return 1; 605 } 606 } 607 608 return 0; 609 } 610 611 int tegra_i2c_get_dvc_bus_num(void) 612 { 613 int i; 614 615 for (i = 0; i < TEGRA_I2C_NUM_CONTROLLERS; i++) { 616 struct i2c_bus *bus = &i2c_controllers[i]; 617 618 if (bus->inited && bus->is_dvc) 619 return i; 620 } 621 622 return -1; 623 } 624 625 /* 626 * Register soft i2c adapters 627 */ 628 U_BOOT_I2C_ADAP_COMPLETE(tegra0, tegra_i2c_init, tegra_i2c_probe, 629 tegra_i2c_read, tegra_i2c_write, 630 tegra_i2c_set_bus_speed, 100000, 0, 0) 631 U_BOOT_I2C_ADAP_COMPLETE(tegra1, tegra_i2c_init, tegra_i2c_probe, 632 tegra_i2c_read, tegra_i2c_write, 633 tegra_i2c_set_bus_speed, 100000, 0, 1) 634 U_BOOT_I2C_ADAP_COMPLETE(tegra2, tegra_i2c_init, tegra_i2c_probe, 635 tegra_i2c_read, tegra_i2c_write, 636 tegra_i2c_set_bus_speed, 100000, 0, 2) 637 U_BOOT_I2C_ADAP_COMPLETE(tegra3, tegra_i2c_init, tegra_i2c_probe, 638 tegra_i2c_read, tegra_i2c_write, 639 tegra_i2c_set_bus_speed, 100000, 0, 3) 640 #if TEGRA_I2C_NUM_CONTROLLERS > 4 641 U_BOOT_I2C_ADAP_COMPLETE(tegra4, tegra_i2c_init, tegra_i2c_probe, 642 tegra_i2c_read, tegra_i2c_write, 643 tegra_i2c_set_bus_speed, 100000, 0, 4) 644 #endif 645