1 /* 2 * Copyright (C) 2011 Renesas Solutions Corp. 3 * Copyright (C) 2011 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> 4 * 5 * This program is free software; you can redistribute it and/or 6 * modify it under the terms of the GNU General Public License as 7 * published by the Free Software Foundation; either version 2 of 8 * the License, or (at your option) any later version. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program; if not, write to the Free Software 17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 18 * MA 02111-1307 USA 19 */ 20 21 #include <common.h> 22 #include <asm/io.h> 23 24 /* Every register is 32bit aligned, but only 8bits in size */ 25 #define ureg(name) u8 name; u8 __pad_##name##0; u16 __pad_##name##1; 26 struct sh_i2c { 27 ureg(icdr); 28 ureg(iccr); 29 ureg(icsr); 30 ureg(icic); 31 ureg(iccl); 32 ureg(icch); 33 }; 34 #undef ureg 35 36 static struct sh_i2c *base; 37 38 /* ICCR */ 39 #define SH_I2C_ICCR_ICE (1 << 7) 40 #define SH_I2C_ICCR_RACK (1 << 6) 41 #define SH_I2C_ICCR_RTS (1 << 4) 42 #define SH_I2C_ICCR_BUSY (1 << 2) 43 #define SH_I2C_ICCR_SCP (1 << 0) 44 45 /* ICSR / ICIC */ 46 #define SH_IC_BUSY (1 << 4) 47 #define SH_IC_TACK (1 << 2) 48 #define SH_IC_WAIT (1 << 1) 49 #define SH_IC_DTE (1 << 0) 50 51 #ifdef CONFIG_SH_I2C_8BIT 52 /* store 8th bit of iccl and icch in ICIC register */ 53 #define SH_I2C_ICIC_ICCLB8 (1 << 7) 54 #define SH_I2C_ICIC_ICCHB8 (1 << 6) 55 #endif 56 57 static u16 iccl, icch; 58 59 #define IRQ_WAIT 1000 60 61 static void irq_dte(struct sh_i2c *base) 62 { 63 int i; 64 65 for (i = 0 ; i < IRQ_WAIT ; i++) { 66 if (SH_IC_DTE & readb(&base->icsr)) 67 break; 68 udelay(10); 69 } 70 } 71 72 static int irq_dte_with_tack(struct sh_i2c *base) 73 { 74 int i; 75 76 for (i = 0 ; i < IRQ_WAIT ; i++) { 77 if (SH_IC_DTE & readb(&base->icsr)) 78 break; 79 if (SH_IC_TACK & readb(&base->icsr)) 80 return -1; 81 udelay(10); 82 } 83 return 0; 84 } 85 86 static void irq_busy(struct sh_i2c *base) 87 { 88 int i; 89 90 for (i = 0 ; i < IRQ_WAIT ; i++) { 91 if (!(SH_IC_BUSY & readb(&base->icsr))) 92 break; 93 udelay(10); 94 } 95 } 96 97 static int i2c_set_addr(struct sh_i2c *base, u8 id, u8 reg, int stop) 98 { 99 u8 icic = SH_IC_TACK; 100 101 writeb(readb(&base->iccr) & ~SH_I2C_ICCR_ICE, &base->iccr); 102 writeb(readb(&base->iccr) | SH_I2C_ICCR_ICE, &base->iccr); 103 104 writeb(iccl & 0xff, &base->iccl); 105 writeb(icch & 0xff, &base->icch); 106 #ifdef CONFIG_SH_I2C_8BIT 107 if (iccl > 0xff) 108 icic |= SH_I2C_ICIC_ICCLB8; 109 if (icch > 0xff) 110 icic |= SH_I2C_ICIC_ICCHB8; 111 #endif 112 writeb(icic, &base->icic); 113 114 writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RTS|SH_I2C_ICCR_BUSY), &base->iccr); 115 irq_dte(base); 116 117 writeb(readb(&base->icsr) & ~SH_IC_TACK, &base->icsr); 118 writeb(id << 1, &base->icdr); 119 if (irq_dte_with_tack(base) != 0) 120 return -1; 121 122 writeb(reg, &base->icdr); 123 if (stop) 124 writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RTS), &base->iccr); 125 126 if (irq_dte_with_tack(base) != 0) 127 return -1; 128 return 0; 129 } 130 131 static void i2c_finish(struct sh_i2c *base) 132 { 133 writeb(0, &base->icsr); 134 writeb(readb(&base->iccr) & ~SH_I2C_ICCR_ICE, &base->iccr); 135 } 136 137 static void i2c_raw_write(struct sh_i2c *base, u8 id, u8 reg, u8 val) 138 { 139 i2c_set_addr(base, id, reg, 0); 140 udelay(10); 141 142 writeb(val, &base->icdr); 143 irq_dte(base); 144 145 writeb((SH_I2C_ICCR_ICE | SH_I2C_ICCR_RTS), &base->iccr); 146 irq_dte(base); 147 irq_busy(base); 148 149 i2c_finish(base); 150 } 151 152 static u8 i2c_raw_read(struct sh_i2c *base, u8 id, u8 reg) 153 { 154 u8 ret; 155 156 #if defined(CONFIG_SH73A0) 157 i2c_set_addr(base, id, reg, 0); 158 #else 159 i2c_set_addr(base, id, reg, 1); 160 udelay(100); 161 #endif 162 163 writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RTS|SH_I2C_ICCR_BUSY), &base->iccr); 164 irq_dte(base); 165 166 writeb(id << 1 | 0x01, &base->icdr); 167 irq_dte(base); 168 169 writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_SCP), &base->iccr); 170 irq_dte(base); 171 172 ret = readb(&base->icdr); 173 174 writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RACK), &base->iccr); 175 readb(&base->icdr); /* Dummy read */ 176 irq_busy(base); 177 178 i2c_finish(base); 179 180 return ret; 181 } 182 183 #ifdef CONFIG_I2C_MULTI_BUS 184 static unsigned int current_bus; 185 186 /** 187 * i2c_set_bus_num - change active I2C bus 188 * @bus: bus index, zero based 189 * @returns: 0 on success, non-0 on failure 190 */ 191 int i2c_set_bus_num(unsigned int bus) 192 { 193 if ((bus < 0) || (bus >= CONFIG_SYS_MAX_I2C_BUS)) { 194 printf("Bad bus: %d\n", bus); 195 return -1; 196 } 197 198 switch (bus) { 199 case 0: 200 base = (void *)CONFIG_SH_I2C_BASE0; 201 break; 202 case 1: 203 base = (void *)CONFIG_SH_I2C_BASE1; 204 break; 205 #ifdef CONFIG_SH_I2C_BASE2 206 case 2: 207 base = (void *)CONFIG_SH_I2C_BASE2; 208 break; 209 #endif 210 #ifdef CONFIG_SH_I2C_BASE3 211 case 3: 212 base = (void *)CONFIG_SH_I2C_BASE3; 213 break; 214 #endif 215 #ifdef CONFIG_SH_I2C_BASE4 216 case 4: 217 base = (void *)CONFIG_SH_I2C_BASE4; 218 break; 219 #endif 220 default: 221 return -1; 222 } 223 current_bus = bus; 224 225 return 0; 226 } 227 228 /** 229 * i2c_get_bus_num - returns index of active I2C bus 230 */ 231 unsigned int i2c_get_bus_num(void) 232 { 233 return current_bus; 234 } 235 #endif 236 237 #define SH_I2C_ICCL_CALC(clk, date, t_low, t_high) \ 238 ((clk / rate) * (t_low / t_low + t_high)) 239 #define SH_I2C_ICCH_CALC(clk, date, t_low, t_high) \ 240 ((clk / rate) * (t_high / t_low + t_high)) 241 242 void i2c_init(int speed, int slaveaddr) 243 { 244 int num, denom, tmp; 245 246 #ifdef CONFIG_I2C_MULTI_BUS 247 current_bus = 0; 248 #endif 249 base = (struct sh_i2c *)CONFIG_SH_I2C_BASE0; 250 251 /* 252 * Calculate the value for iccl. From the data sheet: 253 * iccl = (p-clock / transfer-rate) * (L / (L + H)) 254 * where L and H are the SCL low and high ratio. 255 */ 256 num = CONFIG_SH_I2C_CLOCK * CONFIG_SH_I2C_DATA_LOW; 257 denom = speed * (CONFIG_SH_I2C_DATA_HIGH + CONFIG_SH_I2C_DATA_LOW); 258 tmp = num * 10 / denom; 259 if (tmp % 10 >= 5) 260 iccl = (u16)((num/denom) + 1); 261 else 262 iccl = (u16)(num/denom); 263 264 /* Calculate the value for icch. From the data sheet: 265 icch = (p clock / transfer rate) * (H / (L + H)) */ 266 num = CONFIG_SH_I2C_CLOCK * CONFIG_SH_I2C_DATA_HIGH; 267 tmp = num * 10 / denom; 268 if (tmp % 10 >= 5) 269 icch = (u16)((num/denom) + 1); 270 else 271 icch = (u16)(num/denom); 272 } 273 274 /* 275 * i2c_read: - Read multiple bytes from an i2c device 276 * 277 * The higher level routines take into account that this function is only 278 * called with len < page length of the device (see configuration file) 279 * 280 * @chip: address of the chip which is to be read 281 * @addr: i2c data address within the chip 282 * @alen: length of the i2c data address (1..2 bytes) 283 * @buffer: where to write the data 284 * @len: how much byte do we want to read 285 * @return: 0 in case of success 286 */ 287 int i2c_read(u8 chip, u32 addr, int alen, u8 *buffer, int len) 288 { 289 int i = 0; 290 for (i = 0 ; i < len ; i++) 291 buffer[i] = i2c_raw_read(base, chip, addr + i); 292 293 return 0; 294 } 295 296 /* 297 * i2c_write: - Write multiple bytes to an i2c device 298 * 299 * The higher level routines take into account that this function is only 300 * called with len < page length of the device (see configuration file) 301 * 302 * @chip: address of the chip which is to be written 303 * @addr: i2c data address within the chip 304 * @alen: length of the i2c data address (1..2 bytes) 305 * @buffer: where to find the data to be written 306 * @len: how much byte do we want to read 307 * @return: 0 in case of success 308 */ 309 int i2c_write(u8 chip, u32 addr, int alen, u8 *buffer, int len) 310 { 311 int i = 0; 312 for (i = 0; i < len ; i++) 313 i2c_raw_write(base, chip, addr + i, buffer[i]); 314 315 return 0; 316 } 317 318 /* 319 * i2c_probe: - Test if a chip answers for a given i2c address 320 * 321 * @chip: address of the chip which is searched for 322 * @return: 0 if a chip was found, -1 otherwhise 323 */ 324 int i2c_probe(u8 chip) 325 { 326 int ret; 327 328 ret = i2c_set_addr(base, chip, 0, 1); 329 i2c_finish(base); 330 return ret; 331 } 332