1 /* 2 * Copyright (C) 2011 Renesas Solutions Corp. 3 * Copyright (C) 2011 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> 4 * 5 * This program is free software; you can redistribute it and/or 6 * modify it under the terms of the GNU General Public License as 7 * published by the Free Software Foundation; either version 2 of 8 * the License, or (at your option) any later version. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program; if not, write to the Free Software 17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 18 * MA 02111-1307 USA 19 */ 20 21 #include <common.h> 22 #include <asm/io.h> 23 24 /* Every register is 32bit aligned, but only 8bits in size */ 25 #define ureg(name) u8 name; u8 __pad_##name##0; u16 __pad_##name##1; 26 struct sh_i2c { 27 ureg(icdr); 28 ureg(iccr); 29 ureg(icsr); 30 ureg(icic); 31 ureg(iccl); 32 ureg(icch); 33 }; 34 #undef ureg 35 36 static struct sh_i2c *base; 37 38 /* ICCR */ 39 #define SH_I2C_ICCR_ICE (1 << 7) 40 #define SH_I2C_ICCR_RACK (1 << 6) 41 #define SH_I2C_ICCR_RTS (1 << 4) 42 #define SH_I2C_ICCR_BUSY (1 << 2) 43 #define SH_I2C_ICCR_SCP (1 << 0) 44 45 /* ICSR / ICIC */ 46 #define SH_IC_BUSY (1 << 4) 47 #define SH_IC_TACK (1 << 2) 48 #define SH_IC_WAIT (1 << 1) 49 #define SH_IC_DTE (1 << 0) 50 51 #ifdef CONFIG_SH_I2C_8BIT 52 /* store 8th bit of iccl and icch in ICIC register */ 53 #define SH_I2C_ICIC_ICCLB8 (1 << 7) 54 #define SH_I2C_ICIC_ICCHB8 (1 << 6) 55 #endif 56 57 static u16 iccl, icch; 58 59 #define IRQ_WAIT 1000 60 61 static void irq_dte(struct sh_i2c *base) 62 { 63 int i; 64 65 for (i = 0 ; i < IRQ_WAIT ; i++) { 66 if (SH_IC_DTE & readb(&base->icsr)) 67 break; 68 udelay(10); 69 } 70 } 71 72 static void irq_busy(struct sh_i2c *base) 73 { 74 int i; 75 76 for (i = 0 ; i < IRQ_WAIT ; i++) { 77 if (!(SH_IC_BUSY & readb(&base->icsr))) 78 break; 79 udelay(10); 80 } 81 } 82 83 static void i2c_set_addr(struct sh_i2c *base, u8 id, u8 reg, int stop) 84 { 85 u8 icic = 0; 86 87 writeb(readb(&base->iccr) & ~SH_I2C_ICCR_ICE, &base->iccr); 88 writeb(readb(&base->iccr) | SH_I2C_ICCR_ICE, &base->iccr); 89 90 writeb(iccl & 0xff, &base->iccl); 91 writeb(icch & 0xff, &base->icch); 92 #ifdef CONFIG_SH_I2C_8BIT 93 if (iccl > 0xff) 94 icic |= SH_I2C_ICIC_ICCLB8; 95 if (icch > 0xff) 96 icic |= SH_I2C_ICIC_ICCHB8; 97 #endif 98 writeb(icic, &base->icic); 99 100 writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RTS|SH_I2C_ICCR_BUSY), &base->iccr); 101 irq_dte(base); 102 103 writeb(id << 1, &base->icdr); 104 irq_dte(base); 105 106 writeb(reg, &base->icdr); 107 if (stop) 108 writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RTS), &base->iccr); 109 110 irq_dte(base); 111 } 112 113 static void i2c_finish(struct sh_i2c *base) 114 { 115 writeb(0, &base->icsr); 116 writeb(readb(&base->iccr) & ~SH_I2C_ICCR_ICE, &base->iccr); 117 } 118 119 static void i2c_raw_write(struct sh_i2c *base, u8 id, u8 reg, u8 val) 120 { 121 i2c_set_addr(base, id, reg, 0); 122 udelay(10); 123 124 writeb(val, &base->icdr); 125 irq_dte(base); 126 127 writeb((SH_I2C_ICCR_ICE | SH_I2C_ICCR_RTS), &base->iccr); 128 irq_dte(base); 129 irq_busy(base); 130 131 i2c_finish(base); 132 } 133 134 static u8 i2c_raw_read(struct sh_i2c *base, u8 id, u8 reg) 135 { 136 u8 ret; 137 138 #if defined(CONFIG_SH73A0) 139 i2c_set_addr(base, id, reg, 0); 140 #else 141 i2c_set_addr(base, id, reg, 1); 142 udelay(100); 143 #endif 144 145 writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RTS|SH_I2C_ICCR_BUSY), &base->iccr); 146 irq_dte(base); 147 148 writeb(id << 1 | 0x01, &base->icdr); 149 irq_dte(base); 150 151 writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_SCP), &base->iccr); 152 irq_dte(base); 153 154 ret = readb(&base->icdr); 155 156 writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RACK), &base->iccr); 157 readb(&base->icdr); /* Dummy read */ 158 irq_busy(base); 159 160 i2c_finish(base); 161 162 return ret; 163 } 164 165 #ifdef CONFIG_I2C_MULTI_BUS 166 static unsigned int current_bus; 167 168 /** 169 * i2c_set_bus_num - change active I2C bus 170 * @bus: bus index, zero based 171 * @returns: 0 on success, non-0 on failure 172 */ 173 int i2c_set_bus_num(unsigned int bus) 174 { 175 if ((bus < 0) || (bus >= CONFIG_SYS_MAX_I2C_BUS)) { 176 printf("Bad bus: %d\n", bus); 177 return -1; 178 } 179 180 switch (bus) { 181 case 0: 182 base = (void *)CONFIG_SH_I2C_BASE0; 183 break; 184 case 1: 185 base = (void *)CONFIG_SH_I2C_BASE1; 186 break; 187 default: 188 return -1; 189 } 190 current_bus = bus; 191 192 return 0; 193 } 194 195 /** 196 * i2c_get_bus_num - returns index of active I2C bus 197 */ 198 unsigned int i2c_get_bus_num(void) 199 { 200 return current_bus; 201 } 202 #endif 203 204 #define SH_I2C_ICCL_CALC(clk, date, t_low, t_high) \ 205 ((clk / rate) * (t_low / t_low + t_high)) 206 #define SH_I2C_ICCH_CALC(clk, date, t_low, t_high) \ 207 ((clk / rate) * (t_high / t_low + t_high)) 208 209 void i2c_init(int speed, int slaveaddr) 210 { 211 int num, denom, tmp; 212 213 #ifdef CONFIG_I2C_MULTI_BUS 214 current_bus = 0; 215 #endif 216 base = (struct sh_i2c *)CONFIG_SH_I2C_BASE0; 217 218 /* 219 * Calculate the value for iccl. From the data sheet: 220 * iccl = (p-clock / transfer-rate) * (L / (L + H)) 221 * where L and H are the SCL low and high ratio. 222 */ 223 num = CONFIG_SH_I2C_CLOCK * CONFIG_SH_I2C_DATA_LOW; 224 denom = speed * (CONFIG_SH_I2C_DATA_HIGH + CONFIG_SH_I2C_DATA_LOW); 225 tmp = num * 10 / denom; 226 if (tmp % 10 >= 5) 227 iccl = (u16)((num/denom) + 1); 228 else 229 iccl = (u16)(num/denom); 230 231 /* Calculate the value for icch. From the data sheet: 232 icch = (p clock / transfer rate) * (H / (L + H)) */ 233 num = CONFIG_SH_I2C_CLOCK * CONFIG_SH_I2C_DATA_HIGH; 234 tmp = num * 10 / denom; 235 if (tmp % 10 >= 5) 236 icch = (u16)((num/denom) + 1); 237 else 238 icch = (u16)(num/denom); 239 } 240 241 /* 242 * i2c_read: - Read multiple bytes from an i2c device 243 * 244 * The higher level routines take into account that this function is only 245 * called with len < page length of the device (see configuration file) 246 * 247 * @chip: address of the chip which is to be read 248 * @addr: i2c data address within the chip 249 * @alen: length of the i2c data address (1..2 bytes) 250 * @buffer: where to write the data 251 * @len: how much byte do we want to read 252 * @return: 0 in case of success 253 */ 254 int i2c_read(u8 chip, u32 addr, int alen, u8 *buffer, int len) 255 { 256 int i = 0; 257 for (i = 0 ; i < len ; i++) 258 buffer[i] = i2c_raw_read(base, chip, addr + i); 259 260 return 0; 261 } 262 263 /* 264 * i2c_write: - Write multiple bytes to an i2c device 265 * 266 * The higher level routines take into account that this function is only 267 * called with len < page length of the device (see configuration file) 268 * 269 * @chip: address of the chip which is to be written 270 * @addr: i2c data address within the chip 271 * @alen: length of the i2c data address (1..2 bytes) 272 * @buffer: where to find the data to be written 273 * @len: how much byte do we want to read 274 * @return: 0 in case of success 275 */ 276 int i2c_write(u8 chip, u32 addr, int alen, u8 *buffer, int len) 277 { 278 int i = 0; 279 for (i = 0; i < len ; i++) 280 i2c_raw_write(base, chip, addr + i, buffer[i]); 281 282 return 0; 283 } 284 285 /* 286 * i2c_probe: - Test if a chip answers for a given i2c address 287 * 288 * @chip: address of the chip which is searched for 289 * @return: 0 if a chip was found, -1 otherwhise 290 */ 291 int i2c_probe(u8 chip) 292 { 293 return 0; 294 } 295