1 /* 2 * (C) Copyright 2002 3 * David Mueller, ELSOFT AG, d.mueller@elsoft.ch 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24 /* This code should work for both the S3C2400 and the S3C2410 25 * as they seem to have the same I2C controller inside. 26 * The different address mapping is handled by the s3c24xx.h files below. 27 */ 28 29 #include <common.h> 30 #if defined(CONFIG_S3C2400) 31 #include <s3c2400.h> 32 #elif defined(CONFIG_S3C2410) 33 #include <s3c2410.h> 34 #endif 35 36 #include <asm/io.h> 37 #include <i2c.h> 38 39 #ifdef CONFIG_HARD_I2C 40 41 #define I2C_WRITE 0 42 #define I2C_READ 1 43 44 #define I2C_OK 0 45 #define I2C_NOK 1 46 #define I2C_NACK 2 47 #define I2C_NOK_LA 3 /* Lost arbitration */ 48 #define I2C_NOK_TOUT 4 /* time out */ 49 50 #define I2CSTAT_BSY 0x20 /* Busy bit */ 51 #define I2CSTAT_NACK 0x01 /* Nack bit */ 52 #define I2CCON_IRPND 0x10 /* Interrupt pending bit */ 53 #define I2C_MODE_MT 0xC0 /* Master Transmit Mode */ 54 #define I2C_MODE_MR 0x80 /* Master Receive Mode */ 55 #define I2C_START_STOP 0x20 /* START / STOP */ 56 #define I2C_TXRX_ENA 0x10 /* I2C Tx/Rx enable */ 57 58 #define I2C_TIMEOUT 1 /* 1 second */ 59 60 static int GetI2CSDA(void) 61 { 62 struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio(); 63 64 #ifdef CONFIG_S3C2410 65 return (readl(&gpio->GPEDAT) & 0x8000) >> 15; 66 #endif 67 #ifdef CONFIG_S3C2400 68 return (readl(&gpio->PGDAT) & 0x0020) >> 5; 69 #endif 70 } 71 72 #if 0 73 static void SetI2CSDA(int x) 74 { 75 rGPEDAT = (rGPEDAT & ~0x8000) | (x & 1) << 15; 76 } 77 #endif 78 79 static void SetI2CSCL(int x) 80 { 81 struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio(); 82 83 #ifdef CONFIG_S3C2410 84 writel((readl(&gpio->GPEDAT) & ~0x4000) | (x & 1) << 14, &gpio->GPEDAT); 85 #endif 86 #ifdef CONFIG_S3C2400 87 writel((readl(&gpio->PGDAT) & ~0x0040) | (x & 1) << 6, &gpio->PGDAT); 88 #endif 89 } 90 91 static int WaitForXfer(void) 92 { 93 struct s3c24x0_i2c *i2c = s3c24x0_get_base_i2c(); 94 int i; 95 96 i = I2C_TIMEOUT * 10000; 97 while (!(readl(&i2c->IICCON) & I2CCON_IRPND) && (i > 0)) { 98 udelay(100); 99 i--; 100 } 101 102 return (readl(&i2c->IICCON) & I2CCON_IRPND) ? I2C_OK : I2C_NOK_TOUT; 103 } 104 105 static int IsACK(void) 106 { 107 struct s3c24x0_i2c *i2c = s3c24x0_get_base_i2c(); 108 109 return !(readl(&i2c->IICSTAT) & I2CSTAT_NACK); 110 } 111 112 static void ReadWriteByte(void) 113 { 114 struct s3c24x0_i2c *i2c = s3c24x0_get_base_i2c(); 115 116 writel(readl(&i2c->IICCON) & ~I2CCON_IRPND, &i2c->IICCON); 117 } 118 119 void i2c_init(int speed, int slaveadd) 120 { 121 struct s3c24x0_i2c *i2c = s3c24x0_get_base_i2c(); 122 struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio(); 123 ulong freq, pres = 16, div; 124 int i; 125 126 /* wait for some time to give previous transfer a chance to finish */ 127 128 i = I2C_TIMEOUT * 1000; 129 while ((readl(&i2c->IICSTAT) && I2CSTAT_BSY) && (i > 0)) { 130 udelay(1000); 131 i--; 132 } 133 134 if ((readl(&i2c->IICSTAT) & I2CSTAT_BSY) || GetI2CSDA() == 0) { 135 #ifdef CONFIG_S3C2410 136 ulong old_gpecon = readl(&gpio->GPECON); 137 #endif 138 #ifdef CONFIG_S3C2400 139 ulong old_gpecon = readl(&gpio->PGCON); 140 #endif 141 /* bus still busy probably by (most) previously interrupted 142 transfer */ 143 144 #ifdef CONFIG_S3C2410 145 /* set I2CSDA and I2CSCL (GPE15, GPE14) to GPIO */ 146 writel((readl(&gpio->GPECON) & ~0xF0000000) | 0x10000000, 147 &gpio->GPECON); 148 #endif 149 #ifdef CONFIG_S3C2400 150 /* set I2CSDA and I2CSCL (PG5, PG6) to GPIO */ 151 writel((readl(&gpio->PGCON) & ~0x00003c00) | 0x00001000, 152 &gpio->PGCON); 153 #endif 154 155 /* toggle I2CSCL until bus idle */ 156 SetI2CSCL(0); 157 udelay(1000); 158 i = 10; 159 while ((i > 0) && (GetI2CSDA() != 1)) { 160 SetI2CSCL(1); 161 udelay(1000); 162 SetI2CSCL(0); 163 udelay(1000); 164 i--; 165 } 166 SetI2CSCL(1); 167 udelay(1000); 168 169 /* restore pin functions */ 170 #ifdef CONFIG_S3C2410 171 writel(old_gpecon, &gpio->GPECON); 172 #endif 173 #ifdef CONFIG_S3C2400 174 writel(old_gpecon, &gpio->PGCON); 175 #endif 176 } 177 178 /* calculate prescaler and divisor values */ 179 freq = get_PCLK(); 180 if ((freq / pres / (16 + 1)) > speed) 181 /* set prescaler to 512 */ 182 pres = 512; 183 184 div = 0; 185 while ((freq / pres / (div + 1)) > speed) 186 div++; 187 188 /* set prescaler, divisor according to freq, also set 189 * ACKGEN, IRQ */ 190 writel((div & 0x0F) | 0xA0 | ((pres == 512) ? 0x40 : 0), &i2c->IICCON); 191 192 /* init to SLAVE REVEIVE and set slaveaddr */ 193 writel(0, &i2c->IICSTAT); 194 writel(slaveadd, &i2c->IICADD); 195 /* program Master Transmit (and implicit STOP) */ 196 writel(I2C_MODE_MT | I2C_TXRX_ENA, &i2c->IICSTAT); 197 198 } 199 200 /* 201 * cmd_type is 0 for write, 1 for read. 202 * 203 * addr_len can take any value from 0-255, it is only limited 204 * by the char, we could make it larger if needed. If it is 205 * 0 we skip the address write cycle. 206 */ 207 static 208 int i2c_transfer(unsigned char cmd_type, 209 unsigned char chip, 210 unsigned char addr[], 211 unsigned char addr_len, 212 unsigned char data[], unsigned short data_len) 213 { 214 struct s3c24x0_i2c *i2c = s3c24x0_get_base_i2c(); 215 int i, result; 216 217 if (data == 0 || data_len == 0) { 218 /*Don't support data transfer of no length or to address 0 */ 219 printf("i2c_transfer: bad call\n"); 220 return I2C_NOK; 221 } 222 223 /* Check I2C bus idle */ 224 i = I2C_TIMEOUT * 1000; 225 while ((readl(&i2c->IICSTAT) & I2CSTAT_BSY) && (i > 0)) { 226 udelay(1000); 227 i--; 228 } 229 230 if (readl(&i2c->IICSTAT) & I2CSTAT_BSY) 231 return I2C_NOK_TOUT; 232 233 writel(readl(&i2c->IICCON) | 0x80, &i2c->IICCON); 234 result = I2C_OK; 235 236 switch (cmd_type) { 237 case I2C_WRITE: 238 if (addr && addr_len) { 239 writel(chip, &i2c->IICDS); 240 /* send START */ 241 writel(I2C_MODE_MT | I2C_TXRX_ENA | I2C_START_STOP, 242 &i2c->IICSTAT); 243 i = 0; 244 while ((i < addr_len) && (result == I2C_OK)) { 245 result = WaitForXfer(); 246 writel(addr[i], &i2c->IICDS); 247 ReadWriteByte(); 248 i++; 249 } 250 i = 0; 251 while ((i < data_len) && (result == I2C_OK)) { 252 result = WaitForXfer(); 253 writel(data[i], &i2c->IICDS); 254 ReadWriteByte(); 255 i++; 256 } 257 } else { 258 writel(chip, &i2c->IICDS); 259 /* send START */ 260 writel(I2C_MODE_MT | I2C_TXRX_ENA | I2C_START_STOP, 261 &i2c->IICSTAT); 262 i = 0; 263 while ((i < data_len) && (result = I2C_OK)) { 264 result = WaitForXfer(); 265 writel(data[i], &i2c->IICDS); 266 ReadWriteByte(); 267 i++; 268 } 269 } 270 271 if (result == I2C_OK) 272 result = WaitForXfer(); 273 274 /* send STOP */ 275 writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->IICSTAT); 276 ReadWriteByte(); 277 break; 278 279 case I2C_READ: 280 if (addr && addr_len) { 281 writel(I2C_MODE_MT | I2C_TXRX_ENA, &i2c->IICSTAT); 282 writel(chip, &i2c->IICDS); 283 /* send START */ 284 writel(readl(&i2c->IICSTAT) | I2C_START_STOP, 285 &i2c->IICSTAT); 286 result = WaitForXfer(); 287 if (IsACK()) { 288 i = 0; 289 while ((i < addr_len) && (result == I2C_OK)) { 290 writel(addr[i], &i2c->IICDS); 291 ReadWriteByte(); 292 result = WaitForXfer(); 293 i++; 294 } 295 296 writel(chip, &i2c->IICDS); 297 /* resend START */ 298 writel(I2C_MODE_MR | I2C_TXRX_ENA | 299 I2C_START_STOP, &i2c->IICSTAT); 300 ReadWriteByte(); 301 result = WaitForXfer(); 302 i = 0; 303 while ((i < data_len) && (result == I2C_OK)) { 304 /* disable ACK for final READ */ 305 if (i == data_len - 1) 306 writel(readl(&i2c->IICCON) 307 & ~0x80, &i2c->IICCON); 308 ReadWriteByte(); 309 result = WaitForXfer(); 310 data[i] = readl(&i2c->IICDS); 311 i++; 312 } 313 } else { 314 result = I2C_NACK; 315 } 316 317 } else { 318 writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->IICSTAT); 319 writel(chip, &i2c->IICDS); 320 /* send START */ 321 writel(readl(&i2c->IICSTAT) | I2C_START_STOP, 322 &i2c->IICSTAT); 323 result = WaitForXfer(); 324 325 if (IsACK()) { 326 i = 0; 327 while ((i < data_len) && (result == I2C_OK)) { 328 /* disable ACK for final READ */ 329 if (i == data_len - 1) 330 writel(readl(&i2c->IICCON) & 331 ~0x80, &i2c->IICCON); 332 ReadWriteByte(); 333 result = WaitForXfer(); 334 data[i] = readl(&i2c->IICDS); 335 i++; 336 } 337 } else { 338 result = I2C_NACK; 339 } 340 } 341 342 /* send STOP */ 343 writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->IICSTAT); 344 ReadWriteByte(); 345 break; 346 347 default: 348 printf("i2c_transfer: bad call\n"); 349 result = I2C_NOK; 350 break; 351 } 352 353 return (result); 354 } 355 356 int i2c_probe(uchar chip) 357 { 358 uchar buf[1]; 359 360 buf[0] = 0; 361 362 /* 363 * What is needed is to send the chip address and verify that the 364 * address was <ACK>ed (i.e. there was a chip at that address which 365 * drove the data line low). 366 */ 367 return i2c_transfer(I2C_READ, chip << 1, 0, 0, buf, 1) != I2C_OK; 368 } 369 370 int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) 371 { 372 uchar xaddr[4]; 373 int ret; 374 375 if (alen > 4) { 376 printf("I2C read: addr len %d not supported\n", alen); 377 return 1; 378 } 379 380 if (alen > 0) { 381 xaddr[0] = (addr >> 24) & 0xFF; 382 xaddr[1] = (addr >> 16) & 0xFF; 383 xaddr[2] = (addr >> 8) & 0xFF; 384 xaddr[3] = addr & 0xFF; 385 } 386 387 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 388 /* 389 * EEPROM chips that implement "address overflow" are ones 390 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of 391 * address and the extra bits end up in the "chip address" 392 * bit slots. This makes a 24WC08 (1Kbyte) chip look like 393 * four 256 byte chips. 394 * 395 * Note that we consider the length of the address field to 396 * still be one byte because the extra address bits are 397 * hidden in the chip address. 398 */ 399 if (alen > 0) 400 chip |= ((addr >> (alen * 8)) & 401 CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW); 402 #endif 403 if ((ret = 404 i2c_transfer(I2C_READ, chip << 1, &xaddr[4 - alen], alen, 405 buffer, len)) != 0) { 406 printf("I2c read: failed %d\n", ret); 407 return 1; 408 } 409 return 0; 410 } 411 412 int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len) 413 { 414 uchar xaddr[4]; 415 416 if (alen > 4) { 417 printf("I2C write: addr len %d not supported\n", alen); 418 return 1; 419 } 420 421 if (alen > 0) { 422 xaddr[0] = (addr >> 24) & 0xFF; 423 xaddr[1] = (addr >> 16) & 0xFF; 424 xaddr[2] = (addr >> 8) & 0xFF; 425 xaddr[3] = addr & 0xFF; 426 } 427 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 428 /* 429 * EEPROM chips that implement "address overflow" are ones 430 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of 431 * address and the extra bits end up in the "chip address" 432 * bit slots. This makes a 24WC08 (1Kbyte) chip look like 433 * four 256 byte chips. 434 * 435 * Note that we consider the length of the address field to 436 * still be one byte because the extra address bits are 437 * hidden in the chip address. 438 */ 439 if (alen > 0) 440 chip |= ((addr >> (alen * 8)) & 441 CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW); 442 #endif 443 return (i2c_transfer 444 (I2C_WRITE, chip << 1, &xaddr[4 - alen], alen, buffer, 445 len) != 0); 446 } 447 #endif /* CONFIG_HARD_I2C */ 448