1 /* 2 * Freescale i.MX28 I2C Driver 3 * 4 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> 5 * on behalf of DENX Software Engineering GmbH 6 * 7 * Partly based on Linux kernel i2c-mxs.c driver: 8 * Copyright (C) 2011 Wolfram Sang, Pengutronix e.K. 9 * 10 * Which was based on a (non-working) driver which was: 11 * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. 12 * 13 * SPDX-License-Identifier: GPL-2.0+ 14 */ 15 16 #include <common.h> 17 #include <malloc.h> 18 #include <i2c.h> 19 #include <asm/errno.h> 20 #include <asm/io.h> 21 #include <asm/arch/clock.h> 22 #include <asm/arch/imx-regs.h> 23 #include <asm/arch/sys_proto.h> 24 25 #define MXS_I2C_MAX_TIMEOUT 1000000 26 27 static void mxs_i2c_reset(void) 28 { 29 struct mxs_i2c_regs *i2c_regs = (struct mxs_i2c_regs *)MXS_I2C0_BASE; 30 int ret; 31 int speed = i2c_get_bus_speed(); 32 33 ret = mxs_reset_block(&i2c_regs->hw_i2c_ctrl0_reg); 34 if (ret) { 35 debug("MXS I2C: Block reset timeout\n"); 36 return; 37 } 38 39 writel(I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ | I2C_CTRL1_NO_SLAVE_ACK_IRQ | 40 I2C_CTRL1_EARLY_TERM_IRQ | I2C_CTRL1_MASTER_LOSS_IRQ | 41 I2C_CTRL1_SLAVE_STOP_IRQ | I2C_CTRL1_SLAVE_IRQ, 42 &i2c_regs->hw_i2c_ctrl1_clr); 43 44 writel(I2C_QUEUECTRL_PIO_QUEUE_MODE, &i2c_regs->hw_i2c_queuectrl_set); 45 46 i2c_set_bus_speed(speed); 47 } 48 49 static void mxs_i2c_setup_read(uint8_t chip, int len) 50 { 51 struct mxs_i2c_regs *i2c_regs = (struct mxs_i2c_regs *)MXS_I2C0_BASE; 52 53 writel(I2C_QUEUECMD_RETAIN_CLOCK | I2C_QUEUECMD_PRE_SEND_START | 54 I2C_QUEUECMD_MASTER_MODE | I2C_QUEUECMD_DIRECTION | 55 (1 << I2C_QUEUECMD_XFER_COUNT_OFFSET), 56 &i2c_regs->hw_i2c_queuecmd); 57 58 writel((chip << 1) | 1, &i2c_regs->hw_i2c_data); 59 60 writel(I2C_QUEUECMD_SEND_NAK_ON_LAST | I2C_QUEUECMD_MASTER_MODE | 61 (len << I2C_QUEUECMD_XFER_COUNT_OFFSET) | 62 I2C_QUEUECMD_POST_SEND_STOP, &i2c_regs->hw_i2c_queuecmd); 63 64 writel(I2C_QUEUECTRL_QUEUE_RUN, &i2c_regs->hw_i2c_queuectrl_set); 65 } 66 67 static void mxs_i2c_write(uchar chip, uint addr, int alen, 68 uchar *buf, int blen, int stop) 69 { 70 struct mxs_i2c_regs *i2c_regs = (struct mxs_i2c_regs *)MXS_I2C0_BASE; 71 uint32_t data; 72 int i, remain, off; 73 74 if ((alen > 4) || (alen == 0)) { 75 debug("MXS I2C: Invalid address length\n"); 76 return; 77 } 78 79 if (stop) 80 stop = I2C_QUEUECMD_POST_SEND_STOP; 81 82 writel(I2C_QUEUECMD_PRE_SEND_START | 83 I2C_QUEUECMD_MASTER_MODE | I2C_QUEUECMD_DIRECTION | 84 ((blen + alen + 1) << I2C_QUEUECMD_XFER_COUNT_OFFSET) | stop, 85 &i2c_regs->hw_i2c_queuecmd); 86 87 data = (chip << 1) << 24; 88 89 for (i = 0; i < alen; i++) { 90 data >>= 8; 91 data |= ((char *)&addr)[alen - i - 1] << 24; 92 if ((i & 3) == 2) 93 writel(data, &i2c_regs->hw_i2c_data); 94 } 95 96 off = i; 97 for (; i < off + blen; i++) { 98 data >>= 8; 99 data |= buf[i - off] << 24; 100 if ((i & 3) == 2) 101 writel(data, &i2c_regs->hw_i2c_data); 102 } 103 104 remain = 24 - ((i & 3) * 8); 105 if (remain) 106 writel(data >> remain, &i2c_regs->hw_i2c_data); 107 108 writel(I2C_QUEUECTRL_QUEUE_RUN, &i2c_regs->hw_i2c_queuectrl_set); 109 } 110 111 static int mxs_i2c_wait_for_ack(void) 112 { 113 struct mxs_i2c_regs *i2c_regs = (struct mxs_i2c_regs *)MXS_I2C0_BASE; 114 uint32_t tmp; 115 int timeout = MXS_I2C_MAX_TIMEOUT; 116 117 for (;;) { 118 tmp = readl(&i2c_regs->hw_i2c_ctrl1); 119 if (tmp & I2C_CTRL1_NO_SLAVE_ACK_IRQ) { 120 debug("MXS I2C: No slave ACK\n"); 121 goto err; 122 } 123 124 if (tmp & ( 125 I2C_CTRL1_EARLY_TERM_IRQ | I2C_CTRL1_MASTER_LOSS_IRQ | 126 I2C_CTRL1_SLAVE_STOP_IRQ | I2C_CTRL1_SLAVE_IRQ)) { 127 debug("MXS I2C: Error (CTRL1 = %08x)\n", tmp); 128 goto err; 129 } 130 131 if (tmp & I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ) 132 break; 133 134 if (!timeout--) { 135 debug("MXS I2C: Operation timed out\n"); 136 goto err; 137 } 138 139 udelay(1); 140 } 141 142 return 0; 143 144 err: 145 mxs_i2c_reset(); 146 return 1; 147 } 148 149 int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) 150 { 151 struct mxs_i2c_regs *i2c_regs = (struct mxs_i2c_regs *)MXS_I2C0_BASE; 152 uint32_t tmp = 0; 153 int timeout = MXS_I2C_MAX_TIMEOUT; 154 int ret; 155 int i; 156 157 mxs_i2c_write(chip, addr, alen, NULL, 0, 0); 158 ret = mxs_i2c_wait_for_ack(); 159 if (ret) { 160 debug("MXS I2C: Failed writing address\n"); 161 return ret; 162 } 163 164 mxs_i2c_setup_read(chip, len); 165 ret = mxs_i2c_wait_for_ack(); 166 if (ret) { 167 debug("MXS I2C: Failed reading address\n"); 168 return ret; 169 } 170 171 for (i = 0; i < len; i++) { 172 if (!(i & 3)) { 173 while (--timeout) { 174 tmp = readl(&i2c_regs->hw_i2c_queuestat); 175 if (!(tmp & I2C_QUEUESTAT_RD_QUEUE_EMPTY)) 176 break; 177 } 178 179 if (!timeout) { 180 debug("MXS I2C: Failed receiving data!\n"); 181 return -ETIMEDOUT; 182 } 183 184 tmp = readl(&i2c_regs->hw_i2c_queuedata); 185 } 186 buffer[i] = tmp & 0xff; 187 tmp >>= 8; 188 } 189 190 return 0; 191 } 192 193 int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len) 194 { 195 int ret; 196 mxs_i2c_write(chip, addr, alen, buffer, len, 1); 197 ret = mxs_i2c_wait_for_ack(); 198 if (ret) 199 debug("MXS I2C: Failed writing address\n"); 200 201 return ret; 202 } 203 204 int i2c_probe(uchar chip) 205 { 206 int ret; 207 mxs_i2c_write(chip, 0, 1, NULL, 0, 1); 208 ret = mxs_i2c_wait_for_ack(); 209 mxs_i2c_reset(); 210 return ret; 211 } 212 213 int i2c_set_bus_speed(unsigned int speed) 214 { 215 struct mxs_i2c_regs *i2c_regs = (struct mxs_i2c_regs *)MXS_I2C0_BASE; 216 /* 217 * The timing derivation algorithm. There is no documentation for this 218 * algorithm available, it was derived by using the scope and fiddling 219 * with constants until the result observed on the scope was good enough 220 * for 20kHz, 50kHz, 100kHz, 200kHz, 300kHz and 400kHz. It should be 221 * possible to assume the algorithm works for other frequencies as well. 222 * 223 * Note it was necessary to cap the frequency on both ends as it's not 224 * possible to configure completely arbitrary frequency for the I2C bus 225 * clock. 226 */ 227 uint32_t clk = mxc_get_clock(MXC_XTAL_CLK); 228 uint32_t base = ((clk / speed) - 38) / 2; 229 uint16_t high_count = base + 3; 230 uint16_t low_count = base - 3; 231 uint16_t rcv_count = (high_count * 3) / 4; 232 uint16_t xmit_count = low_count / 4; 233 234 if (speed > 540000) { 235 printf("MXS I2C: Speed too high (%d Hz)\n", speed); 236 return -EINVAL; 237 } 238 239 if (speed < 12000) { 240 printf("MXS I2C: Speed too low (%d Hz)\n", speed); 241 return -EINVAL; 242 } 243 244 writel((high_count << 16) | rcv_count, &i2c_regs->hw_i2c_timing0); 245 writel((low_count << 16) | xmit_count, &i2c_regs->hw_i2c_timing1); 246 247 writel((0x0030 << I2C_TIMING2_BUS_FREE_OFFSET) | 248 (0x0030 << I2C_TIMING2_LEADIN_COUNT_OFFSET), 249 &i2c_regs->hw_i2c_timing2); 250 251 return 0; 252 } 253 254 unsigned int i2c_get_bus_speed(void) 255 { 256 struct mxs_i2c_regs *i2c_regs = (struct mxs_i2c_regs *)MXS_I2C0_BASE; 257 uint32_t clk = mxc_get_clock(MXC_XTAL_CLK); 258 uint32_t timing0; 259 260 timing0 = readl(&i2c_regs->hw_i2c_timing0); 261 /* 262 * This is a reverse version of the algorithm presented in 263 * i2c_set_bus_speed(). Please refer there for details. 264 */ 265 return clk / ((((timing0 >> 16) - 3) * 2) + 38); 266 } 267 268 void i2c_init(int speed, int slaveadd) 269 { 270 mxs_i2c_reset(); 271 i2c_set_bus_speed(speed); 272 273 return; 274 } 275