1 /* 2 * i2c driver for Freescale i.MX series 3 * 4 * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> 5 * (c) 2011 Marek Vasut <marek.vasut@gmail.com> 6 * 7 * Based on i2c-imx.c from linux kernel: 8 * Copyright (C) 2005 Torsten Koschorrek <koschorrek at synertronixx.de> 9 * Copyright (C) 2005 Matthias Blaschke <blaschke at synertronixx.de> 10 * Copyright (C) 2007 RightHand Technologies, Inc. 11 * Copyright (C) 2008 Darius Augulis <darius.augulis at teltonika.lt> 12 * 13 * 14 * See file CREDITS for list of people who contributed to this 15 * project. 16 * 17 * This program is free software; you can redistribute it and/or 18 * modify it under the terms of the GNU General Public License as 19 * published by the Free Software Foundation; either version 2 of 20 * the License, or (at your option) any later version. 21 * 22 * This program is distributed in the hope that it will be useful, 23 * but WITHOUT ANY WARRANTY; without even the implied warranty of 24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 25 * GNU General Public License for more details. 26 * 27 * You should have received a copy of the GNU General Public License 28 * along with this program; if not, write to the Free Software 29 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 30 * MA 02111-1307 USA 31 */ 32 33 #include <common.h> 34 #include <asm/arch/clock.h> 35 #include <asm/arch/imx-regs.h> 36 #include <asm/errno.h> 37 #include <asm/io.h> 38 #include <i2c.h> 39 #include <watchdog.h> 40 41 #ifdef I2C_QUIRK_REG 42 struct mxc_i2c_regs { 43 uint8_t iadr; 44 uint8_t ifdr; 45 uint8_t i2cr; 46 uint8_t i2sr; 47 uint8_t i2dr; 48 }; 49 #else 50 struct mxc_i2c_regs { 51 uint32_t iadr; 52 uint32_t ifdr; 53 uint32_t i2cr; 54 uint32_t i2sr; 55 uint32_t i2dr; 56 }; 57 #endif 58 59 #define I2CR_IIEN (1 << 6) 60 #define I2CR_MSTA (1 << 5) 61 #define I2CR_MTX (1 << 4) 62 #define I2CR_TX_NO_AK (1 << 3) 63 #define I2CR_RSTA (1 << 2) 64 65 #define I2SR_ICF (1 << 7) 66 #define I2SR_IBB (1 << 5) 67 #define I2SR_IAL (1 << 4) 68 #define I2SR_IIF (1 << 1) 69 #define I2SR_RX_NO_AK (1 << 0) 70 71 #ifdef I2C_QUIRK_REG 72 #define I2CR_IEN (0 << 7) 73 #define I2CR_IDIS (1 << 7) 74 #define I2SR_IIF_CLEAR (1 << 1) 75 #else 76 #define I2CR_IEN (1 << 7) 77 #define I2CR_IDIS (0 << 7) 78 #define I2SR_IIF_CLEAR (0 << 1) 79 #endif 80 81 #if defined(CONFIG_HARD_I2C) && !defined(CONFIG_SYS_I2C_BASE) 82 #error "define CONFIG_SYS_I2C_BASE to use the mxc_i2c driver" 83 #endif 84 85 #ifdef I2C_QUIRK_REG 86 static u16 i2c_clk_div[60][2] = { 87 { 20, 0x00 }, { 22, 0x01 }, { 24, 0x02 }, { 26, 0x03 }, 88 { 28, 0x04 }, { 30, 0x05 }, { 32, 0x09 }, { 34, 0x06 }, 89 { 36, 0x0A }, { 40, 0x07 }, { 44, 0x0C }, { 48, 0x0D }, 90 { 52, 0x43 }, { 56, 0x0E }, { 60, 0x45 }, { 64, 0x12 }, 91 { 68, 0x0F }, { 72, 0x13 }, { 80, 0x14 }, { 88, 0x15 }, 92 { 96, 0x19 }, { 104, 0x16 }, { 112, 0x1A }, { 128, 0x17 }, 93 { 136, 0x4F }, { 144, 0x1C }, { 160, 0x1D }, { 176, 0x55 }, 94 { 192, 0x1E }, { 208, 0x56 }, { 224, 0x22 }, { 228, 0x24 }, 95 { 240, 0x1F }, { 256, 0x23 }, { 288, 0x5C }, { 320, 0x25 }, 96 { 384, 0x26 }, { 448, 0x2A }, { 480, 0x27 }, { 512, 0x2B }, 97 { 576, 0x2C }, { 640, 0x2D }, { 768, 0x31 }, { 896, 0x32 }, 98 { 960, 0x2F }, { 1024, 0x33 }, { 1152, 0x34 }, { 1280, 0x35 }, 99 { 1536, 0x36 }, { 1792, 0x3A }, { 1920, 0x37 }, { 2048, 0x3B }, 100 { 2304, 0x3C }, { 2560, 0x3D }, { 3072, 0x3E }, { 3584, 0x7A }, 101 { 3840, 0x3F }, { 4096, 0x7B }, { 5120, 0x7D }, { 6144, 0x7E }, 102 }; 103 #else 104 static u16 i2c_clk_div[50][2] = { 105 { 22, 0x20 }, { 24, 0x21 }, { 26, 0x22 }, { 28, 0x23 }, 106 { 30, 0x00 }, { 32, 0x24 }, { 36, 0x25 }, { 40, 0x26 }, 107 { 42, 0x03 }, { 44, 0x27 }, { 48, 0x28 }, { 52, 0x05 }, 108 { 56, 0x29 }, { 60, 0x06 }, { 64, 0x2A }, { 72, 0x2B }, 109 { 80, 0x2C }, { 88, 0x09 }, { 96, 0x2D }, { 104, 0x0A }, 110 { 112, 0x2E }, { 128, 0x2F }, { 144, 0x0C }, { 160, 0x30 }, 111 { 192, 0x31 }, { 224, 0x32 }, { 240, 0x0F }, { 256, 0x33 }, 112 { 288, 0x10 }, { 320, 0x34 }, { 384, 0x35 }, { 448, 0x36 }, 113 { 480, 0x13 }, { 512, 0x37 }, { 576, 0x14 }, { 640, 0x38 }, 114 { 768, 0x39 }, { 896, 0x3A }, { 960, 0x17 }, { 1024, 0x3B }, 115 { 1152, 0x18 }, { 1280, 0x3C }, { 1536, 0x3D }, { 1792, 0x3E }, 116 { 1920, 0x1B }, { 2048, 0x3F }, { 2304, 0x1C }, { 2560, 0x1D }, 117 { 3072, 0x1E }, { 3840, 0x1F } 118 }; 119 #endif 120 121 /* 122 * Calculate and set proper clock divider 123 */ 124 static uint8_t i2c_imx_get_clk(unsigned int rate) 125 { 126 unsigned int i2c_clk_rate; 127 unsigned int div; 128 u8 clk_div; 129 130 #if defined(CONFIG_MX31) 131 struct clock_control_regs *sc_regs = 132 (struct clock_control_regs *)CCM_BASE; 133 134 /* start the required I2C clock */ 135 writel(readl(&sc_regs->cgr0) | (3 << CONFIG_SYS_I2C_CLK_OFFSET), 136 &sc_regs->cgr0); 137 #endif 138 139 /* Divider value calculation */ 140 i2c_clk_rate = mxc_get_clock(MXC_I2C_CLK); 141 div = (i2c_clk_rate + rate - 1) / rate; 142 if (div < i2c_clk_div[0][0]) 143 clk_div = 0; 144 else if (div > i2c_clk_div[ARRAY_SIZE(i2c_clk_div) - 1][0]) 145 clk_div = ARRAY_SIZE(i2c_clk_div) - 1; 146 else 147 for (clk_div = 0; i2c_clk_div[clk_div][0] < div; clk_div++) 148 ; 149 150 /* Store divider value */ 151 return clk_div; 152 } 153 154 /* 155 * Set I2C Bus speed 156 */ 157 static int bus_i2c_set_bus_speed(void *base, int speed) 158 { 159 struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)base; 160 u8 clk_idx = i2c_imx_get_clk(speed); 161 u8 idx = i2c_clk_div[clk_idx][1]; 162 163 /* Store divider value */ 164 writeb(idx, &i2c_regs->ifdr); 165 166 /* Reset module */ 167 writeb(I2CR_IDIS, &i2c_regs->i2cr); 168 writeb(0, &i2c_regs->i2sr); 169 return 0; 170 } 171 172 /* 173 * Get I2C Speed 174 */ 175 static unsigned int bus_i2c_get_bus_speed(void *base) 176 { 177 struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)base; 178 u8 clk_idx = readb(&i2c_regs->ifdr); 179 u8 clk_div; 180 181 for (clk_div = 0; i2c_clk_div[clk_div][1] != clk_idx; clk_div++) 182 ; 183 184 return mxc_get_clock(MXC_I2C_CLK) / i2c_clk_div[clk_div][0]; 185 } 186 187 #define ST_BUS_IDLE (0 | (I2SR_IBB << 8)) 188 #define ST_BUS_BUSY (I2SR_IBB | (I2SR_IBB << 8)) 189 #define ST_IIF (I2SR_IIF | (I2SR_IIF << 8)) 190 191 static int wait_for_sr_state(struct mxc_i2c_regs *i2c_regs, unsigned state) 192 { 193 unsigned sr; 194 ulong elapsed; 195 ulong start_time = get_timer(0); 196 for (;;) { 197 sr = readb(&i2c_regs->i2sr); 198 if (sr & I2SR_IAL) { 199 #ifdef I2C_QUIRK_REG 200 writeb(sr | I2SR_IAL, &i2c_regs->i2sr); 201 #else 202 writeb(sr & ~I2SR_IAL, &i2c_regs->i2sr); 203 #endif 204 printf("%s: Arbitration lost sr=%x cr=%x state=%x\n", 205 __func__, sr, readb(&i2c_regs->i2cr), state); 206 return -ERESTART; 207 } 208 if ((sr & (state >> 8)) == (unsigned char)state) 209 return sr; 210 WATCHDOG_RESET(); 211 elapsed = get_timer(start_time); 212 if (elapsed > (CONFIG_SYS_HZ / 10)) /* .1 seconds */ 213 break; 214 } 215 printf("%s: failed sr=%x cr=%x state=%x\n", __func__, 216 sr, readb(&i2c_regs->i2cr), state); 217 return -ETIMEDOUT; 218 } 219 220 static int tx_byte(struct mxc_i2c_regs *i2c_regs, u8 byte) 221 { 222 int ret; 223 224 writeb(I2SR_IIF_CLEAR, &i2c_regs->i2sr); 225 writeb(byte, &i2c_regs->i2dr); 226 ret = wait_for_sr_state(i2c_regs, ST_IIF); 227 if (ret < 0) 228 return ret; 229 if (ret & I2SR_RX_NO_AK) 230 return -ENODEV; 231 return 0; 232 } 233 234 /* 235 * Stop I2C transaction 236 */ 237 static void i2c_imx_stop(struct mxc_i2c_regs *i2c_regs) 238 { 239 int ret; 240 unsigned int temp = readb(&i2c_regs->i2cr); 241 242 temp &= ~(I2CR_MSTA | I2CR_MTX); 243 writeb(temp, &i2c_regs->i2cr); 244 ret = wait_for_sr_state(i2c_regs, ST_BUS_IDLE); 245 if (ret < 0) 246 printf("%s:trigger stop failed\n", __func__); 247 } 248 249 /* 250 * Send start signal, chip address and 251 * write register address 252 */ 253 static int i2c_init_transfer_(struct mxc_i2c_regs *i2c_regs, 254 uchar chip, uint addr, int alen) 255 { 256 unsigned int temp; 257 int ret; 258 259 /* Enable I2C controller */ 260 #ifdef I2C_QUIRK_REG 261 if (readb(&i2c_regs->i2cr) & I2CR_IDIS) { 262 #else 263 if (!(readb(&i2c_regs->i2cr) & I2CR_IEN)) { 264 #endif 265 writeb(I2CR_IEN, &i2c_regs->i2cr); 266 /* Wait for controller to be stable */ 267 udelay(50); 268 } 269 if (readb(&i2c_regs->iadr) == (chip << 1)) 270 writeb((chip << 1) ^ 2, &i2c_regs->iadr); 271 writeb(I2SR_IIF_CLEAR, &i2c_regs->i2sr); 272 ret = wait_for_sr_state(i2c_regs, ST_BUS_IDLE); 273 if (ret < 0) 274 return ret; 275 276 /* Start I2C transaction */ 277 temp = readb(&i2c_regs->i2cr); 278 temp |= I2CR_MSTA; 279 writeb(temp, &i2c_regs->i2cr); 280 281 ret = wait_for_sr_state(i2c_regs, ST_BUS_BUSY); 282 if (ret < 0) 283 return ret; 284 285 temp |= I2CR_MTX | I2CR_TX_NO_AK; 286 writeb(temp, &i2c_regs->i2cr); 287 288 /* write slave address */ 289 ret = tx_byte(i2c_regs, chip << 1); 290 if (ret < 0) 291 return ret; 292 293 while (alen--) { 294 ret = tx_byte(i2c_regs, (addr >> (alen * 8)) & 0xff); 295 if (ret < 0) 296 return ret; 297 } 298 return 0; 299 } 300 301 static int i2c_idle_bus(void *base); 302 303 static int i2c_init_transfer(struct mxc_i2c_regs *i2c_regs, 304 uchar chip, uint addr, int alen) 305 { 306 int retry; 307 int ret; 308 for (retry = 0; retry < 3; retry++) { 309 ret = i2c_init_transfer_(i2c_regs, chip, addr, alen); 310 if (ret >= 0) 311 return 0; 312 i2c_imx_stop(i2c_regs); 313 if (ret == -ENODEV) 314 return ret; 315 316 printf("%s: failed for chip 0x%x retry=%d\n", __func__, chip, 317 retry); 318 if (ret != -ERESTART) 319 /* Disable controller */ 320 writeb(I2CR_IDIS, &i2c_regs->i2cr); 321 udelay(100); 322 if (i2c_idle_bus(i2c_regs) < 0) 323 break; 324 } 325 printf("%s: give up i2c_regs=%p\n", __func__, i2c_regs); 326 return ret; 327 } 328 329 /* 330 * Read data from I2C device 331 */ 332 int bus_i2c_read(void *base, uchar chip, uint addr, int alen, uchar *buf, 333 int len) 334 { 335 int ret; 336 unsigned int temp; 337 int i; 338 struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)base; 339 340 ret = i2c_init_transfer(i2c_regs, chip, addr, alen); 341 if (ret < 0) 342 return ret; 343 344 temp = readb(&i2c_regs->i2cr); 345 temp |= I2CR_RSTA; 346 writeb(temp, &i2c_regs->i2cr); 347 348 ret = tx_byte(i2c_regs, (chip << 1) | 1); 349 if (ret < 0) { 350 i2c_imx_stop(i2c_regs); 351 return ret; 352 } 353 354 /* setup bus to read data */ 355 temp = readb(&i2c_regs->i2cr); 356 temp &= ~(I2CR_MTX | I2CR_TX_NO_AK); 357 if (len == 1) 358 temp |= I2CR_TX_NO_AK; 359 writeb(temp, &i2c_regs->i2cr); 360 writeb(I2SR_IIF_CLEAR, &i2c_regs->i2sr); 361 readb(&i2c_regs->i2dr); /* dummy read to clear ICF */ 362 363 /* read data */ 364 for (i = 0; i < len; i++) { 365 ret = wait_for_sr_state(i2c_regs, ST_IIF); 366 if (ret < 0) { 367 i2c_imx_stop(i2c_regs); 368 return ret; 369 } 370 371 /* 372 * It must generate STOP before read I2DR to prevent 373 * controller from generating another clock cycle 374 */ 375 if (i == (len - 1)) { 376 i2c_imx_stop(i2c_regs); 377 } else if (i == (len - 2)) { 378 temp = readb(&i2c_regs->i2cr); 379 temp |= I2CR_TX_NO_AK; 380 writeb(temp, &i2c_regs->i2cr); 381 } 382 writeb(I2SR_IIF_CLEAR, &i2c_regs->i2sr); 383 buf[i] = readb(&i2c_regs->i2dr); 384 } 385 i2c_imx_stop(i2c_regs); 386 return 0; 387 } 388 389 /* 390 * Write data to I2C device 391 */ 392 int bus_i2c_write(void *base, uchar chip, uint addr, int alen, 393 const uchar *buf, int len) 394 { 395 int ret; 396 int i; 397 struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)base; 398 399 ret = i2c_init_transfer(i2c_regs, chip, addr, alen); 400 if (ret < 0) 401 return ret; 402 403 for (i = 0; i < len; i++) { 404 ret = tx_byte(i2c_regs, buf[i]); 405 if (ret < 0) 406 break; 407 } 408 i2c_imx_stop(i2c_regs); 409 return ret; 410 } 411 412 struct i2c_parms { 413 void *base; 414 void *idle_bus_data; 415 int (*idle_bus_fn)(void *p); 416 }; 417 418 struct sram_data { 419 unsigned curr_i2c_bus; 420 struct i2c_parms i2c_data[3]; 421 }; 422 423 /* 424 * For SPL boot some boards need i2c before SDRAM is initialized so force 425 * variables to live in SRAM 426 */ 427 static struct sram_data __attribute__((section(".data"))) srdata; 428 429 void *get_base(void) 430 { 431 #ifdef CONFIG_SYS_I2C_BASE 432 #ifdef CONFIG_I2C_MULTI_BUS 433 void *ret = srdata.i2c_data[srdata.curr_i2c_bus].base; 434 if (ret) 435 return ret; 436 #endif 437 return (void *)CONFIG_SYS_I2C_BASE; 438 #elif defined(CONFIG_I2C_MULTI_BUS) 439 return srdata.i2c_data[srdata.curr_i2c_bus].base; 440 #else 441 return srdata.i2c_data[0].base; 442 #endif 443 } 444 445 static struct i2c_parms *i2c_get_parms(void *base) 446 { 447 int i = 0; 448 struct i2c_parms *p = srdata.i2c_data; 449 while (i < ARRAY_SIZE(srdata.i2c_data)) { 450 if (p->base == base) 451 return p; 452 p++; 453 i++; 454 } 455 printf("Invalid I2C base: %p\n", base); 456 return NULL; 457 } 458 459 static int i2c_idle_bus(void *base) 460 { 461 struct i2c_parms *p = i2c_get_parms(base); 462 if (p && p->idle_bus_fn) 463 return p->idle_bus_fn(p->idle_bus_data); 464 return 0; 465 } 466 467 #ifdef CONFIG_I2C_MULTI_BUS 468 unsigned int i2c_get_bus_num(void) 469 { 470 return srdata.curr_i2c_bus; 471 } 472 473 int i2c_set_bus_num(unsigned bus_idx) 474 { 475 if (bus_idx >= ARRAY_SIZE(srdata.i2c_data)) 476 return -1; 477 if (!srdata.i2c_data[bus_idx].base) 478 return -1; 479 srdata.curr_i2c_bus = bus_idx; 480 return 0; 481 } 482 #endif 483 484 int i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len) 485 { 486 return bus_i2c_read(get_base(), chip, addr, alen, buf, len); 487 } 488 489 int i2c_write(uchar chip, uint addr, int alen, uchar *buf, int len) 490 { 491 return bus_i2c_write(get_base(), chip, addr, alen, buf, len); 492 } 493 494 /* 495 * Test if a chip at a given address responds (probe the chip) 496 */ 497 int i2c_probe(uchar chip) 498 { 499 return bus_i2c_write(get_base(), chip, 0, 0, NULL, 0); 500 } 501 502 void bus_i2c_init(void *base, int speed, int unused, 503 int (*idle_bus_fn)(void *p), void *idle_bus_data) 504 { 505 int i = 0; 506 struct i2c_parms *p = srdata.i2c_data; 507 if (!base) 508 return; 509 for (;;) { 510 if (!p->base || (p->base == base)) { 511 p->base = base; 512 if (idle_bus_fn) { 513 p->idle_bus_fn = idle_bus_fn; 514 p->idle_bus_data = idle_bus_data; 515 } 516 break; 517 } 518 p++; 519 i++; 520 if (i >= ARRAY_SIZE(srdata.i2c_data)) 521 return; 522 } 523 bus_i2c_set_bus_speed(base, speed); 524 } 525 526 /* 527 * Init I2C Bus 528 */ 529 void i2c_init(int speed, int unused) 530 { 531 bus_i2c_init(get_base(), speed, unused, NULL, NULL); 532 } 533 534 /* 535 * Set I2C Speed 536 */ 537 int i2c_set_bus_speed(unsigned int speed) 538 { 539 return bus_i2c_set_bus_speed(get_base(), speed); 540 } 541 542 /* 543 * Get I2C Speed 544 */ 545 unsigned int i2c_get_bus_speed(void) 546 { 547 return bus_i2c_get_bus_speed(get_base()); 548 } 549