1 /* 2 * i2c driver for Freescale i.MX series 3 * 4 * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> 5 * (c) 2011 Marek Vasut <marek.vasut@gmail.com> 6 * 7 * Based on i2c-imx.c from linux kernel: 8 * Copyright (C) 2005 Torsten Koschorrek <koschorrek at synertronixx.de> 9 * Copyright (C) 2005 Matthias Blaschke <blaschke at synertronixx.de> 10 * Copyright (C) 2007 RightHand Technologies, Inc. 11 * Copyright (C) 2008 Darius Augulis <darius.augulis at teltonika.lt> 12 * 13 * 14 * See file CREDITS for list of people who contributed to this 15 * project. 16 * 17 * This program is free software; you can redistribute it and/or 18 * modify it under the terms of the GNU General Public License as 19 * published by the Free Software Foundation; either version 2 of 20 * the License, or (at your option) any later version. 21 * 22 * This program is distributed in the hope that it will be useful, 23 * but WITHOUT ANY WARRANTY; without even the implied warranty of 24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 25 * GNU General Public License for more details. 26 * 27 * You should have received a copy of the GNU General Public License 28 * along with this program; if not, write to the Free Software 29 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 30 * MA 02111-1307 USA 31 */ 32 33 #include <common.h> 34 #include <asm/arch/clock.h> 35 #include <asm/arch/imx-regs.h> 36 #include <asm/errno.h> 37 #include <asm/io.h> 38 #include <i2c.h> 39 40 struct mxc_i2c_regs { 41 uint32_t iadr; 42 uint32_t ifdr; 43 uint32_t i2cr; 44 uint32_t i2sr; 45 uint32_t i2dr; 46 }; 47 48 #define I2CR_IEN (1 << 7) 49 #define I2CR_IIEN (1 << 6) 50 #define I2CR_MSTA (1 << 5) 51 #define I2CR_MTX (1 << 4) 52 #define I2CR_TX_NO_AK (1 << 3) 53 #define I2CR_RSTA (1 << 2) 54 55 #define I2SR_ICF (1 << 7) 56 #define I2SR_IBB (1 << 5) 57 #define I2SR_IIF (1 << 1) 58 #define I2SR_RX_NO_AK (1 << 0) 59 60 #ifdef CONFIG_SYS_I2C_BASE 61 #define I2C_BASE CONFIG_SYS_I2C_BASE 62 #else 63 #error "define CONFIG_SYS_I2C_BASE to use the mxc_i2c driver" 64 #endif 65 66 #define I2C_MAX_TIMEOUT 10000 67 68 static u16 i2c_clk_div[50][2] = { 69 { 22, 0x20 }, { 24, 0x21 }, { 26, 0x22 }, { 28, 0x23 }, 70 { 30, 0x00 }, { 32, 0x24 }, { 36, 0x25 }, { 40, 0x26 }, 71 { 42, 0x03 }, { 44, 0x27 }, { 48, 0x28 }, { 52, 0x05 }, 72 { 56, 0x29 }, { 60, 0x06 }, { 64, 0x2A }, { 72, 0x2B }, 73 { 80, 0x2C }, { 88, 0x09 }, { 96, 0x2D }, { 104, 0x0A }, 74 { 112, 0x2E }, { 128, 0x2F }, { 144, 0x0C }, { 160, 0x30 }, 75 { 192, 0x31 }, { 224, 0x32 }, { 240, 0x0F }, { 256, 0x33 }, 76 { 288, 0x10 }, { 320, 0x34 }, { 384, 0x35 }, { 448, 0x36 }, 77 { 480, 0x13 }, { 512, 0x37 }, { 576, 0x14 }, { 640, 0x38 }, 78 { 768, 0x39 }, { 896, 0x3A }, { 960, 0x17 }, { 1024, 0x3B }, 79 { 1152, 0x18 }, { 1280, 0x3C }, { 1536, 0x3D }, { 1792, 0x3E }, 80 { 1920, 0x1B }, { 2048, 0x3F }, { 2304, 0x1C }, { 2560, 0x1D }, 81 { 3072, 0x1E }, { 3840, 0x1F } 82 }; 83 84 /* 85 * Calculate and set proper clock divider 86 */ 87 static uint8_t i2c_imx_get_clk(unsigned int rate) 88 { 89 unsigned int i2c_clk_rate; 90 unsigned int div; 91 u8 clk_div; 92 93 #if defined(CONFIG_MX31) 94 struct clock_control_regs *sc_regs = 95 (struct clock_control_regs *)CCM_BASE; 96 97 /* start the required I2C clock */ 98 writel(readl(&sc_regs->cgr0) | (3 << CONFIG_SYS_I2C_CLK_OFFSET), 99 &sc_regs->cgr0); 100 #endif 101 102 /* Divider value calculation */ 103 i2c_clk_rate = mxc_get_clock(MXC_IPG_PERCLK); 104 div = (i2c_clk_rate + rate - 1) / rate; 105 if (div < i2c_clk_div[0][0]) 106 clk_div = 0; 107 else if (div > i2c_clk_div[ARRAY_SIZE(i2c_clk_div) - 1][0]) 108 clk_div = ARRAY_SIZE(i2c_clk_div) - 1; 109 else 110 for (clk_div = 0; i2c_clk_div[clk_div][0] < div; clk_div++) 111 ; 112 113 /* Store divider value */ 114 return clk_div; 115 } 116 117 /* 118 * Reset I2C Controller 119 */ 120 void i2c_reset(void) 121 { 122 struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE; 123 124 writeb(0, &i2c_regs->i2cr); /* Reset module */ 125 writeb(0, &i2c_regs->i2sr); 126 } 127 128 /* 129 * Init I2C Bus 130 */ 131 void i2c_init(int speed, int unused) 132 { 133 struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE; 134 u8 clk_idx = i2c_imx_get_clk(speed); 135 u8 idx = i2c_clk_div[clk_idx][1]; 136 137 /* Store divider value */ 138 writeb(idx, &i2c_regs->ifdr); 139 140 i2c_reset(); 141 } 142 143 /* 144 * Set I2C Speed 145 */ 146 int i2c_set_bus_speed(unsigned int speed) 147 { 148 i2c_init(speed, 0); 149 return 0; 150 } 151 152 /* 153 * Get I2C Speed 154 */ 155 unsigned int i2c_get_bus_speed(void) 156 { 157 struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE; 158 u8 clk_idx = readb(&i2c_regs->ifdr); 159 u8 clk_div; 160 161 for (clk_div = 0; i2c_clk_div[clk_div][1] != clk_idx; clk_div++) 162 ; 163 164 return mxc_get_clock(MXC_IPG_PERCLK) / i2c_clk_div[clk_div][0]; 165 } 166 167 /* 168 * Wait for bus to be busy (or free if for_busy = 0) 169 * 170 * for_busy = 1: Wait for IBB to be asserted 171 * for_busy = 0: Wait for IBB to be de-asserted 172 */ 173 int i2c_imx_bus_busy(int for_busy) 174 { 175 struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE; 176 unsigned int temp; 177 178 int timeout = I2C_MAX_TIMEOUT; 179 180 while (timeout--) { 181 temp = readb(&i2c_regs->i2sr); 182 183 if (for_busy && (temp & I2SR_IBB)) 184 return 0; 185 if (!for_busy && !(temp & I2SR_IBB)) 186 return 0; 187 188 udelay(1); 189 } 190 191 return 1; 192 } 193 194 /* 195 * Wait for transaction to complete 196 */ 197 int i2c_imx_trx_complete(void) 198 { 199 struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE; 200 int timeout = I2C_MAX_TIMEOUT; 201 202 while (timeout--) { 203 if (readb(&i2c_regs->i2sr) & I2SR_IIF) 204 return 0; 205 206 udelay(1); 207 } 208 209 return -ETIMEDOUT; 210 } 211 212 static int tx_byte(struct mxc_i2c_regs *i2c_regs, u8 byte) 213 { 214 int ret; 215 216 writeb(0, &i2c_regs->i2sr); 217 writeb(byte, &i2c_regs->i2dr); 218 ret = i2c_imx_trx_complete(); 219 if (ret < 0) 220 return ret; 221 ret = readb(&i2c_regs->i2sr); 222 if (ret & I2SR_RX_NO_AK) 223 return -ENODEV; 224 return 0; 225 } 226 227 /* 228 * Start the controller 229 */ 230 int i2c_imx_start(void) 231 { 232 struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE; 233 unsigned int temp = 0; 234 int result; 235 236 /* Enable I2C controller */ 237 writeb(0, &i2c_regs->i2sr); 238 writeb(I2CR_IEN, &i2c_regs->i2cr); 239 240 /* Wait controller to be stable */ 241 udelay(50); 242 243 /* Start I2C transaction */ 244 temp = readb(&i2c_regs->i2cr); 245 temp |= I2CR_MSTA; 246 writeb(temp, &i2c_regs->i2cr); 247 248 result = i2c_imx_bus_busy(1); 249 if (result) 250 return result; 251 252 temp |= I2CR_MTX | I2CR_TX_NO_AK; 253 writeb(temp, &i2c_regs->i2cr); 254 255 return 0; 256 } 257 258 /* 259 * Stop the controller 260 */ 261 void i2c_imx_stop(void) 262 { 263 struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE; 264 unsigned int temp = 0; 265 266 /* Stop I2C transaction */ 267 temp = readb(&i2c_regs->i2cr); 268 temp &= ~(I2CR_MSTA | I2CR_MTX); 269 writeb(temp, &i2c_regs->i2cr); 270 271 i2c_imx_bus_busy(0); 272 273 /* Disable I2C controller */ 274 writeb(0, &i2c_regs->i2cr); 275 } 276 277 /* 278 * Send start signal, chip address and 279 * write register address 280 */ 281 static int i2c_init_transfer(struct mxc_i2c_regs *i2c_regs, 282 uchar chip, uint addr, int alen) 283 { 284 int ret = i2c_imx_start(); 285 if (ret) 286 goto exit; 287 288 /* write slave address */ 289 ret = tx_byte(i2c_regs, chip << 1); 290 if (ret < 0) 291 goto exit; 292 293 while (alen--) { 294 ret = tx_byte(i2c_regs, (addr >> (alen * 8)) & 0xff); 295 if (ret < 0) 296 goto exit; 297 } 298 return 0; 299 exit: 300 i2c_imx_stop(); 301 return ret; 302 } 303 304 /* 305 * Read data from I2C device 306 */ 307 int i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len) 308 { 309 struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE; 310 int ret; 311 unsigned int temp; 312 int i; 313 314 ret = i2c_init_transfer(i2c_regs, chip, addr, alen); 315 if (ret < 0) 316 return ret; 317 318 temp = readb(&i2c_regs->i2cr); 319 temp |= I2CR_RSTA; 320 writeb(temp, &i2c_regs->i2cr); 321 322 ret = tx_byte(i2c_regs, (chip << 1) | 1); 323 if (ret < 0) { 324 i2c_imx_stop(); 325 return ret; 326 } 327 328 /* setup bus to read data */ 329 temp = readb(&i2c_regs->i2cr); 330 temp &= ~(I2CR_MTX | I2CR_TX_NO_AK); 331 if (len == 1) 332 temp |= I2CR_TX_NO_AK; 333 writeb(temp, &i2c_regs->i2cr); 334 writeb(0, &i2c_regs->i2sr); 335 readb(&i2c_regs->i2dr); /* dummy read to clear ICF */ 336 337 /* read data */ 338 for (i = 0; i < len; i++) { 339 ret = i2c_imx_trx_complete(); 340 if (ret) { 341 i2c_imx_stop(); 342 return ret; 343 } 344 345 /* 346 * It must generate STOP before read I2DR to prevent 347 * controller from generating another clock cycle 348 */ 349 if (i == (len - 1)) { 350 temp = readb(&i2c_regs->i2cr); 351 temp &= ~(I2CR_MSTA | I2CR_MTX); 352 writeb(temp, &i2c_regs->i2cr); 353 i2c_imx_bus_busy(0); 354 } else if (i == (len - 2)) { 355 temp = readb(&i2c_regs->i2cr); 356 temp |= I2CR_TX_NO_AK; 357 writeb(temp, &i2c_regs->i2cr); 358 } 359 360 writeb(0, &i2c_regs->i2sr); 361 buf[i] = readb(&i2c_regs->i2dr); 362 } 363 364 i2c_imx_stop(); 365 366 return ret; 367 } 368 369 /* 370 * Write data to I2C device 371 */ 372 int i2c_write(uchar chip, uint addr, int alen, uchar *buf, int len) 373 { 374 struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE; 375 int ret; 376 int i; 377 378 ret = i2c_init_transfer(i2c_regs, chip, addr, alen); 379 if (ret < 0) 380 return ret; 381 382 for (i = 0; i < len; i++) { 383 ret = tx_byte(i2c_regs, buf[i]); 384 if (ret < 0) 385 break; 386 } 387 388 i2c_imx_stop(); 389 390 return ret; 391 } 392 393 /* 394 * Test if a chip at a given address responds (probe the chip) 395 */ 396 int i2c_probe(uchar chip) 397 { 398 return i2c_write(chip, 0, 0, NULL, 0); 399 } 400