1 /* 2 * i2c driver for Freescale i.MX series 3 * 4 * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> 5 * (c) 2011 Marek Vasut <marek.vasut@gmail.com> 6 * 7 * Based on i2c-imx.c from linux kernel: 8 * Copyright (C) 2005 Torsten Koschorrek <koschorrek at synertronixx.de> 9 * Copyright (C) 2005 Matthias Blaschke <blaschke at synertronixx.de> 10 * Copyright (C) 2007 RightHand Technologies, Inc. 11 * Copyright (C) 2008 Darius Augulis <darius.augulis at teltonika.lt> 12 * 13 * 14 * See file CREDITS for list of people who contributed to this 15 * project. 16 * 17 * This program is free software; you can redistribute it and/or 18 * modify it under the terms of the GNU General Public License as 19 * published by the Free Software Foundation; either version 2 of 20 * the License, or (at your option) any later version. 21 * 22 * This program is distributed in the hope that it will be useful, 23 * but WITHOUT ANY WARRANTY; without even the implied warranty of 24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 25 * GNU General Public License for more details. 26 * 27 * You should have received a copy of the GNU General Public License 28 * along with this program; if not, write to the Free Software 29 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 30 * MA 02111-1307 USA 31 */ 32 33 #include <common.h> 34 #include <asm/arch/clock.h> 35 #include <asm/arch/imx-regs.h> 36 #include <asm/errno.h> 37 #include <asm/io.h> 38 #include <i2c.h> 39 #include <watchdog.h> 40 41 struct mxc_i2c_regs { 42 uint32_t iadr; 43 uint32_t ifdr; 44 uint32_t i2cr; 45 uint32_t i2sr; 46 uint32_t i2dr; 47 }; 48 49 #define I2CR_IEN (1 << 7) 50 #define I2CR_IIEN (1 << 6) 51 #define I2CR_MSTA (1 << 5) 52 #define I2CR_MTX (1 << 4) 53 #define I2CR_TX_NO_AK (1 << 3) 54 #define I2CR_RSTA (1 << 2) 55 56 #define I2SR_ICF (1 << 7) 57 #define I2SR_IBB (1 << 5) 58 #define I2SR_IIF (1 << 1) 59 #define I2SR_RX_NO_AK (1 << 0) 60 61 #ifdef CONFIG_SYS_I2C_BASE 62 #define I2C_BASE CONFIG_SYS_I2C_BASE 63 #else 64 #error "define CONFIG_SYS_I2C_BASE to use the mxc_i2c driver" 65 #endif 66 67 static u16 i2c_clk_div[50][2] = { 68 { 22, 0x20 }, { 24, 0x21 }, { 26, 0x22 }, { 28, 0x23 }, 69 { 30, 0x00 }, { 32, 0x24 }, { 36, 0x25 }, { 40, 0x26 }, 70 { 42, 0x03 }, { 44, 0x27 }, { 48, 0x28 }, { 52, 0x05 }, 71 { 56, 0x29 }, { 60, 0x06 }, { 64, 0x2A }, { 72, 0x2B }, 72 { 80, 0x2C }, { 88, 0x09 }, { 96, 0x2D }, { 104, 0x0A }, 73 { 112, 0x2E }, { 128, 0x2F }, { 144, 0x0C }, { 160, 0x30 }, 74 { 192, 0x31 }, { 224, 0x32 }, { 240, 0x0F }, { 256, 0x33 }, 75 { 288, 0x10 }, { 320, 0x34 }, { 384, 0x35 }, { 448, 0x36 }, 76 { 480, 0x13 }, { 512, 0x37 }, { 576, 0x14 }, { 640, 0x38 }, 77 { 768, 0x39 }, { 896, 0x3A }, { 960, 0x17 }, { 1024, 0x3B }, 78 { 1152, 0x18 }, { 1280, 0x3C }, { 1536, 0x3D }, { 1792, 0x3E }, 79 { 1920, 0x1B }, { 2048, 0x3F }, { 2304, 0x1C }, { 2560, 0x1D }, 80 { 3072, 0x1E }, { 3840, 0x1F } 81 }; 82 83 /* 84 * Calculate and set proper clock divider 85 */ 86 static uint8_t i2c_imx_get_clk(unsigned int rate) 87 { 88 unsigned int i2c_clk_rate; 89 unsigned int div; 90 u8 clk_div; 91 92 #if defined(CONFIG_MX31) 93 struct clock_control_regs *sc_regs = 94 (struct clock_control_regs *)CCM_BASE; 95 96 /* start the required I2C clock */ 97 writel(readl(&sc_regs->cgr0) | (3 << CONFIG_SYS_I2C_CLK_OFFSET), 98 &sc_regs->cgr0); 99 #endif 100 101 /* Divider value calculation */ 102 i2c_clk_rate = mxc_get_clock(MXC_IPG_PERCLK); 103 div = (i2c_clk_rate + rate - 1) / rate; 104 if (div < i2c_clk_div[0][0]) 105 clk_div = 0; 106 else if (div > i2c_clk_div[ARRAY_SIZE(i2c_clk_div) - 1][0]) 107 clk_div = ARRAY_SIZE(i2c_clk_div) - 1; 108 else 109 for (clk_div = 0; i2c_clk_div[clk_div][0] < div; clk_div++) 110 ; 111 112 /* Store divider value */ 113 return clk_div; 114 } 115 116 /* 117 * Reset I2C Controller 118 */ 119 void i2c_reset(void) 120 { 121 struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE; 122 123 writeb(0, &i2c_regs->i2cr); /* Reset module */ 124 writeb(0, &i2c_regs->i2sr); 125 } 126 127 /* 128 * Init I2C Bus 129 */ 130 void i2c_init(int speed, int unused) 131 { 132 struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE; 133 u8 clk_idx = i2c_imx_get_clk(speed); 134 u8 idx = i2c_clk_div[clk_idx][1]; 135 136 /* Store divider value */ 137 writeb(idx, &i2c_regs->ifdr); 138 139 i2c_reset(); 140 } 141 142 /* 143 * Set I2C Speed 144 */ 145 int i2c_set_bus_speed(unsigned int speed) 146 { 147 i2c_init(speed, 0); 148 return 0; 149 } 150 151 /* 152 * Get I2C Speed 153 */ 154 unsigned int i2c_get_bus_speed(void) 155 { 156 struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE; 157 u8 clk_idx = readb(&i2c_regs->ifdr); 158 u8 clk_div; 159 160 for (clk_div = 0; i2c_clk_div[clk_div][1] != clk_idx; clk_div++) 161 ; 162 163 return mxc_get_clock(MXC_IPG_PERCLK) / i2c_clk_div[clk_div][0]; 164 } 165 166 #define ST_BUS_IDLE (0 | (I2SR_IBB << 8)) 167 #define ST_BUS_BUSY (I2SR_IBB | (I2SR_IBB << 8)) 168 #define ST_IIF (I2SR_IIF | (I2SR_IIF << 8)) 169 170 static int wait_for_sr_state(struct mxc_i2c_regs *i2c_regs, unsigned state) 171 { 172 unsigned sr; 173 ulong elapsed; 174 ulong start_time = get_timer(0); 175 for (;;) { 176 sr = readb(&i2c_regs->i2sr); 177 if ((sr & (state >> 8)) == (unsigned char)state) 178 return sr; 179 WATCHDOG_RESET(); 180 elapsed = get_timer(start_time); 181 if (elapsed > (CONFIG_SYS_HZ / 10)) /* .1 seconds */ 182 break; 183 } 184 printf("%s: failed sr=%x cr=%x state=%x\n", __func__, 185 sr, readb(&i2c_regs->i2cr), state); 186 return -ETIMEDOUT; 187 } 188 189 static int tx_byte(struct mxc_i2c_regs *i2c_regs, u8 byte) 190 { 191 int ret; 192 193 writeb(0, &i2c_regs->i2sr); 194 writeb(byte, &i2c_regs->i2dr); 195 ret = wait_for_sr_state(i2c_regs, ST_IIF); 196 if (ret < 0) 197 return ret; 198 if (ret & I2SR_RX_NO_AK) 199 return -ENODEV; 200 return 0; 201 } 202 203 /* 204 * Stop the controller 205 */ 206 void i2c_imx_stop(void) 207 { 208 int ret; 209 struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE; 210 unsigned int temp = 0; 211 212 /* Stop I2C transaction */ 213 temp = readb(&i2c_regs->i2cr); 214 temp &= ~(I2CR_MSTA | I2CR_MTX); 215 writeb(temp, &i2c_regs->i2cr); 216 217 ret = wait_for_sr_state(i2c_regs, ST_BUS_IDLE); 218 if (ret < 0) 219 printf("%s:trigger stop failed\n", __func__); 220 /* Disable I2C controller */ 221 writeb(0, &i2c_regs->i2cr); 222 } 223 224 /* 225 * Send start signal, chip address and 226 * write register address 227 */ 228 static int i2c_init_transfer(struct mxc_i2c_regs *i2c_regs, 229 uchar chip, uint addr, int alen) 230 { 231 unsigned int temp; 232 int ret; 233 234 /* Enable I2C controller */ 235 writeb(0, &i2c_regs->i2sr); 236 writeb(I2CR_IEN, &i2c_regs->i2cr); 237 238 /* Wait for controller to be stable */ 239 udelay(50); 240 241 /* Start I2C transaction */ 242 temp = readb(&i2c_regs->i2cr); 243 temp |= I2CR_MSTA; 244 writeb(temp, &i2c_regs->i2cr); 245 246 ret = wait_for_sr_state(i2c_regs, ST_BUS_BUSY); 247 if (ret < 0) 248 goto exit; 249 250 temp |= I2CR_MTX | I2CR_TX_NO_AK; 251 writeb(temp, &i2c_regs->i2cr); 252 253 /* write slave address */ 254 ret = tx_byte(i2c_regs, chip << 1); 255 if (ret < 0) 256 goto exit; 257 258 while (alen--) { 259 ret = tx_byte(i2c_regs, (addr >> (alen * 8)) & 0xff); 260 if (ret < 0) 261 goto exit; 262 } 263 return 0; 264 exit: 265 i2c_imx_stop(); 266 return ret; 267 } 268 269 /* 270 * Read data from I2C device 271 */ 272 int i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len) 273 { 274 struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE; 275 int ret; 276 unsigned int temp; 277 int i; 278 279 ret = i2c_init_transfer(i2c_regs, chip, addr, alen); 280 if (ret < 0) 281 return ret; 282 283 temp = readb(&i2c_regs->i2cr); 284 temp |= I2CR_RSTA; 285 writeb(temp, &i2c_regs->i2cr); 286 287 ret = tx_byte(i2c_regs, (chip << 1) | 1); 288 if (ret < 0) { 289 i2c_imx_stop(); 290 return ret; 291 } 292 293 /* setup bus to read data */ 294 temp = readb(&i2c_regs->i2cr); 295 temp &= ~(I2CR_MTX | I2CR_TX_NO_AK); 296 if (len == 1) 297 temp |= I2CR_TX_NO_AK; 298 writeb(temp, &i2c_regs->i2cr); 299 writeb(0, &i2c_regs->i2sr); 300 readb(&i2c_regs->i2dr); /* dummy read to clear ICF */ 301 302 /* read data */ 303 for (i = 0; i < len; i++) { 304 ret = wait_for_sr_state(i2c_regs, ST_IIF); 305 if (ret < 0) { 306 i2c_imx_stop(); 307 return ret; 308 } 309 310 /* 311 * It must generate STOP before read I2DR to prevent 312 * controller from generating another clock cycle 313 */ 314 if (i == (len - 1)) { 315 temp = readb(&i2c_regs->i2cr); 316 temp &= ~(I2CR_MSTA | I2CR_MTX); 317 writeb(temp, &i2c_regs->i2cr); 318 wait_for_sr_state(i2c_regs, ST_BUS_IDLE); 319 } else if (i == (len - 2)) { 320 temp = readb(&i2c_regs->i2cr); 321 temp |= I2CR_TX_NO_AK; 322 writeb(temp, &i2c_regs->i2cr); 323 } 324 writeb(0, &i2c_regs->i2sr); 325 buf[i] = readb(&i2c_regs->i2dr); 326 } 327 328 i2c_imx_stop(); 329 330 return 0; 331 } 332 333 /* 334 * Write data to I2C device 335 */ 336 int i2c_write(uchar chip, uint addr, int alen, uchar *buf, int len) 337 { 338 struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE; 339 int ret; 340 int i; 341 342 ret = i2c_init_transfer(i2c_regs, chip, addr, alen); 343 if (ret < 0) 344 return ret; 345 346 for (i = 0; i < len; i++) { 347 ret = tx_byte(i2c_regs, buf[i]); 348 if (ret < 0) 349 break; 350 } 351 352 i2c_imx_stop(); 353 354 return ret; 355 } 356 357 /* 358 * Test if a chip at a given address responds (probe the chip) 359 */ 360 int i2c_probe(uchar chip) 361 { 362 return i2c_write(chip, 0, 0, NULL, 0); 363 } 364