1 /* 2 * i2c driver for Freescale i.MX series 3 * 4 * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> 5 * (c) 2011 Marek Vasut <marek.vasut@gmail.com> 6 * 7 * Based on i2c-imx.c from linux kernel: 8 * Copyright (C) 2005 Torsten Koschorrek <koschorrek at synertronixx.de> 9 * Copyright (C) 2005 Matthias Blaschke <blaschke at synertronixx.de> 10 * Copyright (C) 2007 RightHand Technologies, Inc. 11 * Copyright (C) 2008 Darius Augulis <darius.augulis at teltonika.lt> 12 * 13 * 14 * See file CREDITS for list of people who contributed to this 15 * project. 16 * 17 * This program is free software; you can redistribute it and/or 18 * modify it under the terms of the GNU General Public License as 19 * published by the Free Software Foundation; either version 2 of 20 * the License, or (at your option) any later version. 21 * 22 * This program is distributed in the hope that it will be useful, 23 * but WITHOUT ANY WARRANTY; without even the implied warranty of 24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 25 * GNU General Public License for more details. 26 * 27 * You should have received a copy of the GNU General Public License 28 * along with this program; if not, write to the Free Software 29 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 30 * MA 02111-1307 USA 31 */ 32 33 #include <common.h> 34 #include <asm/arch/clock.h> 35 #include <asm/arch/imx-regs.h> 36 #include <asm/io.h> 37 #include <i2c.h> 38 39 struct mxc_i2c_regs { 40 uint32_t iadr; 41 uint32_t ifdr; 42 uint32_t i2cr; 43 uint32_t i2sr; 44 uint32_t i2dr; 45 }; 46 47 #define I2CR_IEN (1 << 7) 48 #define I2CR_IIEN (1 << 6) 49 #define I2CR_MSTA (1 << 5) 50 #define I2CR_MTX (1 << 4) 51 #define I2CR_TX_NO_AK (1 << 3) 52 #define I2CR_RSTA (1 << 2) 53 54 #define I2SR_ICF (1 << 7) 55 #define I2SR_IBB (1 << 5) 56 #define I2SR_IIF (1 << 1) 57 #define I2SR_RX_NO_AK (1 << 0) 58 59 #ifdef CONFIG_SYS_I2C_BASE 60 #define I2C_BASE CONFIG_SYS_I2C_BASE 61 #else 62 #error "define CONFIG_SYS_I2C_BASE to use the mxc_i2c driver" 63 #endif 64 65 #define I2C_MAX_TIMEOUT 10000 66 67 static u16 i2c_clk_div[50][2] = { 68 { 22, 0x20 }, { 24, 0x21 }, { 26, 0x22 }, { 28, 0x23 }, 69 { 30, 0x00 }, { 32, 0x24 }, { 36, 0x25 }, { 40, 0x26 }, 70 { 42, 0x03 }, { 44, 0x27 }, { 48, 0x28 }, { 52, 0x05 }, 71 { 56, 0x29 }, { 60, 0x06 }, { 64, 0x2A }, { 72, 0x2B }, 72 { 80, 0x2C }, { 88, 0x09 }, { 96, 0x2D }, { 104, 0x0A }, 73 { 112, 0x2E }, { 128, 0x2F }, { 144, 0x0C }, { 160, 0x30 }, 74 { 192, 0x31 }, { 224, 0x32 }, { 240, 0x0F }, { 256, 0x33 }, 75 { 288, 0x10 }, { 320, 0x34 }, { 384, 0x35 }, { 448, 0x36 }, 76 { 480, 0x13 }, { 512, 0x37 }, { 576, 0x14 }, { 640, 0x38 }, 77 { 768, 0x39 }, { 896, 0x3A }, { 960, 0x17 }, { 1024, 0x3B }, 78 { 1152, 0x18 }, { 1280, 0x3C }, { 1536, 0x3D }, { 1792, 0x3E }, 79 { 1920, 0x1B }, { 2048, 0x3F }, { 2304, 0x1C }, { 2560, 0x1D }, 80 { 3072, 0x1E }, { 3840, 0x1F } 81 }; 82 83 /* 84 * Calculate and set proper clock divider 85 */ 86 static uint8_t i2c_imx_get_clk(unsigned int rate) 87 { 88 unsigned int i2c_clk_rate; 89 unsigned int div; 90 u8 clk_div; 91 92 #if defined(CONFIG_MX31) 93 struct clock_control_regs *sc_regs = 94 (struct clock_control_regs *)CCM_BASE; 95 96 /* start the required I2C clock */ 97 writel(readl(&sc_regs->cgr0) | (3 << CONFIG_SYS_I2C_CLK_OFFSET), 98 &sc_regs->cgr0); 99 #endif 100 101 /* Divider value calculation */ 102 i2c_clk_rate = mxc_get_clock(MXC_IPG_PERCLK); 103 div = (i2c_clk_rate + rate - 1) / rate; 104 if (div < i2c_clk_div[0][0]) 105 clk_div = 0; 106 else if (div > i2c_clk_div[ARRAY_SIZE(i2c_clk_div) - 1][0]) 107 clk_div = ARRAY_SIZE(i2c_clk_div) - 1; 108 else 109 for (clk_div = 0; i2c_clk_div[clk_div][0] < div; clk_div++) 110 ; 111 112 /* Store divider value */ 113 return clk_div; 114 } 115 116 /* 117 * Reset I2C Controller 118 */ 119 void i2c_reset(void) 120 { 121 struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE; 122 123 writeb(0, &i2c_regs->i2cr); /* Reset module */ 124 writeb(0, &i2c_regs->i2sr); 125 } 126 127 /* 128 * Init I2C Bus 129 */ 130 void i2c_init(int speed, int unused) 131 { 132 struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE; 133 u8 clk_idx = i2c_imx_get_clk(speed); 134 u8 idx = i2c_clk_div[clk_idx][1]; 135 136 /* Store divider value */ 137 writeb(idx, &i2c_regs->ifdr); 138 139 i2c_reset(); 140 } 141 142 /* 143 * Set I2C Speed 144 */ 145 int i2c_set_bus_speed(unsigned int speed) 146 { 147 i2c_init(speed, 0); 148 return 0; 149 } 150 151 /* 152 * Get I2C Speed 153 */ 154 unsigned int i2c_get_bus_speed(void) 155 { 156 struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE; 157 u8 clk_idx = readb(&i2c_regs->ifdr); 158 u8 clk_div; 159 160 for (clk_div = 0; i2c_clk_div[clk_div][1] != clk_idx; clk_div++) 161 ; 162 163 return mxc_get_clock(MXC_IPG_PERCLK) / i2c_clk_div[clk_div][0]; 164 } 165 166 /* 167 * Wait for bus to be busy (or free if for_busy = 0) 168 * 169 * for_busy = 1: Wait for IBB to be asserted 170 * for_busy = 0: Wait for IBB to be de-asserted 171 */ 172 int i2c_imx_bus_busy(int for_busy) 173 { 174 struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE; 175 unsigned int temp; 176 177 int timeout = I2C_MAX_TIMEOUT; 178 179 while (timeout--) { 180 temp = readb(&i2c_regs->i2sr); 181 182 if (for_busy && (temp & I2SR_IBB)) 183 return 0; 184 if (!for_busy && !(temp & I2SR_IBB)) 185 return 0; 186 187 udelay(1); 188 } 189 190 return 1; 191 } 192 193 /* 194 * Wait for transaction to complete 195 */ 196 int i2c_imx_trx_complete(void) 197 { 198 struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE; 199 int timeout = I2C_MAX_TIMEOUT; 200 201 while (timeout--) { 202 if (readb(&i2c_regs->i2sr) & I2SR_IIF) { 203 writeb(0, &i2c_regs->i2sr); 204 return 0; 205 } 206 207 udelay(1); 208 } 209 210 return 1; 211 } 212 213 /* 214 * Check if the transaction was ACKed 215 */ 216 int i2c_imx_acked(void) 217 { 218 struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE; 219 220 return readb(&i2c_regs->i2sr) & I2SR_RX_NO_AK; 221 } 222 223 /* 224 * Start the controller 225 */ 226 int i2c_imx_start(void) 227 { 228 struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE; 229 unsigned int temp = 0; 230 int result; 231 232 /* Enable I2C controller */ 233 writeb(0, &i2c_regs->i2sr); 234 writeb(I2CR_IEN, &i2c_regs->i2cr); 235 236 /* Wait controller to be stable */ 237 udelay(50); 238 239 /* Start I2C transaction */ 240 temp = readb(&i2c_regs->i2cr); 241 temp |= I2CR_MSTA; 242 writeb(temp, &i2c_regs->i2cr); 243 244 result = i2c_imx_bus_busy(1); 245 if (result) 246 return result; 247 248 temp |= I2CR_MTX | I2CR_TX_NO_AK; 249 writeb(temp, &i2c_regs->i2cr); 250 251 return 0; 252 } 253 254 /* 255 * Stop the controller 256 */ 257 void i2c_imx_stop(void) 258 { 259 struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE; 260 unsigned int temp = 0; 261 262 /* Stop I2C transaction */ 263 temp = readb(&i2c_regs->i2cr); 264 temp &= ~(I2CR_MSTA | I2CR_MTX); 265 writeb(temp, &i2c_regs->i2cr); 266 267 i2c_imx_bus_busy(0); 268 269 /* Disable I2C controller */ 270 writeb(0, &i2c_regs->i2cr); 271 } 272 273 /* 274 * Set chip address and access mode 275 * 276 * read = 1: READ access 277 * read = 0: WRITE access 278 */ 279 int i2c_imx_set_chip_addr(uchar chip, int read) 280 { 281 struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE; 282 int ret; 283 284 writeb((chip << 1) | read, &i2c_regs->i2dr); 285 286 ret = i2c_imx_trx_complete(); 287 if (ret) 288 return ret; 289 290 ret = i2c_imx_acked(); 291 if (ret) 292 return ret; 293 294 return ret; 295 } 296 297 /* 298 * Write register address 299 */ 300 int i2c_imx_set_reg_addr(uint addr, int alen) 301 { 302 struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE; 303 int ret = 0; 304 305 while (alen--) { 306 writeb((addr >> (alen * 8)) & 0xff, &i2c_regs->i2dr); 307 308 ret = i2c_imx_trx_complete(); 309 if (ret) 310 break; 311 312 ret = i2c_imx_acked(); 313 if (ret) 314 break; 315 } 316 317 return ret; 318 } 319 320 /* 321 * Try if a chip add given address responds (probe the chip) 322 */ 323 int i2c_probe(uchar chip) 324 { 325 int ret; 326 327 ret = i2c_imx_start(); 328 if (ret) 329 return ret; 330 331 ret = i2c_imx_set_chip_addr(chip, 0); 332 if (ret) 333 return ret; 334 335 i2c_imx_stop(); 336 337 return ret; 338 } 339 340 /* 341 * Read data from I2C device 342 */ 343 int i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len) 344 { 345 struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE; 346 int ret; 347 unsigned int temp; 348 int i; 349 350 ret = i2c_imx_start(); 351 if (ret) 352 return ret; 353 354 /* write slave address */ 355 ret = i2c_imx_set_chip_addr(chip, 0); 356 if (ret) 357 return ret; 358 359 ret = i2c_imx_set_reg_addr(addr, alen); 360 if (ret) 361 return ret; 362 363 temp = readb(&i2c_regs->i2cr); 364 temp |= I2CR_RSTA; 365 writeb(temp, &i2c_regs->i2cr); 366 367 ret = i2c_imx_set_chip_addr(chip, 1); 368 if (ret) 369 return ret; 370 371 /* setup bus to read data */ 372 temp = readb(&i2c_regs->i2cr); 373 temp &= ~(I2CR_MTX | I2CR_TX_NO_AK); 374 if (len == 1) 375 temp |= I2CR_TX_NO_AK; 376 writeb(temp, &i2c_regs->i2cr); 377 readb(&i2c_regs->i2dr); 378 379 /* read data */ 380 for (i = 0; i < len; i++) { 381 ret = i2c_imx_trx_complete(); 382 if (ret) 383 return ret; 384 385 /* 386 * It must generate STOP before read I2DR to prevent 387 * controller from generating another clock cycle 388 */ 389 if (i == (len - 1)) { 390 temp = readb(&i2c_regs->i2cr); 391 temp &= ~(I2CR_MSTA | I2CR_MTX); 392 writeb(temp, &i2c_regs->i2cr); 393 i2c_imx_bus_busy(0); 394 } else if (i == (len - 2)) { 395 temp = readb(&i2c_regs->i2cr); 396 temp |= I2CR_TX_NO_AK; 397 writeb(temp, &i2c_regs->i2cr); 398 } 399 400 buf[i] = readb(&i2c_regs->i2dr); 401 } 402 403 i2c_imx_stop(); 404 405 return ret; 406 } 407 408 /* 409 * Write data to I2C device 410 */ 411 int i2c_write(uchar chip, uint addr, int alen, uchar *buf, int len) 412 { 413 struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE; 414 int ret; 415 int i; 416 417 ret = i2c_imx_start(); 418 if (ret) 419 return ret; 420 421 /* write slave address */ 422 ret = i2c_imx_set_chip_addr(chip, 0); 423 if (ret) 424 return ret; 425 426 ret = i2c_imx_set_reg_addr(addr, alen); 427 if (ret) 428 return ret; 429 430 for (i = 0; i < len; i++) { 431 writeb(buf[i], &i2c_regs->i2dr); 432 433 ret = i2c_imx_trx_complete(); 434 if (ret) 435 return ret; 436 437 ret = i2c_imx_acked(); 438 if (ret) 439 return ret; 440 } 441 442 i2c_imx_stop(); 443 444 return ret; 445 } 446