1 /* 2 * i2c driver for Freescale i.MX series 3 * 4 * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> 5 * (c) 2011 Marek Vasut <marek.vasut@gmail.com> 6 * 7 * Based on i2c-imx.c from linux kernel: 8 * Copyright (C) 2005 Torsten Koschorrek <koschorrek at synertronixx.de> 9 * Copyright (C) 2005 Matthias Blaschke <blaschke at synertronixx.de> 10 * Copyright (C) 2007 RightHand Technologies, Inc. 11 * Copyright (C) 2008 Darius Augulis <darius.augulis at teltonika.lt> 12 * 13 * 14 * SPDX-License-Identifier: GPL-2.0+ 15 */ 16 17 #include <common.h> 18 #include <asm/arch/clock.h> 19 #include <asm/arch/imx-regs.h> 20 #include <asm/errno.h> 21 #include <asm/imx-common/mxc_i2c.h> 22 #include <asm/io.h> 23 #include <i2c.h> 24 #include <watchdog.h> 25 #include <dm.h> 26 #include <fdtdec.h> 27 28 DECLARE_GLOBAL_DATA_PTR; 29 30 #define I2C_QUIRK_FLAG (1 << 0) 31 32 #define IMX_I2C_REGSHIFT 2 33 #define VF610_I2C_REGSHIFT 0 34 /* Register index */ 35 #define IADR 0 36 #define IFDR 1 37 #define I2CR 2 38 #define I2SR 3 39 #define I2DR 4 40 41 #define I2CR_IIEN (1 << 6) 42 #define I2CR_MSTA (1 << 5) 43 #define I2CR_MTX (1 << 4) 44 #define I2CR_TX_NO_AK (1 << 3) 45 #define I2CR_RSTA (1 << 2) 46 47 #define I2SR_ICF (1 << 7) 48 #define I2SR_IBB (1 << 5) 49 #define I2SR_IAL (1 << 4) 50 #define I2SR_IIF (1 << 1) 51 #define I2SR_RX_NO_AK (1 << 0) 52 53 #ifdef I2C_QUIRK_REG 54 #define I2CR_IEN (0 << 7) 55 #define I2CR_IDIS (1 << 7) 56 #define I2SR_IIF_CLEAR (1 << 1) 57 #else 58 #define I2CR_IEN (1 << 7) 59 #define I2CR_IDIS (0 << 7) 60 #define I2SR_IIF_CLEAR (0 << 1) 61 #endif 62 63 #if defined(CONFIG_HARD_I2C) && !defined(CONFIG_SYS_I2C_BASE) 64 #error "define CONFIG_SYS_I2C_BASE to use the mxc_i2c driver" 65 #endif 66 67 #ifdef I2C_QUIRK_REG 68 static u16 i2c_clk_div[60][2] = { 69 { 20, 0x00 }, { 22, 0x01 }, { 24, 0x02 }, { 26, 0x03 }, 70 { 28, 0x04 }, { 30, 0x05 }, { 32, 0x09 }, { 34, 0x06 }, 71 { 36, 0x0A }, { 40, 0x07 }, { 44, 0x0C }, { 48, 0x0D }, 72 { 52, 0x43 }, { 56, 0x0E }, { 60, 0x45 }, { 64, 0x12 }, 73 { 68, 0x0F }, { 72, 0x13 }, { 80, 0x14 }, { 88, 0x15 }, 74 { 96, 0x19 }, { 104, 0x16 }, { 112, 0x1A }, { 128, 0x17 }, 75 { 136, 0x4F }, { 144, 0x1C }, { 160, 0x1D }, { 176, 0x55 }, 76 { 192, 0x1E }, { 208, 0x56 }, { 224, 0x22 }, { 228, 0x24 }, 77 { 240, 0x1F }, { 256, 0x23 }, { 288, 0x5C }, { 320, 0x25 }, 78 { 384, 0x26 }, { 448, 0x2A }, { 480, 0x27 }, { 512, 0x2B }, 79 { 576, 0x2C }, { 640, 0x2D }, { 768, 0x31 }, { 896, 0x32 }, 80 { 960, 0x2F }, { 1024, 0x33 }, { 1152, 0x34 }, { 1280, 0x35 }, 81 { 1536, 0x36 }, { 1792, 0x3A }, { 1920, 0x37 }, { 2048, 0x3B }, 82 { 2304, 0x3C }, { 2560, 0x3D }, { 3072, 0x3E }, { 3584, 0x7A }, 83 { 3840, 0x3F }, { 4096, 0x7B }, { 5120, 0x7D }, { 6144, 0x7E }, 84 }; 85 #else 86 static u16 i2c_clk_div[50][2] = { 87 { 22, 0x20 }, { 24, 0x21 }, { 26, 0x22 }, { 28, 0x23 }, 88 { 30, 0x00 }, { 32, 0x24 }, { 36, 0x25 }, { 40, 0x26 }, 89 { 42, 0x03 }, { 44, 0x27 }, { 48, 0x28 }, { 52, 0x05 }, 90 { 56, 0x29 }, { 60, 0x06 }, { 64, 0x2A }, { 72, 0x2B }, 91 { 80, 0x2C }, { 88, 0x09 }, { 96, 0x2D }, { 104, 0x0A }, 92 { 112, 0x2E }, { 128, 0x2F }, { 144, 0x0C }, { 160, 0x30 }, 93 { 192, 0x31 }, { 224, 0x32 }, { 240, 0x0F }, { 256, 0x33 }, 94 { 288, 0x10 }, { 320, 0x34 }, { 384, 0x35 }, { 448, 0x36 }, 95 { 480, 0x13 }, { 512, 0x37 }, { 576, 0x14 }, { 640, 0x38 }, 96 { 768, 0x39 }, { 896, 0x3A }, { 960, 0x17 }, { 1024, 0x3B }, 97 { 1152, 0x18 }, { 1280, 0x3C }, { 1536, 0x3D }, { 1792, 0x3E }, 98 { 1920, 0x1B }, { 2048, 0x3F }, { 2304, 0x1C }, { 2560, 0x1D }, 99 { 3072, 0x1E }, { 3840, 0x1F } 100 }; 101 #endif 102 103 #ifndef CONFIG_SYS_MXC_I2C1_SPEED 104 #define CONFIG_SYS_MXC_I2C1_SPEED 100000 105 #endif 106 #ifndef CONFIG_SYS_MXC_I2C2_SPEED 107 #define CONFIG_SYS_MXC_I2C2_SPEED 100000 108 #endif 109 #ifndef CONFIG_SYS_MXC_I2C3_SPEED 110 #define CONFIG_SYS_MXC_I2C3_SPEED 100000 111 #endif 112 #ifndef CONFIG_SYS_MXC_I2C4_SPEED 113 #define CONFIG_SYS_MXC_I2C4_SPEED 100000 114 #endif 115 116 #ifndef CONFIG_SYS_MXC_I2C1_SLAVE 117 #define CONFIG_SYS_MXC_I2C1_SLAVE 0 118 #endif 119 #ifndef CONFIG_SYS_MXC_I2C2_SLAVE 120 #define CONFIG_SYS_MXC_I2C2_SLAVE 0 121 #endif 122 #ifndef CONFIG_SYS_MXC_I2C3_SLAVE 123 #define CONFIG_SYS_MXC_I2C3_SLAVE 0 124 #endif 125 #ifndef CONFIG_SYS_MXC_I2C4_SLAVE 126 #define CONFIG_SYS_MXC_I2C4_SLAVE 0 127 #endif 128 129 /* 130 * Calculate and set proper clock divider 131 */ 132 static uint8_t i2c_imx_get_clk(struct mxc_i2c_bus *i2c_bus, unsigned int rate) 133 { 134 unsigned int i2c_clk_rate; 135 unsigned int div; 136 u8 clk_div; 137 138 #if defined(CONFIG_MX31) 139 struct clock_control_regs *sc_regs = 140 (struct clock_control_regs *)CCM_BASE; 141 142 /* start the required I2C clock */ 143 writel(readl(&sc_regs->cgr0) | (3 << CONFIG_SYS_I2C_CLK_OFFSET), 144 &sc_regs->cgr0); 145 #endif 146 147 /* Divider value calculation */ 148 i2c_clk_rate = mxc_get_clock(MXC_I2C_CLK); 149 div = (i2c_clk_rate + rate - 1) / rate; 150 if (div < i2c_clk_div[0][0]) 151 clk_div = 0; 152 else if (div > i2c_clk_div[ARRAY_SIZE(i2c_clk_div) - 1][0]) 153 clk_div = ARRAY_SIZE(i2c_clk_div) - 1; 154 else 155 for (clk_div = 0; i2c_clk_div[clk_div][0] < div; clk_div++) 156 ; 157 158 /* Store divider value */ 159 return clk_div; 160 } 161 162 /* 163 * Set I2C Bus speed 164 */ 165 static int bus_i2c_set_bus_speed(struct mxc_i2c_bus *i2c_bus, int speed) 166 { 167 ulong base = i2c_bus->base; 168 bool quirk = i2c_bus->driver_data & I2C_QUIRK_FLAG ? true : false; 169 u8 clk_idx = i2c_imx_get_clk(i2c_bus, speed); 170 u8 idx = i2c_clk_div[clk_idx][1]; 171 int reg_shift = quirk ? VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT; 172 173 /* Store divider value */ 174 writeb(idx, base + (IFDR << reg_shift)); 175 176 /* Reset module */ 177 writeb(I2CR_IDIS, base + (I2CR << reg_shift)); 178 writeb(0, base + (I2SR << reg_shift)); 179 return 0; 180 } 181 182 #define ST_BUS_IDLE (0 | (I2SR_IBB << 8)) 183 #define ST_BUS_BUSY (I2SR_IBB | (I2SR_IBB << 8)) 184 #define ST_IIF (I2SR_IIF | (I2SR_IIF << 8)) 185 186 static int wait_for_sr_state(struct mxc_i2c_bus *i2c_bus, unsigned state) 187 { 188 unsigned sr; 189 ulong elapsed; 190 bool quirk = i2c_bus->driver_data & I2C_QUIRK_FLAG ? true : false; 191 int reg_shift = quirk ? VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT; 192 ulong base = i2c_bus->base; 193 ulong start_time = get_timer(0); 194 for (;;) { 195 sr = readb(base + (I2SR << reg_shift)); 196 if (sr & I2SR_IAL) { 197 if (quirk) 198 writeb(sr | I2SR_IAL, base + 199 (I2SR << reg_shift)); 200 else 201 writeb(sr & ~I2SR_IAL, base + 202 (I2SR << reg_shift)); 203 printf("%s: Arbitration lost sr=%x cr=%x state=%x\n", 204 __func__, sr, readb(base + (I2CR << reg_shift)), 205 state); 206 return -ERESTART; 207 } 208 if ((sr & (state >> 8)) == (unsigned char)state) 209 return sr; 210 WATCHDOG_RESET(); 211 elapsed = get_timer(start_time); 212 if (elapsed > (CONFIG_SYS_HZ / 10)) /* .1 seconds */ 213 break; 214 } 215 printf("%s: failed sr=%x cr=%x state=%x\n", __func__, 216 sr, readb(base + (I2CR << reg_shift)), state); 217 return -ETIMEDOUT; 218 } 219 220 static int tx_byte(struct mxc_i2c_bus *i2c_bus, u8 byte) 221 { 222 int ret; 223 int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ? 224 VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT; 225 ulong base = i2c_bus->base; 226 227 writeb(I2SR_IIF_CLEAR, base + (I2SR << reg_shift)); 228 writeb(byte, base + (I2DR << reg_shift)); 229 230 ret = wait_for_sr_state(i2c_bus, ST_IIF); 231 if (ret < 0) 232 return ret; 233 if (ret & I2SR_RX_NO_AK) 234 return -ENODEV; 235 return 0; 236 } 237 238 /* 239 * Stub implementations for outer i2c slave operations. 240 */ 241 void __i2c_force_reset_slave(void) 242 { 243 } 244 void i2c_force_reset_slave(void) 245 __attribute__((weak, alias("__i2c_force_reset_slave"))); 246 247 /* 248 * Stop I2C transaction 249 */ 250 static void i2c_imx_stop(struct mxc_i2c_bus *i2c_bus) 251 { 252 int ret; 253 int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ? 254 VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT; 255 ulong base = i2c_bus->base; 256 unsigned int temp = readb(base + (I2CR << reg_shift)); 257 258 temp &= ~(I2CR_MSTA | I2CR_MTX); 259 writeb(temp, base + (I2CR << reg_shift)); 260 ret = wait_for_sr_state(i2c_bus, ST_BUS_IDLE); 261 if (ret < 0) 262 printf("%s:trigger stop failed\n", __func__); 263 } 264 265 /* 266 * Send start signal, chip address and 267 * write register address 268 */ 269 static int i2c_init_transfer_(struct mxc_i2c_bus *i2c_bus, u8 chip, 270 u32 addr, int alen) 271 { 272 unsigned int temp; 273 int ret; 274 bool quirk = i2c_bus->driver_data & I2C_QUIRK_FLAG ? true : false; 275 ulong base = i2c_bus->base; 276 int reg_shift = quirk ? VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT; 277 278 /* Reset i2c slave */ 279 i2c_force_reset_slave(); 280 281 /* Enable I2C controller */ 282 if (quirk) 283 ret = readb(base + (I2CR << reg_shift)) & I2CR_IDIS; 284 else 285 ret = !(readb(base + (I2CR << reg_shift)) & I2CR_IEN); 286 287 if (ret) { 288 writeb(I2CR_IEN, base + (I2CR << reg_shift)); 289 /* Wait for controller to be stable */ 290 udelay(50); 291 } 292 293 if (readb(base + (IADR << reg_shift)) == (chip << 1)) 294 writeb((chip << 1) ^ 2, base + (IADR << reg_shift)); 295 writeb(I2SR_IIF_CLEAR, base + (I2SR << reg_shift)); 296 ret = wait_for_sr_state(i2c_bus, ST_BUS_IDLE); 297 if (ret < 0) 298 return ret; 299 300 /* Start I2C transaction */ 301 temp = readb(base + (I2CR << reg_shift)); 302 temp |= I2CR_MSTA; 303 writeb(temp, base + (I2CR << reg_shift)); 304 305 ret = wait_for_sr_state(i2c_bus, ST_BUS_BUSY); 306 if (ret < 0) 307 return ret; 308 309 temp |= I2CR_MTX | I2CR_TX_NO_AK; 310 writeb(temp, base + (I2CR << reg_shift)); 311 312 /* write slave address */ 313 ret = tx_byte(i2c_bus, chip << 1); 314 if (ret < 0) 315 return ret; 316 317 while (alen--) { 318 ret = tx_byte(i2c_bus, (addr >> (alen * 8)) & 0xff); 319 if (ret < 0) 320 return ret; 321 } 322 return 0; 323 } 324 325 #ifndef CONFIG_DM_I2C 326 int i2c_idle_bus(struct mxc_i2c_bus *i2c_bus) 327 { 328 if (i2c_bus && i2c_bus->idle_bus_fn) 329 return i2c_bus->idle_bus_fn(i2c_bus->idle_bus_data); 330 return 0; 331 } 332 #else 333 /* 334 * Since pinmux is not supported, implement a weak function here. 335 * You can implement your i2c_bus_idle in board file. When pinctrl 336 * is supported, this can be removed. 337 */ 338 int __i2c_idle_bus(struct mxc_i2c_bus *i2c_bus) 339 { 340 return 0; 341 } 342 343 int i2c_idle_bus(struct mxc_i2c_bus *i2c_bus) 344 __attribute__((weak, alias("__i2c_idle_bus"))); 345 #endif 346 347 static int i2c_init_transfer(struct mxc_i2c_bus *i2c_bus, u8 chip, 348 u32 addr, int alen) 349 { 350 int retry; 351 int ret; 352 int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ? 353 VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT; 354 for (retry = 0; retry < 3; retry++) { 355 ret = i2c_init_transfer_(i2c_bus, chip, addr, alen); 356 if (ret >= 0) 357 return 0; 358 i2c_imx_stop(i2c_bus); 359 if (ret == -ENODEV) 360 return ret; 361 362 printf("%s: failed for chip 0x%x retry=%d\n", __func__, chip, 363 retry); 364 if (ret != -ERESTART) 365 /* Disable controller */ 366 writeb(I2CR_IDIS, i2c_bus->base + (I2CR << reg_shift)); 367 udelay(100); 368 if (i2c_idle_bus(i2c_bus) < 0) 369 break; 370 } 371 printf("%s: give up i2c_regs=0x%lx\n", __func__, i2c_bus->base); 372 return ret; 373 } 374 375 376 static int i2c_write_data(struct mxc_i2c_bus *i2c_bus, u8 chip, const u8 *buf, 377 int len) 378 { 379 int i, ret = 0; 380 381 debug("i2c_write_data: chip=0x%x, len=0x%x\n", chip, len); 382 debug("write_data: "); 383 /* use rc for counter */ 384 for (i = 0; i < len; ++i) 385 debug(" 0x%02x", buf[i]); 386 debug("\n"); 387 388 for (i = 0; i < len; i++) { 389 ret = tx_byte(i2c_bus, buf[i]); 390 if (ret < 0) { 391 debug("i2c_write_data(): rc=%d\n", ret); 392 break; 393 } 394 } 395 396 return ret; 397 } 398 399 static int i2c_read_data(struct mxc_i2c_bus *i2c_bus, uchar chip, uchar *buf, 400 int len) 401 { 402 int ret; 403 unsigned int temp; 404 int i; 405 int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ? 406 VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT; 407 ulong base = i2c_bus->base; 408 409 debug("i2c_read_data: chip=0x%x, len=0x%x\n", chip, len); 410 411 /* setup bus to read data */ 412 temp = readb(base + (I2CR << reg_shift)); 413 temp &= ~(I2CR_MTX | I2CR_TX_NO_AK); 414 if (len == 1) 415 temp |= I2CR_TX_NO_AK; 416 writeb(temp, base + (I2CR << reg_shift)); 417 writeb(I2SR_IIF_CLEAR, base + (I2SR << reg_shift)); 418 /* dummy read to clear ICF */ 419 readb(base + (I2DR << reg_shift)); 420 421 /* read data */ 422 for (i = 0; i < len; i++) { 423 ret = wait_for_sr_state(i2c_bus, ST_IIF); 424 if (ret < 0) { 425 debug("i2c_read_data(): ret=%d\n", ret); 426 i2c_imx_stop(i2c_bus); 427 return ret; 428 } 429 430 /* 431 * It must generate STOP before read I2DR to prevent 432 * controller from generating another clock cycle 433 */ 434 if (i == (len - 1)) { 435 i2c_imx_stop(i2c_bus); 436 } else if (i == (len - 2)) { 437 temp = readb(base + (I2CR << reg_shift)); 438 temp |= I2CR_TX_NO_AK; 439 writeb(temp, base + (I2CR << reg_shift)); 440 } 441 writeb(I2SR_IIF_CLEAR, base + (I2SR << reg_shift)); 442 buf[i] = readb(base + (I2DR << reg_shift)); 443 } 444 445 /* reuse ret for counter*/ 446 for (ret = 0; ret < len; ++ret) 447 debug(" 0x%02x", buf[ret]); 448 debug("\n"); 449 450 i2c_imx_stop(i2c_bus); 451 return 0; 452 } 453 454 #ifndef CONFIG_DM_I2C 455 /* 456 * Read data from I2C device 457 */ 458 static int bus_i2c_read(struct mxc_i2c_bus *i2c_bus, u8 chip, u32 addr, 459 int alen, u8 *buf, int len) 460 { 461 int ret = 0; 462 u32 temp; 463 int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ? 464 VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT; 465 ulong base = i2c_bus->base; 466 467 ret = i2c_init_transfer(i2c_bus, chip, addr, alen); 468 if (ret < 0) 469 return ret; 470 471 temp = readb(base + (I2CR << reg_shift)); 472 temp |= I2CR_RSTA; 473 writeb(temp, base + (I2CR << reg_shift)); 474 475 ret = tx_byte(i2c_bus, (chip << 1) | 1); 476 if (ret < 0) { 477 i2c_imx_stop(i2c_bus); 478 return ret; 479 } 480 481 ret = i2c_read_data(i2c_bus, chip, buf, len); 482 483 i2c_imx_stop(i2c_bus); 484 return ret; 485 } 486 487 /* 488 * Write data to I2C device 489 */ 490 static int bus_i2c_write(struct mxc_i2c_bus *i2c_bus, u8 chip, u32 addr, 491 int alen, const u8 *buf, int len) 492 { 493 int ret = 0; 494 495 ret = i2c_init_transfer(i2c_bus, chip, addr, alen); 496 if (ret < 0) 497 return ret; 498 499 ret = i2c_write_data(i2c_bus, chip, buf, len); 500 501 i2c_imx_stop(i2c_bus); 502 503 return ret; 504 } 505 506 static struct mxc_i2c_bus mxc_i2c_buses[] = { 507 #if defined(CONFIG_MX25) 508 { 0, IMX_I2C_BASE }, 509 { 1, IMX_I2C2_BASE }, 510 { 2, IMX_I2C3_BASE }, 511 #elif defined(CONFIG_MX27) 512 { 0, IMX_I2C1_BASE }, 513 { 1, IMX_I2C2_BASE }, 514 #elif defined(CONFIG_MX31) || defined(CONFIG_MX35) || \ 515 defined(CONFIG_MX51) || defined(CONFIG_MX53) || \ 516 defined(CONFIG_MX6) 517 { 0, I2C1_BASE_ADDR }, 518 { 1, I2C2_BASE_ADDR }, 519 { 2, I2C3_BASE_ADDR }, 520 #if defined(CONFIG_MX6DL) 521 { 3, I2C4_BASE_ADDR }, 522 #endif 523 #elif defined(CONFIG_LS102XA) 524 { 0, I2C1_BASE_ADDR, I2C_QUIRK_FLAG }, 525 { 1, I2C2_BASE_ADDR, I2C_QUIRK_FLAG }, 526 { 2, I2C3_BASE_ADDR, I2C_QUIRK_FLAG }, 527 #elif defined(CONFIG_VF610) 528 { 0, I2C0_BASE_ADDR, I2C_QUIRK_FLAG }, 529 #elif defined(CONFIG_FSL_LSCH3) 530 { 0, I2C1_BASE_ADDR, I2C_QUIRK_FLAG }, 531 { 1, I2C2_BASE_ADDR, I2C_QUIRK_FLAG }, 532 { 2, I2C3_BASE_ADDR, I2C_QUIRK_FLAG }, 533 { 3, I2C4_BASE_ADDR, I2C_QUIRK_FLAG }, 534 #else 535 #error "architecture not supported" 536 #endif 537 { } 538 }; 539 540 struct mxc_i2c_bus *i2c_get_base(struct i2c_adapter *adap) 541 { 542 return &mxc_i2c_buses[adap->hwadapnr]; 543 } 544 545 static int mxc_i2c_read(struct i2c_adapter *adap, uint8_t chip, 546 uint addr, int alen, uint8_t *buffer, 547 int len) 548 { 549 return bus_i2c_read(i2c_get_base(adap), chip, addr, alen, buffer, len); 550 } 551 552 static int mxc_i2c_write(struct i2c_adapter *adap, uint8_t chip, 553 uint addr, int alen, uint8_t *buffer, 554 int len) 555 { 556 return bus_i2c_write(i2c_get_base(adap), chip, addr, alen, buffer, len); 557 } 558 559 /* 560 * Test if a chip at a given address responds (probe the chip) 561 */ 562 static int mxc_i2c_probe(struct i2c_adapter *adap, uint8_t chip) 563 { 564 return bus_i2c_write(i2c_get_base(adap), chip, 0, 0, NULL, 0); 565 } 566 567 int __enable_i2c_clk(unsigned char enable, unsigned i2c_num) 568 { 569 return 1; 570 } 571 int enable_i2c_clk(unsigned char enable, unsigned i2c_num) 572 __attribute__((weak, alias("__enable_i2c_clk"))); 573 574 void bus_i2c_init(int index, int speed, int unused, 575 int (*idle_bus_fn)(void *p), void *idle_bus_data) 576 { 577 int ret; 578 579 if (index >= ARRAY_SIZE(mxc_i2c_buses)) { 580 debug("Error i2c index\n"); 581 return; 582 } 583 584 mxc_i2c_buses[index].idle_bus_fn = idle_bus_fn; 585 mxc_i2c_buses[index].idle_bus_data = idle_bus_data; 586 587 ret = enable_i2c_clk(1, index); 588 if (ret < 0) { 589 debug("I2C-%d clk fail to enable.\n", index); 590 return; 591 } 592 593 bus_i2c_set_bus_speed(&mxc_i2c_buses[index], speed); 594 } 595 596 /* 597 * Init I2C Bus 598 */ 599 static void mxc_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr) 600 { 601 bus_i2c_init(adap->hwadapnr, speed, slaveaddr, NULL, NULL); 602 } 603 604 /* 605 * Set I2C Speed 606 */ 607 static u32 mxc_i2c_set_bus_speed(struct i2c_adapter *adap, uint speed) 608 { 609 return bus_i2c_set_bus_speed(i2c_get_base(adap), speed); 610 } 611 612 /* 613 * Register mxc i2c adapters 614 */ 615 U_BOOT_I2C_ADAP_COMPLETE(mxc0, mxc_i2c_init, mxc_i2c_probe, 616 mxc_i2c_read, mxc_i2c_write, 617 mxc_i2c_set_bus_speed, 618 CONFIG_SYS_MXC_I2C1_SPEED, 619 CONFIG_SYS_MXC_I2C1_SLAVE, 0) 620 U_BOOT_I2C_ADAP_COMPLETE(mxc1, mxc_i2c_init, mxc_i2c_probe, 621 mxc_i2c_read, mxc_i2c_write, 622 mxc_i2c_set_bus_speed, 623 CONFIG_SYS_MXC_I2C2_SPEED, 624 CONFIG_SYS_MXC_I2C2_SLAVE, 1) 625 #ifdef CONFIG_SYS_I2C_MXC_I2C3 626 U_BOOT_I2C_ADAP_COMPLETE(mxc2, mxc_i2c_init, mxc_i2c_probe, 627 mxc_i2c_read, mxc_i2c_write, 628 mxc_i2c_set_bus_speed, 629 CONFIG_SYS_MXC_I2C3_SPEED, 630 CONFIG_SYS_MXC_I2C3_SLAVE, 2) 631 #endif 632 633 #ifdef CONFIG_SYS_I2C_MXC_I2C4 634 U_BOOT_I2C_ADAP_COMPLETE(mxc3, mxc_i2c_init, mxc_i2c_probe, 635 mxc_i2c_read, mxc_i2c_write, 636 mxc_i2c_set_bus_speed, 637 CONFIG_SYS_MXC_I2C4_SPEED, 638 CONFIG_SYS_MXC_I2C4_SLAVE, 3) 639 #endif 640 641 #else 642 643 static int mxc_i2c_set_bus_speed(struct udevice *bus, unsigned int speed) 644 { 645 struct mxc_i2c_bus *i2c_bus = dev_get_priv(bus); 646 647 return bus_i2c_set_bus_speed(i2c_bus, speed); 648 } 649 650 static int mxc_i2c_probe(struct udevice *bus) 651 { 652 struct mxc_i2c_bus *i2c_bus = dev_get_priv(bus); 653 fdt_addr_t addr; 654 int ret; 655 656 i2c_bus->driver_data = dev_get_driver_data(bus); 657 658 addr = dev_get_addr(bus); 659 if (addr == FDT_ADDR_T_NONE) 660 return -ENODEV; 661 662 i2c_bus->base = addr; 663 i2c_bus->index = bus->seq; 664 665 /* Enable clk */ 666 ret = enable_i2c_clk(1, bus->seq); 667 if (ret < 0) 668 return ret; 669 670 ret = i2c_idle_bus(i2c_bus); 671 if (ret < 0) { 672 /* Disable clk */ 673 enable_i2c_clk(0, bus->seq); 674 return ret; 675 } 676 677 /* 678 * Pinmux settings are in board file now, until pinmux is supported, 679 * we can set pinmux here in probe function. 680 */ 681 682 debug("i2c : controller bus %d at %lu , speed %d: ", 683 bus->seq, i2c_bus->base, 684 i2c_bus->speed); 685 686 return 0; 687 } 688 689 static int mxc_i2c_probe_chip(struct udevice *bus, u32 chip_addr, 690 u32 chip_flags) 691 { 692 int ret; 693 struct mxc_i2c_bus *i2c_bus = dev_get_priv(bus); 694 695 ret = i2c_init_transfer(i2c_bus, chip_addr, 0, 0); 696 if (ret < 0) { 697 debug("%s failed, ret = %d\n", __func__, ret); 698 return ret; 699 } 700 701 i2c_imx_stop(i2c_bus); 702 703 return 0; 704 } 705 706 static int mxc_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs) 707 { 708 struct mxc_i2c_bus *i2c_bus = dev_get_priv(bus); 709 int ret = 0; 710 ulong base = i2c_bus->base; 711 int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ? 712 VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT; 713 714 /* 715 * Here the 3rd parameter addr and the 4th one alen are set to 0, 716 * because here we only want to send out chip address. The register 717 * address is wrapped in msg. 718 */ 719 ret = i2c_init_transfer(i2c_bus, msg->addr, 0, 0); 720 if (ret < 0) { 721 debug("i2c_init_transfer error: %d\n", ret); 722 return ret; 723 } 724 725 for (; nmsgs > 0; nmsgs--, msg++) { 726 bool next_is_read = nmsgs > 1 && (msg[1].flags & I2C_M_RD); 727 debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len); 728 if (msg->flags & I2C_M_RD) 729 ret = i2c_read_data(i2c_bus, msg->addr, msg->buf, 730 msg->len); 731 else { 732 ret = i2c_write_data(i2c_bus, msg->addr, msg->buf, 733 msg->len); 734 if (ret) 735 break; 736 if (next_is_read) { 737 /* Reuse ret */ 738 ret = readb(base + (I2CR << reg_shift)); 739 ret |= I2CR_RSTA; 740 writeb(ret, base + (I2CR << reg_shift)); 741 742 ret = tx_byte(i2c_bus, (msg->addr << 1) | 1); 743 if (ret < 0) { 744 i2c_imx_stop(i2c_bus); 745 break; 746 } 747 } 748 } 749 } 750 751 if (ret) 752 debug("i2c_write: error sending\n"); 753 754 i2c_imx_stop(i2c_bus); 755 756 return ret; 757 } 758 759 static const struct dm_i2c_ops mxc_i2c_ops = { 760 .xfer = mxc_i2c_xfer, 761 .probe_chip = mxc_i2c_probe_chip, 762 .set_bus_speed = mxc_i2c_set_bus_speed, 763 }; 764 765 static const struct udevice_id mxc_i2c_ids[] = { 766 { .compatible = "fsl,imx21-i2c", }, 767 { .compatible = "fsl,vf610-i2c", .data = I2C_QUIRK_FLAG, }, 768 {} 769 }; 770 771 U_BOOT_DRIVER(i2c_mxc) = { 772 .name = "i2c_mxc", 773 .id = UCLASS_I2C, 774 .of_match = mxc_i2c_ids, 775 .probe = mxc_i2c_probe, 776 .priv_auto_alloc_size = sizeof(struct mxc_i2c_bus), 777 .ops = &mxc_i2c_ops, 778 }; 779 #endif 780